JPH0243742A - Manufacture of compound semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding the improvement of a method for manufacturing a compound semiconductor device that uses a two-dimensional electron gas layer as a channel, which is generated by using selective doping technology, for example, it is possible to By electrically separating the substrate and active area in both directions,
With the aim of contributing to the realization of high integration, a high-resistance interlayer separation layer is formed on the entire surface by implanting oxygen ions either directly on a semi-insulating compound semiconductor substrate or after epitaxially growing a compound semiconductor layer. and then growing a necessary compound semiconductor layer such as an active layer on the core isolation layer.

[Industrial application field]

The present invention relates to an improvement in a method for manufacturing a compound semiconductor device in which a channel is a two-dimensional electron gas layer generated by using, for example, selective doping technology.

In order to improve the operating speed of semiconductor devices, the practical use of compound semiconductors such as GaAs-based semiconductors is progressing, and the so-called selective doping technology, which spatially separates the impurity doping region and the carrier movement region, is being applied. A high electron mobility field effect transistor (high electron mobility field effect transistor) uses electrons in a two-dimensional state as carriers.
2. Description of the Related Art Semiconductor devices such as a low power transistor (HEMT) have been developed.

As such semiconductor devices become highly integrated, it is becoming a problem that electrical interference occurs between adjacent semiconductor devices, resulting in mutual malfunction of the semiconductor devices.

[Conventional technology]

In the conventional method for manufacturing the above type of semiconductor devices, as a means for separating adjacent semiconductor devices, (1) etching and scraping off the space between the semiconductor devices to form a gap (recess method); (2) ) Oxygen is implanted between semiconductor devices using ion implantation,
Methods such as forming a high resistance region (oxygen implantation method) are being carried out.

When using the recess method (1), the electrodes and
There are manufacturing difficulties because it is necessary to pass through a gap to form the wiring. However, the oxygen injection method (2) is currently widely used because it is effective in achieving high integration.

[Problem to be solved by the invention]

In the conventional technology, as described above, electrical isolation between semiconductor devices is mainly considered in the horizontal direction, and sufficient measures are not taken between the substrate and the element, that is, in the vertical direction.

However, in recent years, it has been found that semi-insulating GaAs substrates and non-doped GaAs buffer layers, which are frequently used as substrates, also cause electrical interference between adjacent semiconductor devices.

Currently, for example, semi-insulating GaAs substrates are
Doping Cr-○ into the doped state increases the resistivity to 10
7 [Ω・ω] or more, and although attempts have been made to use an A/GaAs layer as a buffer layer, it is insufficient as an electrical isolation means for high integration. be.

The present invention attempts to contribute to the realization of high integration by electrically separating the substrate and the active region not only in the lateral direction but also in the vertical direction.

[Means to solve the problem]

FIG. 1 shows a semiconductor device i (H
EMT) shows a cutaway side view of the main parts.

In the figure, ■ is a semi-insulating GaAs substrate, 2 is a GaAsJ isolation layer formed by implanting oxygen, 3 is a non-doped GaAs active layer, and 4 is an AlGa doped with Si.
As electron supply layer, 5 is a GaAs contact layer doped with St, 6 is a two-dimensional electron gas layer, 7 is an isolation layer formed by implanting oxygen, S3+ and 8, 2 are source electrodes, 8G+ and 8G□ 801, 8 and 2 are drain electrodes, and 10 is an alloyed region.

When manufacturing this semiconductor device, a semi-insulating GaAs substrate 1 or a non-doped GaAs layer (
Glabella separation layer 2 made of high resistance by injecting oxygen into (not shown)
After forming the active layer 3, electron supply layer 4, contact layer 5, etc., the active layer 3, electron supply layer 4, contact layer 5, etc. are grown in order, and then oxygen is similarly implanted to form the element isolation layer 7.

By doing this, each completed element is surrounded by layers with high resistance, so electrical interference will not occur between them.

As described above, in the method for manufacturing a compound semiconductor device according to the present invention, oxygen ions are implanted into a semi-insulating compound semiconductor substrate (for example, a semi-insulating GaAs substrate) to form a high-resistance glabella separation layer (for example, a glabella separation layer) on the entire surface. forming an active layer (e.g. GaA) on the interlayer separation layer;
s active layer 3), or a step of growing a compound semiconductor layer (for example, a non-doped GaAs layer IA) on a semi-insulating compound semiconductor substrate.
), followed by a step of implanting oxygen ions into the compound semiconductor layer and the semi-insulating compound semiconductor substrate to form a high-resistance interlayer separation layer on the entire surface, and then an active layer on the interlayer separation layer. and growing a necessary compound semiconductor layer such as a layer.

[Effect]

In the semiconductor device obtained by adopting the above-mentioned means, the substrate and the active region are electrically isolated not only in the horizontal direction but also in the vertical direction, so that electrical isolation between the elements is achieved. There is almost no physical interference, and there is no performance deterioration even with high integration.

〔Example〕

Figures 2 to 5 represent cutaway side views of the main parts of the HEMT at key points in the process for explaining one embodiment of the present invention.
This will be explained with reference to these figures.

Note that the same symbols as those used in FIG. 1 indicate the same parts or have the same meaning.

Refer to Figure 2 (11) A semi-insulating GaAs substrate 1 is placed in an ion implantation chamber of an ion implantation device, and the dose is set to 5 x 1, for example.
0 ” (Cm-”), acceleration energy for example 5
Oxygen ions are implanted at a level of about 0 [KeV], and the interlayer separation layer 2 is formed to a depth of about 1000 (people).
form.

(2) The substrate 1 is grown by molecular beam epitaxial growth (molec).
It was placed in an MBE growth chamber in an ular beam epitaxy (MBE) apparatus, and the temperature was set to 680 ('C).
), the non-doped GaAs active layer 3 is grown to a thickness of about 0.4 [μm], for example, and then doped with Si to a thickness of about 1X1018 (, lJ-') to a thickness of about 0.09 [μm], for example. ) of AlGaAs electron supply layer 4, and then Si is grown, for example, with lX1018
am −' ) doping thickness, for example 0. Ol
A GaAs contact layer 4 of about [μm] is grown. It goes without saying that when the semiconductor layers are stacked in this manner, a two-dimensional electron supply layer 6 is generated on the active layer 3 side at the interface between the active layer 3 and the electron supply layer 4.

See Figure 4. (3) By applying a resist process in ordinary photolithography technology, a photoresist mask with an opening in the area where the element isolation layer is to be formed is formed, and then the substrate is removed. 1 is again placed in the ion implantation chamber of the ion implantation device, and the dose is adjusted to, for example, I x 10I3 (
cm-”), and the acceleration energy is, for example, 150 (KeV
), oxygen ions are selectively implanted to form an interelement isolation layer 7 that reaches the interlayer isolation layer 2.

See FIG.
, drain bridges 8, 1, 81) 2, etc. are formed, and alloying treatment is performed to establish ohmic contact between them and the two-dimensional electron gas layer 6, and then the gate electrode 8 is formed.
Complete by forming G+ and 8Gt. In addition, symbol 10
is the same as described above, indicating the alloyed region generated in the alloying process.

Figures 6 to 10 represent cutaway side views of main parts of the HEMT at key points in the process for explaining other embodiments of the present invention, and the following description will be made with reference to these figures. . Note that the same symbols as those used in FIGS. 1 to 5 indicate the same parts or have the same meanings.

Refer to Figure 6 (a semi-insulating GaAs substrate l with an 11 plane index of (100) is placed in a growth chamber of an MBE apparatus, and the temperature is set to 680°C.
('C), a non-doped GaAs layer IA having a thickness of, for example, about 0°1 [μm] is grown.

(2) Place the substrate 1 in an ion implantation chamber of an ion implantation apparatus without exposing it to the atmosphere, and set the dose amount to, for example, I
Oxygen ions are implanted into the entire surface with an acceleration energy of about 10" (cm-23), for example, about 50 (KeV), and a glabellar separation N with a thickness of about 0.2 [μm] is formed.
form 2. Therefore, the interlayer separation layer 2 is made of non-doped G.
It is formed by going beyond the interface between the aAs layer IA and the substrate 1 and entering the base Fil side.

(3) Place the substrate 1 in the growth chamber of the MBE apparatus again without exposing it to the atmosphere, maintain the temperature at 680 ('C), and grow a non-woven film with a thickness of, for example, about 0.4 [μm].・Doped GaA
s active layer 3 is grown and then Si is grown, for example I
Doping thickness of about 1010 (Cm-'), for example 0
．． An AlGaAs electron supply layer 4 of about 0.09 (μm) is grown, and then Si is grown using, for example, IXI OI8 (c
m-3) doped thickness, for example, 0.01 (μm
] A GaAs contact layer 4 is grown. In this case as well, a two-dimensional electron supply layer 6 is generated on the active layer 3 side at the interface between the active layer 3 and the electron supply layer 4.

(4) Place the substrate 1 again in the ion implantation chamber of the ion implantation device, and adjust the dose amount to, for example, lXlX1013 ("2
) degree, and the acceleration energy is, for example, 150 (KeV
), oxygen ions are selectively implanted to form an interelement isolation layer 7 that reaches the interlayer isolation layer 2.

When performing this selective ion implantation, it is better to use a focused ion beam if you do not want to use a resist process in photolithography technology, but at this stage, the growth of each semiconductor layer has been completed. Therefore, board 1
There is no problem in forming a photoresist mask by exposing the photoresist to the atmosphere.

(5) By applying conventional techniques, recess formation in the gate region, formation of source electrodes 8, 1 and 8.2, train electrodes 801 and 8, 2, etc. An alloying process is performed to establish ohmic contact with the dimensional electron gas layer 6, and then gate electrodes 8.1 and 8.2 are formed to complete the process. Note that symbol 10 is an alloying region.

In the case of relying on any of the above embodiments, it is completed)-(
No electrical interference occurred during EMT.

The main difference between the first and second embodiments is that non-doped GaAs1i+A was formed in the second embodiment.

In this second embodiment, the temperature of the substrate 11 is sufficiently high, and
It is effective to carry out when there are circumstances where thermal etching cannot be carried out over a sufficiently long period of time.

In this case, after forming the non-doped GaAs layer IA on the base +&l, oxygen ions are implanted, and then the non-doped GaAs layer IA is formed on the base +&l.
It is preferable to use a system that allows the steps leading to the growth of each semiconductor layer, such as the doped GaAs active layer 3, to proceed without being exposed to the atmosphere even once.

FIG. 11 is an explanatory diagram of main parts showing a comprehensive system combining an MBE device and an ion implantation device that can be used to achieve good results when implementing the present invention.

In the figure, 11 is a board exchange room, 12 is a board transfer room, 1
Reference numeral 3 indicates a substrate transfer rod, 14 an MBE growth chamber, 15 an ion accelerator, and 16 an ion implantation chamber.

To carry out the present invention using this system, the substrate 1 is moved back and forth between the MBE growth chamber 14 and the ion implantation chamber 16 to proceed with growth and processing. When such a system is used, the process proceeds without exposing the substrate 1 to the atmosphere, so the interface state between each semiconductor layer is good, and the resulting semiconductor device has very good characteristics.

〔Effect of the invention〕

In the method for manufacturing a compound semiconductor device according to the present invention, a high-resistance interlayer separation layer is formed by implanting oxygen ions on a semi-insulating compound semiconductor substrate, either directly or after epitaxially growing a compound semiconductor layer. Then, necessary semiconductor layers such as an active layer are grown on the interlayer separation layer.

By employing the above structure, in the semiconductor device obtained, the substrate and the active region are electrically isolated not only in the horizontal direction but also in the vertical direction, so that electrical isolation between the elements is achieved. There is almost no physical interference (there is no performance deterioration even with high integration).

[Brief explanation of the drawing]

FIG. 1 is a cutaway side view of the main parts of a semiconductor device for explaining the present invention in detail, and FIGS. 2 to 5 are main parts of the HEMT at important process points for explaining one embodiment of the present invention. cut side view,
6 to 10 are cutaway side views of main parts of the HEMT at important process points for explaining other embodiments of the present invention,
FIG. 11 shows an explanatory view of the main parts of a comprehensive system combining an MBE device and an ion implantation device for carrying out the present invention. In the figure, ■ is a semi-insulating GaAs substrate, 2 is a GaAs interlayer isolation layer formed by implanting oxygen, 3 is a non-doped GaAs active layer, and 4 is an A6GaA substrate doped with Si.
s electron supply layer, 5 is a Si-doped GaAs concrete layer, 6 is a two-dimensional electron gas layer, 7 is an inter-element isolation layer formed by implanting oxygen, 8, 1 and 85□ are source electrodes, 8G+ and 86 □ is the gate electrode, 8 n+! 8 and 2 are drain electrodes, and 10 is an alloyed region, respectively. Patent applicant: Fujitsu Ltd. Representative Patent Attorney Shoji Aitani

Claims (2)

[Claims] (1) A step of implanting oxygen ions into a semi-insulating compound semiconductor substrate to form a high-resistance interlayer separation layer over the entire surface, and then a step of growing necessary compound semiconductor layers such as an active layer on the interlayer separation layer. A method for manufacturing a compound semiconductor device, comprising: (2) A step of epitaxially growing a compound semiconductor layer on a semi-insulating compound semiconductor substrate, and then implanting oxygen ions into the compound semiconductor layer and the semi-insulating compound semiconductor substrate to form a high-resistance interlayer separation layer on the entire surface. 1. A method for manufacturing a compound semiconductor device, comprising: a step of growing a necessary compound semiconductor layer such as an active layer on the interlayer separation layer.