JPH0254177A - Peak value detection circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a peak value detection circuit, and an object of the present invention is to inexpensively realize a peak value detection circuit for analog signals that follows temporally varying peak values. an AD converter that converts into a digital signal, a reversible counter, and compares the output value of the AD converter with the output value B of the counter, and outputs a first comparison output signal when A > 8 state; a comparison circuit that outputs a second comparison output signal when in the B state; an increase mode setting section that sets the reversible counter to an increase mode by the first comparison output signal and causes it to count the first clock; and a reduction mode setting unit that sets the reversible counter to a reduction mode by a comparison output signal of and reduces the count value of the reversible counter by a second clock obtained by dividing the first clock,
By comparing the output value of the reversible counter and the output value of the AD converter, the count value of the reversible counter is made to follow the peak value by adding and subtracting the first and second clock signals having different periods. Configure.

[Industrial application field]

The present invention relates to an improvement in a peak value detection circuit that follows temporally varying analog peak values.

Optical reading devices that read image signals such as marks and characters detect the white level peak value of the analog signal read from the image sensor and control the lighting.

White level correction, etc. are performed to improve reading accuracy.

This peak value is detected in the white area of conventional media, but like a bankbook, there is a step before and after the center hold.
Furthermore, in the case of a medium with background pattern printing, the peak value of this portion is lower than that of the white background portion, so it is necessary to detect the peak value that follows this.

For this reason, a conventional method has been adopted in which the charge accumulated in the hold capacitor of the analog peak value detection circuit is leaked using a high resistance, and when a peak value higher than the leaked peak value is input, it is held. Although,
In order to always leak at a constant rate with respect to changes in temperature and humidity, the leakage of the analog peak value detection circuit itself must be kept small, and expensive and expensive measures such as the use of highly insulating components and careful mounting are required. There is a problem.

Therefore, a simple tracking type peak value detection circuit is required.

[Conventional technology]

FIG. 5 is a block diagram of the reading device, FIG. 6 is an explanatory diagram of a passbook reading method, FIG. 7 is an explanatory diagram of white level fluctuations in passbook reading, and FIG. 8 is a diagram showing an example of a conventional analog peak value detection circuit.

Fig. 5 shows a block diagram of an optical reading device for a bankbook, etc., in which an image of the medium 1 is formed on a one-dimensional image sensor 2 while feeding a medium 1 on which marks, characters, etc. are printed. It scans and outputs a directional image signal in synchronization with the clock.

This read image signal (analog signal) is
It is converted into a digital signal by the converter 5, compared with a predetermined voltage, and binarized.

Here, the peak value detection circuit 6 detects a white level peak value (hereinafter simply referred to as peak value) of a white background area provided at the beginning of the medium 1.
This peak value is used to control the illumination by the lamp control unit 7 during reading of the white background area, and the peak value held under suitable illumination is used as the reference voltage of the AD converter 5 to control the white level. Used for correction.

When the medium 1 is a passbook, as shown in Figure 6, there is a step before and after the center hold (binding part), so the distance between the lamp 3 and the passbook surface is different, and the required peak value changes. In the area where the tint block is printed, reflected light also decreases and the peak value decreases.

This pattern is shown in FIG. 7, and it is clear that accurate white level correction can be performed by gently following the fluctuation of the peak value.

As a tracking method, a method is adopted in which the peak value held in the white area is decreased at a constant rate, and if there is a peak value higher in level than the decreased peak value, this value is retained.

FIG. 8 shows an example of an analog peak value detection circuit for correcting the forward voltage of the diode D, and is configured so that the peak voltage charged in the hold capacitor C is leaked through a high resistance R.

[Problem to be solved by the invention]

As explained above, the conventional method of detecting the peak value corresponding to the reading area is to leak the hold capacitor of the analog peak value detection circuit using a high resistance, so that it is stable against changes in temperature and humidity. In order to prevent leakage, it is necessary to reduce the leakage of the analog peak value detection circuit itself, and there are expensive issues such as the use of highly insulating components and mounting considerations. Since even bits leaked, there was an issue of inaccuracy.

In view of the above problems, it is an object of the present invention to provide a tracking type peak value detection circuit that operates stably and is inexpensive.

[Means to solve the problem]

As shown in the figure, an AD converter (10) that converts an analog signal (50) to be detected into a digital signal, a reversible counter (11), an output value A of the AD converter, and an output value B of the counter. and when A > B state, the first comparison output signal (65)
is output, and the second comparison output signal (66
), and an increase mode setting unit (20) that sets the reversible counter (11) to an increase mode by a first comparison output signal (65) and causes it to count a first clock (60). Then, the reversible counter (11) is set to a decreasing mode by a second comparison output signal (66), and a second clock (6) is generated by dividing the first clock (60).
1), a reduction mode setting section (21) is provided to reduce the count value of the reversible counter (11).

[For production]

First comparison output signal (A > 8) 55 is comparison circuit 1
2, the increase mode setting unit 20 selects this first
The reversible counter 11 is set to the increase mode using the comparison output signal 65 of , and the first clock signal 60 is counted (up-counted), and when the second comparison output signal (A<B) 66 is output, the reversible counter 11 is set to the increase mode. The mode setting section 21 is a reversible counter 1
1 is set in a decreasing mode, and the second clock signal 61 is used to decrease (down count).

If, for example, a reading clock of an image sensor is used as the first clock 0, the output of the reversible counter 11 will quickly reach the voltage value of the analog signal being input, and the first clock 60 will be divided into multiple parts. If this is used as the second clock 61, the value of the reversible counter 11 can be gradually decreased.

Note that when the output value of the AD converter 10 and the output value B of the reversible counter 11 are the same, that is, when A = B, the reversible counter 11 does not perform a counting operation and holds the counted value as it is.

Furthermore, as a method of removing the reduction due to the black dummy bit of the -dimensional image sensor, the second comparison output signal 66
The second comparison output signal 66 after reading la for a predetermined time (more than dummy bits) is used to set the reduction mode.

In addition, in order to prevent the peak value from increasing due to white scratches on the image sensor, the first comparison output signal 65 after the first comparison output signal 65 has continued for a predetermined period of time (for the allowable number of white scratches) is used. Set to increase mode.

As described above, the reversible counter 11 can detect and hold the peak value while smoothly following it.

[Embodiment] A block diagram of the Dn circuit of the embodiment, FIG. 3 is an increase mode operation time chart, and FIG. 4 is a decrease mode operation time chart.

In this embodiment, the first comparison output signal (hereinafter referred to as A>B signal) 65 continues after the Rokurotsuta division clock is the read clock of the image sensor (hereinafter simply referred to as Kuronkuro 0 and corresponds to the first Kukotoku). An example will be shown in which the increase mode is set by 6G and the decrease mode is set by the second comparison output signal (hereinafter referred to as A<B signal) 6G that continues for m clocks.

In Fig. 1, numeral 10 is an 8-bit (255-level) AD converter that converts the analog signal 50 read out from the dimensional image sensor into digital, and numeral 11 is an 8-bit or more reversible counter that converts its count value (output). The value B) is output as the peak signal 52, and 12 is a comparison circuit that outputs the AD converter output signal 51 (output value A).
) and the peak value signal 52 output from the reversible counter 11
(output value B), A>8 signal 65 or A<
The one that outputs the B signal 66, 13 is a 0m circuit that counts m clocks 60 from the rising edge of the A < B signal 66, and after that, the A < B signal 6
14 is a Dn circuit that counts n clocks 60 from the rising edge of the A > [1 signal 65 and outputs the subsequent A > 8 signal 65; 15 is a DV circuit that outputs the clock 60 is divided into 17K, and the second clock (hereinafter the divided clock CLO (JD)
16 is a launch circuit that latches the B signal 66 output from the DI+1 circuit 13 with CLOCKD61.
17 is an AND circuit, which connects the output of the latch circuit 16 and CLOC.
AND KD61 and output the DOWN signal 63,
18 is a comparison circuit that sets the reversible counter 11 to a decreasing mode, and determines whether the output value B of the held peak signal 52 is between the upper limit setting value S1 and the lower limit setting value S2; When it is larger than the upper limit set value S1, it outputs 0VER, when it is between the upper limit set value S1 and lower limit set value S2, it outputs NORMAL, and when it is smaller than the lower limit set value, it outputs UNDER signal. .

In Figure 2, four DTYPE FFs (flip-flops) 22 are connected in cascade, and each DTYPE FF 2
This shows an example of a Dn circuit in which the outputs of 2 are ANDed by the AND circuit 23, and when the A > B signal 65 continues for 4 clocks, the IIP signal 62 is output, and the A < B signal 6
At the same time as the output of 5 is completed, the up multiplier signal output is stopped.

Note that the Dm circuit 13 is also similar, and has m stages of DTYPE FF.
Consists of 22.

Here, the values of m and n are determined as follows.

Now, if the number of cells in the image sensor is 2, and 16 cells of black dummy bits are added at the beginning of the readout, the m
The value of n is set to 32, and n is set to 4 in order to ignore white scratches specific to image sensors. Furthermore, in order to reduce the level by a maximum of 4 in one line, k=528.

Examples of operation when the above values are set are shown in FIGS. 3 and 4.

An example of operation will be explained below.

[Increase mode] (See Figure 3) As a result of comparing the output value A of the AD converter 10 and the output value B of the reversible counter 11, when A>B, the comparison circuit 12 outputs the A>B signal 65. After the continuation of 4 clocks is detected by the Dn circuit 14, the subsequent A>R signal 65 is
It is output as a P signal 62, and the reversible counter 11 is set to increment mode.

During the second increment mode, reversible counter 11 counts and adds clocks 60.

As a result, the reversible counter 11 counts until its count value matches the current output value A of the AD converter, and thereafter holds that value until it enters the decreasing mode.

[Decrease mode] (See Figure 4) When the comparator circuit 12 outputs the B signal 66, m
After continuing for 1 minute, A < B signal 66 is DIl + circuit 13
A DOWN signal 63, which is an AND of this signal and CLOCKD 61, is used to set the reduction mode.

This DOWN signal 63 is output from CLO(JD61 to A<
It is a cutout of the B signal 66 and is synchronized with the clock 60, so if A < B signal 66, set the decrease mode and C
This is equivalent to counting down with LOCKD61.

In addition, when ^=B in the above operation, the reversible counter 11
No counting operation is performed.

As described above, when the output of the AD converter 10 is large, the peak value is quickly detected by the clock 60, and when the output of the 8-digit converter 10 is small, it is gradually decreased by the CLOCKD 61, and the reversible counter 11 that has decreased thereafter. When there is an output from the AD converter that is larger than the output value B, a peak value is detected and held in accordance with the output, and is output as a peak signal 52 to a white level correction circuit or the like.

[Lighting control]

The peak signal 52 (output value B) detected and held by the reversible counter 11 is compared with the upper limit setting value S1 and the lower limit setting value s2 by the comparator circuit 18, and depending on the peak value level, 0VER output and NORMAL output, respectively.
Output, IJNDBR output is output and lighting is controlled.

In an actual reading device, the light source of the reading device is turned on at a constant level such that the white portion of the medium falls within the reading range of the sensor, and increases to an appropriate level as the white portion is read. Thereafter, the white level peak value of the white background portion is held in the reversible counter 11 under this lighting level, and then the white level peak value gradually decreases in accordance with the reading area of the medium.

〔Effect of the invention〕

The present invention uses a digital circuit to realize a peak value detection circuit that reduces the held peak value at a fixed rate and follows the white level corresponding to the reading area. The characteristics of the sensor can be configured to prevent malfunctions due to defective elements. ■ Operation is stable because it is not affected by temperature and humidity. ■ The device is less expensive because high insulation measures are not required.

Fig. 2 is a block diagram of the Dn circuit of the embodiment, Fig. 3 is an increase mode operation time chart, Fig. 4 is a decrease mode operation time chart, Fig. 5 is a block diagram of the reading device, and Fig. 6 is a passbook reading method. Explanatory diagram, Figure 7 is an explanatory diagram of white level fluctuation in bankbook reading, Figure 8
The figure is a block diagram of a conventional analog peak value detection circuit. In the figure, 1 is a medium 1 passbook, 2 is a one-dimensional image sensor, 3 is a light source, a lamp, 10 is an AD converter, 11 is a reversible counter, 1
2 is a comparison circuit, 13 is a 0m circuit, 14 is an on circuit, 15
is a frequency divider circuit DV, 16 is a launch circuit, 17 is an AND circuit, 20 is an increase mode setting section, 21 is a decrease mode setting section,
18 is a comparison circuit, 22 is a D TYPE FF, 23 is an AND circuit, 50 is an analog signal, 51 is an AD converter output signal, 52 is a peak signal, 60 is a clock, a first clock, 61 is a frequency-divided clock CLOCKD, 2nd
clock, 62 is an up times signal 63 is a down signal, 6
5 is A>8 signal, first comparison output signal, 66 is A<B
signal, the second comparison output signal.

Roasted beard J
1. Ward? ■ →− ヲ3.7: LP mogo F゛kai? , 9 Gumte 7-to (Picture vine 3 Diagram mode tH lower time ke V-F Lo spear 4 Diagram 1 Sushihi 1) Mouth/Soft chain W-5'' Kusarimine Otsu■

Claims (1)

[Claims] 1. A peak value detection circuit that tracks and detects the peak value of an analog signal that fluctuates over time, the circuit comprising:
AD converter (10) that converts 50) into a digital signal
and a reversible counter (11), which compares the output value A of the AD converter and the output value B of the counter, outputs a first comparison output signal (65) when A>B, and outputs a first comparison output signal (65) when A<B. Second comparison output signal (66) when in B state
a comparison circuit (12) that outputs a first comparison output signal (
an increase mode setting unit (20) that sets the reversible counter (11) to an increase mode using the second comparison output signal (65) and causes the reversible counter (11) to count the first clock (60); is set to decrease mode and the first
A second clock (61) obtained by dividing the clock (60) of
A reduction mode setting unit (21) is provided to reduce the count value of the reversible counter (11) by comparing the output value of the reversible counter (11) and the output value of the AD converter to determine whether the period is different. A peak value detection circuit characterized in that the count value of the reversible counter (11) is made to follow the peak value by adding and subtracting, respectively, using first and second clock signals. 2. At least one of the increase mode setting section and the decrease mode setting section is provided with means for outputting a comparison output signal after a predetermined period of time and setting the mode of the reversible counter. The peak value detection circuit according to claim 1.