JPH0258274A - semiconductor equipment - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device equipped with an electrostatic protecting circuit assuring a sufficient electrostatic breakdown strength by a method, in an integrated circuit constituted by using MOSFET's having LDD structure, an N<+> region is formed by using phosphorus impurity, only in an MOSFET constituting the electrostatic protecting circuit. CONSTITUTION:On the same semiconductor substrate 1, the following are arranged; an internal circuit 2 formed by MOSFET's having LDD structure to relieve drain electric field, and an electrostatic protecting circuit 3 to protect the internal circuit 2 from external abnormal signals. The source.drain of the LDD transistors of the above internal circuit 2 has high concentration diffusion regions 10, 11 of arsenic. The source.drain region of the LDD transistor in the above electrostatic protecting circuit 3 has high concentration diffusion regions 12, 13 of phosphorus. Since the average range distance to the semiconductor substrate 1 and the diffusion coefficient of arsenic and those of phosphorus are mutually different, the N<+> diffusion layer of the electrostatic protecting circuit 3 is about two times as deep and about one-half wide as the N<+> diffusion layer of the internal circuit 2. Thereby the electrostatic breakdown strength is remarkably improved.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to the maintenance of the input or output terminal of a semiconductor integrated circuit configured using MOSFETs, and particularly relates to the maintenance of an LDD for alleviating the drain electric field. It relates to a semiconductor device with a structure.

[Prior Art] Due to the miniaturization of device structures, a high electric field is generated inside the device, and deterioration development due to hot carriers occurs.

As a countermeasure to this, a region is formed from the gate edge and is formed by arsenic impurities. An LDD structure in which the region is formed at a position away from the gate is generally employed.

On the other hand, the input or output terminals of semiconductor integrated circuits constructed using MOSFETs have extremely high impedance, so if a high voltage such as static electricity is applied, the MOSFET
It is well known that the gate part of SFET is easily broken. For this reason, an electrostatic protection circuit formed by a clamp MCl5 element and an input diffused resistor is used.

However, regarding the output terminal, since a large-area parasitic diode is formed between the source and drain/region of the output MOS Pg T and the semiconductor substrate, it is also possible to use the aforementioned protection circuit or replace it with an output MO8FET. be.

[Problems to be Solved by the Invention] Normally, MOSFETs constituting this protection circuit are MOSFETs with an I, Dl) structure, similar to the internal circuit, but due to the effect of the loop region formed from the gate end, ,
Compared to conventional protection circuits using MOSFETs, there was a problem in that the electrostatic breakdown voltage was significantly lower.

The present invention solves the problems of conventional semiconductor devices by 1+.
The objective is to provide a semiconductor device having an electrostatic protection circuit that ensures sufficient electrostatic breakdown voltage.

[Means for Solving the Problems] The semiconductor device of the present invention includes an LDD that relaxes the drain electric field.
(In an integrated circuit composed of MOS FETs having four structures, MOS
It is characterized by the fact that it is made of pure Linnaeus.

[Example code] An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, an MO8 element 2 of an internal circuit and an electrostatic protection circuit 5 are formed on a semiconductor substrate 1. Internal circuit M
In O3 element 2, the symbol 10°11 is N+ due to arsenic.
A diffusion layer, typically formed by ion implantation. Reference numerals 6 and 7 are N- diffusion layers formed by ion implantation of phosphorus directly below the @wall spacer 16, which is generally called a sidewall. This N- diffusion layer has a lower concentration (, LDDt
It is made of IT. Conventionally, as shown in FIG. 2, for 1 electrostatic protection circuit 3ON + diffusion layers 212 and 215, arsenic ion implantation was performed to remove MO8 element 2O of the internal circuit.
N+ diffusion layer 10. 11 was formed at the same time. In the present invention, the N+ diffusion layer 1 of the MO3 element 2 of the internal circuit
The N+ diffusion layers 12 and 15 of the electrostatic protection circuit 3 are selectively formed by phosphorus implantation using the Otrin graphing technique.

Here, the N+ diffusion layer 13 serves both as a source and a diffusion resistance of the clamp MO8 element. As can be seen from FIG. 1, compared to the width of the N-diffusion layer of the internal circuit 2, the N
- The width of the diffusion Ri8,q is approximately 1/2. This is because the depth of the N+ diffusion layer at the final upstream is
This is because the amount of phosphorus is approximately twice that of arsenic.

By forming the N diffusion layer of the electrostatic protection circuit with phosphorus, the N+ diffusion depth is approximately doubled, the width of the N- diffusion layer is approximately halved, and the electrostatic breakdown strength is greatly improved. do. For example, in an electrostatic breakdown test of 200PF10Ω, in the case of an LDD structure in which the N diffusion layer of the electrostatic protection circuit is made of arsenic, the breakdown voltage is approximately 200v to 500v, whereas in the case of an LDD structure in which the N diffusion layer is made of phosphorus. 400v or more is humiliated.

[Effects of the Invention] As described above, according to the present invention, an LD that alleviates the drain electric field can be achieved without making significant changes to the semiconductor manufacturing process.
In a semiconductor integrated circuit having a nl structure, an electrostatic protection circuit having sufficient wp electric breakdown strength can be realized.

[Brief explanation of the drawing]

FIG. 1 is a main sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a main sectional view of a conventional semiconductor device. 1... Semiconductor substrate 2... MO8 element of internal circuit 3...
..... Electrostatic protection circuit 4 ..... P-type well 5 ..... Selective enablement film 6.7, 8, 9.28.29 ... ...N''' diffusion layer 10.11, 212, 213...N+ diffusion layer of arsenic impurity 12.15...N+ diffusion layer 4 of Linnaean impurity...
......Gate electrode 5...Gate oxide film 6...Side wall 7...Interlayer insulating film 8... ...At wiring 9...Protective film

Claims (1)

[Claims] On the same semiconductor substrate, an internal circuit formed by a MOSFET having an LDD structure that relieves the drain electric field;
The internal circuit has an electrostatic protection circuit for protecting the internal circuit from abnormal external signals, and the sources and drains of the LDD transistors of the internal circuit have high concentration diffusion regions of arsenic, and the LDD of the electrostatic protection circuit has A semiconductor device characterized in that the source and drain of a transistor have a high concentration diffusion region of phosphorus.