JPH0259729A - Active matrix display element - Google Patents

Abstract

PURPOSE:To reduce the fluctuation of the picture element potential of the title display element by increasing or decreasing both of the inter-gate drain capacity and auxiliary capacity in a specific ratio against the dislocation produced at the time of forming electrodes. CONSTITUTION:An electrode 18 for auxiliary capacity is electrically connected with a picture element electrode 15 together with a drain electrode 15 and the electrodes 18 and 16 have then same center line 19 which is almost parallel with a signal line 11. Then the ratio of the varying quantity of the gate-drain capacity to that of the auxiliary capacity associated with the positional deviation produced at the time of forming the electrodes is set within the range from (maximum value of gate-drain capacity):(minimum capacity value of displaying medium + auxiliary capacity) to (minimum value of gate-drain capacity):(maximum capacity value of displaying medium + auxiliary capacity). Therefore, both the gate-drain capacity and auxiliary capacity increase or decrease at an almost fixed rate against the dislocation at the time of the patterning of each electrode. Accordingly, the in-plane fluctuation of the decline of the drain potential and fluctuation at every lot can be suppressed easily without giving any trouble to the process.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an active matrix type display element, and particularly to its array configuration.

(Prior Art) In recent years, with regard to display elements using liquid crystals, active matrix type display elements with large capacity and high density are being actively developed and put into practical use for use in television displays, graphic displays, and the like. In such display elements, semiconductor switches are used as means for driving and controlling each pixel so that high contrast display without crosstalk can be performed. As semiconductor switches, thin film transistors (TFTs) and MIM elements formed on transparent insulating substrates are used because they are capable of transmissive display and are easy to increase in area.
Usually used.

FIG. 3 is an equivalent circuit diagram of the type of display element described above, in which a TPT is used as a switching element for directly driving each pixel, for example. In the figure, the gate electrode in the TPT is a scanning line 1, a signal line 2 is provided in a direction intersecting this line to serve as a source electrode in the TPT, and a display electrode is placed across the gate electrode to serve as a drain electrode. A so-called line sequential method is adopted in which when voltages are applied to the gate electrodes in sequence, the signal voltages of the signal lines 2 of each column are supplied to the display electrodes.

However, the load 3 coupled to the drain electrode, ie a dielectric display, for example a liquid crystal, has a capacitance CIC. Also, there is a parasitic capacitance cqd between the gate electrode and the drain electrode.
Therefore, after scanning the nth scanning line, the next (n+1)
When moving to the scanning of the th scanning line, charges are redistributed between CIC and Cgd, and a phenomenon occurs in which the display electrode potential Vd decreases.

Therefore, in order to alleviate this phenomenon, for example,
As described in JP-A-45219@ and JP-A-58-106860, a measure has been taken to provide a predetermined auxiliary capacitor IC3. Here, the potential Vx of the auxiliary capacitor C5 is set to the ground in JP-A-60-45219.
In Japanese Patent Application Laid-Open No. 58-106860, the gate potential is set as the gate potential one scan before.

Figure 4 shows the auxiliary capacitance C3 and paranormal appearance ff1c in one pixel.
FIG. 3 is an equivalent circuit diagram showing the relationship between ad and the like. In the same figure,
Vg represents a gate potential, Vs represents a source potential, Vd represents a drain potential, and Vc represents a common potential. Then, when the difference between the gate potential during on and off times is Δvg, the decrease ΔVd in the drain potential in one frame is expressed by the following equation.

Δyd=cc+cl・△Vg/ (Cgd+Clc+C
s) As is clear from this equation, by newly providing the auxiliary capacitor CSt, the amount of decrease in ΔVd can be reduced.

(Problem to be Solved by the Invention) However, in this method, Cgd differs from pixel to pixel due to mask shift during exposure or shot shift during step-and-repeat exposure even within the same screen. This is a hindrance to improving screen quality.

Furthermore, as a method for eliminating such mask displacement during exposure, there is an example of arranging source and drain electrodes perpendicular to the longitudinal direction of the gate, as described in Japanese Patent Laid-Open No. 62-165368. There is. In this conventional example, the gate-drain capacitance Cgd can be kept constant, but the need to reduce Cgd results in finer electrode wiring, which imposes severe restrictions on the process and has the disadvantage that disconnections are likely to occur.

As described above, in conventional active matrix display elements, there is a problem with a drop in drain potential within the screen, and variations in the amount of this drop, or variations from lot to lot. However, the method of eliminating exposure deviation by adjusting the thickness of the wafer also has the problem of an increase in defects due to microfabrication as described above.

The present invention was made in view of the above-mentioned conventional circumstances, and provides an active matrix display element with high screen quality that reasonably suppresses in-plane variation in drain potential drop and lot-to-lot variation. The purpose is to provide.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides: - an active element having a gate electrode, a gate insulating film, a channel region, a source electrode, and a drain electrode for each pixel on a main surface; A pixel electrode connected to the gate electrode is provided, and a predetermined auxiliary capacitance is separately provided, and a scanning line integrated with the gate electrode and a scanning line integrated with the source electrode are arranged in a matrix around the active element and the pixel electrode. an active element substrate on which signal lines are formed; a counter substrate having a common electrode on one main surface facing the active element substrate; and a display medium sandwiched between the active element substrate and the counter substrate. The present invention relates to an active matrix display element comprising:

In the active element substrate, the gate/drain capacitance and the auxiliary capacitance between the gate N pole and the drain electrode are formed in parallel to the signal line, and the gate/drain capacitance and the auxiliary capacitance are as follows. It increases or decreases at a roughly constant ratio with respect to the positional deviation during patterning of each electrode.

(Function) In the active matrix display element of the present invention, when Cgd and C5 change, the amount of change Δ'■d in drain potential is given by the following equation.

△−Vd = (80(Jd (Clc+Cs) −
ΔCs −Cgd) −ΔVg/ (C(Jd+C
1c+Cs) 2Here, △Cgd represents the amount of change in the capacitance between the gate and drain, and 80s represents the amount of change in the auxiliary capacitance.

Therefore, when the corresponding pixel is on and off, Cgd and CIC
If there is no change in ΔCgd:ΔCs=Cgd:(CI
When the relationship C+O3> is satisfied, the drain potential ■d is not affected even if there is a positional deviation during electrode formation with respect to the design. Actually, since Cgd and C1c change between on and off, Cgd* and CIC" at the effective voltage must be taken into consideration.

Therefore, the ratio of △Cqd and 8C5 is (maximum value of Cgd)
: Selected within the range of ((minimum value of CIC) IC3) to (minimum value of Cgd): ((maximum value of CIC) IC3).

In this invention, the dimensions and arrangement of the electrodes are designed so that the gate-drain capacitance cgd and the auxiliary capacitance ICs both increase or decrease at the above-mentioned ratio with respect to positional deviation during electrode formation. An active matrix display element with uniform characteristics can be obtained using conventional process technology without imposing restrictions on the manufacturing process such as microfabrication or measures against disconnection.

(Example) The details of the present invention will be described below with reference to the drawings, taking as an example the case where the active matrix type display element is a liquid crystal display element using TPT as a switching element.

FIG. 1 is a schematic diagram showing the arrangement of active elements, etc. in one embodiment of the present invention. In the figure, 1 for each pixel
The active element 10, for example TPT, has a gate electrode 12 integrated with the scanning line 11, a source electrode 14 integrated with the signal line 13, and a drain electrode 16 connected to the pixel electrode 15.
It is composed of etc. Here, the scanning line 11 is, for example, a wiring for applying a scanning signal to the gate of the active element 10, while the signal line 13 is, for example, a wiring for applying an image signal to the source of the active element 10. Overall, one pixel is composed of a plurality of active elements 10 and one pixel electrode 15 connected thereto, and scanning lines 11 and signal lines 13 are formed in a matrix around the active elements 10. has been done. In addition, an auxiliary electrode 17 is formed integrally with the scanning line 11 in the same way as the gate electrode 12 within the pixel.
When the gate electrode 12 is integrated with the (n+1)th scanning line 11 in the same pixel, the auxiliary electrode 17 is connected to the nth scanning line 1.
It is one with 1. Furthermore, an auxiliary capacitor electrode 18 having a rectangular shape similar to the drain electrode 16 is formed simultaneously with the source electrode 14 and the drain electrode 16, but a part of this auxiliary capacitor electrode 18 is covered with an insulating film (not shown). It faces the auxiliary electrode 17 via the auxiliary electrode 17. And auxiliary capacitance electrode 1
8 is electrically connected to the pixel electrode 15 together with the drain electrode 16 . Further, the auxiliary capacitance electrode 18 has the same center line 19 in a direction roughly parallel to the signal line 11 as the drain electrode 16 in the same pixel. The sizes of the drain electrode 16 and the auxiliary capacitance electrode 18 are determined by the width Wd of each.
The only difference is the two widths Wc, and the ratio of the width Wd to the width WC is C.
gd: ((maximum value of C1c) IC3).

FIG. 2 is a schematic sectional view showing one pixel portion in this embodiment, and corresponds to the AA section in FIG. 1 viewed from the direction of the arrow. Explaining FIG. 2 according to the manufacturing process, for example, on one main surface of the substrate 20 made of glass,
For example, the gate electrode 12 is formed by coating a Cr (chromium) film by sputtering and photo-etching it into a predetermined shape, and then covering it with a gate insulating film made of, for example, silicon oxide (S i Ox ). 21 is formed by the plasma CVD method.Here, although not shown, when the gate electrode 12 is formed, the scanning line 11 and the auxiliary electrode 17 are also formed in the same process. The film 21 is an insulating film interposed between the scanning line 11 (auxiliary electrode 17) and the signal line 13 (pixel electrode 15, auxiliary capacitance electrode 18) in FIG. In the part facing the electrode 12,
For example, i-type hydrogenated amorphous silicon (a-3:H
) is formed using the plasma CVD method, and furthermore, the channel region 22
Above, an n-type a-3i source region 23 and a drain region 24 electrically isolated from each other are provided using the same plasma CVD method. On the gate insulating film 21 adjacent to the 24 side, a pixel electrode 15 is provided by, for example, coating an ITO (indium tin oxide) film by sputtering and then photoetching it into a predetermined shape. Further, one end of the drain electrode 16 is connected to the drain region 24, and the other end of the drain electrode 16 extends and is connected to the pixel electrode 15. Furthermore, one end of the source electrode 14 is connected to the source region 23. Here, the source electrode 14 and the drain electrode 16 are formed using the same method, for example, formed by sequentially coating an MO (molybdenum) film and an AI (aluminum) film by sputtering, and then photoetching them into a predetermined shape. Although not shown, the signal line 13 and the auxiliary capacitor electrode 18 in FIG. 1 are also formed in the same process as the source electrode 14 and the drain electrode 16. Like the drain electrode 16, one end of the active electrode 18 extends over and is connected to the pixel electrode 15. In this way, the desired active element substrate 2
5 is obtained. On the other hand, a common electrode 27 made of, for example, ITO is formed on one main surface of the substrate 26 made of, for example, glass, thereby forming a counter substrate 28 . An alignment film 29 made of, for example, low-temperature cure type polyimide (PI) is further formed on the entire surface of one main surface on which the active elements 10 and the like of the active element substrate 25 are formed, and an alignment film 29 made of, for example, low temperature cure type polyimide (PI) is further formed on the entire surface. An alignment film 30 made of, for example, low-temperature cure type polyimide is also formed on the entire main surface on which the common electrode 27 is formed. Then, each of the alignment films 29 and 30 is rubbed in a predetermined direction with a cloth or the like on one main surface of the active element substrate 25 and the counter substrate 28, thereby applying an alignment treatment by rubbing.

Further, the active element substrate 25 and the counter substrate 28 are arranged such that their surfaces face each other and their alignment axes form approximately 90', and a display medium 31, for example, a nematic liquid crystal, is held in the gap between them. ing. Here, when combining the active element substrate 25 and the counter substrate 28, the alignment film 29
, 30 are set such that the direction of good viewing angle faces the front direction. Polarizing plates 32 and 33 are provided on the other main surfaces of the active element substrate 25 and the counter substrate 28, respectively.
is attached, and illumination is performed from the other main surface side of either the active element substrate 25 or the counter substrate 28.

In this embodiment, the gate-drain capacitance 1c! between the gate electrode 12 and the drain electrode 16! lld and auxiliary electrode 17
and the auxiliary capacitor C separately provided between the auxiliary capacitor electrode 18
s are formed in line in a direction approximately parallel to the signal line 13. In particular, since the drain electrode 16 and the auxiliary capacitance electrode 18 are designed so that the center line 19 is the same, the gate-drain capacitance ff1cqd and the auxiliary capacitance O
3 is an approximately constant ratio to the positional deviation during patterning of each electrode such as the scanning line 11 and signal line 13, that is, Cc+d.
: Increase or decrease at the ratio of ((maximum value of CIC) + C3). As a result, in this embodiment, although the gray scale fluctuation was evaluated using the CRT image signal, the drain electrode 16 or the auxiliary capacitance electrode 18 within the screen
overlaps with the gate electrode 12 or the auxiliary electrode 17 △
The variation in L (see FIG. 1) did not pose a problem in terms of screen quality.

Further, in order to test the propagation distortion of the gate drive pulse due to the gate wiring resistance and the capacitance of the scanning line 11, the write characteristics were also evaluated, and the characteristics were no inferior to the conventional characteristics. Furthermore, when we measured the drain current-gate voltage characteristics of the active element 10, we found that the off-state current was approximately 3X1O-1
2(A), the on-current is approximately 2X10'(A>, and the conventional T
It was similar to PT.

[Effects of the Invention] The present invention can reduce fluctuations in pixel potential due to capacitive coupling between signal lines and pixel electrodes within a screen and from lot to lot even if there is a positional shift when forming electrodes of active elements. Also,
without introducing new processes to the current manufacturing process.
A uniform active matrix display element with excellent reproducibility and high screen quality can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing the arrangement of active elements in an embodiment of the present invention, FIG. 2 is a schematic cross-sectional view of one pixel portion in an embodiment of the invention, and FIG. 3 is a conventional active matrix. FIG. 4 is an equivalent circuit diagram of one pixel of an example of a conventional active matrix display element provided with an auxiliary capacitor. 10... Active element 11... Scanning line 12... Gate electrode 13... Signal line 14... Source electrode 15... ... Pixel electrode 16 ... Drain electrode 17 ... Auxiliary electrode 21 ... Gate insulating film 22 ... Channel region 25 ... Active element Substrate 27...Common electrode 28...Counter substrate 31...Display medium C3...Auxiliary capacitance Cgd...Gate/drain capacitance agent Patent Attorney Noriyuki Ken Yudo Takehana Kikuo 19↑・(Sewing Fig. 1 c Fig. Fig. 2

Claims (1)

[Claims] For each pixel on one main surface, a gate electrode, a gate insulating film,
An active element having a channel region, a source electrode, and a drain electrode, and a pixel electrode connected to the drain electrode are respectively arranged, and a predetermined auxiliary capacitor is separately provided, and a predetermined auxiliary capacitor is provided around the active element and the pixel electrode. has an active element substrate on which a scanning line integral with the gate electrode and a signal line integral with the source electrode are formed in a matrix, and a common electrode disposed opposite to the active element substrate on one principal surface. In an active matrix display element comprising a counter substrate and a display medium sandwiched between the active element substrate and the counter substrate, a gate-drain capacitance between the gate electrode and the drain electrode and the auxiliary capacitor are provided. are formed in a direction substantially parallel to the signal line,
The ratio of the amount of change in the gate-drain capacitance to the amount of change in the auxiliary capacitance due to positional deviation during electrode formation is (maximum value of the gate-drain capacitance): (minimum value of the capacitance of the display medium + the auxiliary capacitance). 1. An active matrix display element characterized in that the active matrix display element is in a range from (minimum value of the gate-drain capacitance) to (maximum value of the capacitance of the display medium+the auxiliary capacitance).