JPH0279608A - Offset adjusting device for operational amplifier - Google Patents

Abstract

PURPOSE:To simplify adjustment and to attain high reliability by controlling an offset voltage in digital manner. CONSTITUTION:Transistors 14-18 comprise current mirror circuits with different magnification, and the collector current of a transistor 20 can be set at the current of 0-15/2 times the current value supplied from a power current source at every pitch of 1/2 times corresponding to levels set at the output terminals 3a-3d of a data latch circuit 3. In other words, the levels of the output terminals 3a-3d of the data latch circuit 3 are set corresponding to the deviated quantity of the offset voltage of an operational amplifier by a CPU 1, and the level of the output terminal 3e of the data latch circuit 3 is set corresponding to the deviated direction of the off-set voltage. Thereby, the optimum offset voltage can be obtained. In such a way, it is possible to perform offset control with high reliability with a miniaturized and inexpensive facility.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an offset adjustment device for adjusting the offset voltage of an operational amplifier.

[Prior art] Generally, an operational amplifier is used in a camera's photometric device.

Here, if the offset voltage of the operational amplifier is large and the brightness of the subject is low, the ratio of dark current to photocurrent of the photoelectric conversion element as a light receiving element becomes large, causing a photometry error. Therefore, in cameras that require highly accurate photometry, it is necessary to adjust the offset voltage of the operational amplifier in order to minimize the influence of the dark current of the photoelectric conversion element.

FIG. 7 shows a conventional example of a camera photometer using an operational amplifier.

A silicon photodiode (hereinafter referred to as S) as a light receiving element
A photoelectric conversion element 101 such as a PD (abbreviated as PD) is an operational amplifier 10.
4, and ideally has zero bias. The photoelectric conversion element 101 generates a photocurrent Ip according to the intensity of incident light, and charges the capacitor 102. A trigger switch 103 is connected in parallel to the capacitor 102 .

The output v out of the operational amplifier 104 is connected to the capacitor 102
The amount of charge increases depending on the amount of charge. operational amplifier 10
The output V out of No. 4 is connected to the inverting input terminal of the comparator 105 and is compared with the output V coa+p of the determination voltage generating circuit 106 connected to the non-inverting input terminal.

The operation shown in FIG. 7 will be explained with reference to the timing chart shown in FIG.

In the initial state, the trigger switch 103 is on. Therefore, the photocurrent 1p generated in the photoelectric conversion element 101 is transferred to the reference voltage source Vr via the trigger switch 103.
flows to ef'. Therefore, the capacitor 102 is not charged and the output V out of the operational amplifier is equal to the reference voltage V re
It is maintained at f'.

At the same time as exposure starts, trigger switch 103 is turned off. Therefore, the photocurrent 1p is charged in the capacitor 102, and the following voltage V is applied across the capacitor 102.
c is generated.

Here, C is the capacitance of the capacitor 102.

Assuming that the photocurrent 1p is constant, equation (1) can be transformed into a linear equation as follows.

Vc - (Ip /C)t - (2) Therefore, the output Vout of the operational amplifier 104 is equal to the reference voltage V
rises linearly from rcl'. Operational amplification output V ou
When t rises to a voltage equal to the determination voltage v comp, the output COM P out of the comparator 105 changes from the "H" level to the "L" level.

In response to this "L" level signal COMPout, an exposure end signal is generated. Therefore, the exposure time t is expressed as follows.

t-CΦVcomp/I+) −(3
) Here, if the judgment voltage V coip is set so that the optimal exposure time t is obtained for the photocurrent 1p, even if the brightness of the subject changes and the photocurrent IP changes, the optimal exposure will always be obtained. An exposure end signal can be obtained when the amount is reached.

However, - the SP used as a photodetector in the shell
When D is forward biased, it has the characteristic of flowing current like a normal diode. At a bias voltage of about 10-odd mV, almost no current flows in a normal diode, but in the case of an SPD, the area is very large, so
Several pA flows. Furthermore, even when biased in the reverse direction, there is a dark current characteristic, and a beam current flows.

FIG. 9 shows an example of the dark current-reverse voltage characteristics of the SPD using temperature Ta as a parameter. The horizontal axis shows the reverse voltage, and the vertical axis shows the dark current in logarithm. From this, when the reverse bias is 10 mV, the dark current is about 0.4 pA at 25°C, but 5
It can be seen that when the temperature reaches 5° C., a dark current of 109 A or more is generated.

Considering the dark current 1d, equation (3) is transformed as follows.

t-C-Vcoap/(Ip+Id) -C4) Here, if the photocurrent 1p is sufficiently larger than the dark current 1d,
The dark current 1d is hardly a problem, but when the photocurrent 1p is small, that is, when the brightness of the subject is low, the exposure time shifts to become shorter due to the dark current 1d.

When a bias voltage is applied to the SPD in this way, the photocurrent is 1
Since a current other than p flows through the SPD, exposure accuracy deteriorates.

To prevent this, the bias voltage to the SPD must be set to zero. In FIG. 7, the bias voltage applied to the photoelectric conversion element 101 means the operational amplifier 10.
4 offset voltage.

FIG. 10 shows an example of a conventional offset adjustment device for an operational amplifier.

An inverting input terminal (-) and a non-inverting input terminal (+) are connected to gate terminals of MOS transistors 210 and 202, respectively. MOS transistors 210 and 202 constitute a differential input transistor pair. Transistors 203, 204, 205, 206, 20 connected to power supply terminal Vce
7 constitutes a current mirror circuit, which supplies current from the current source circuit 208 to the entire device.

A differential transistor pair 209, 210 connected to the transistor 203 of the current mirror circuit, and a resistor 220 connected to the base terminal of the transistor 209, 210.
221, 222, 223, and 224 constitute an offset adjustment circuit. Reference voltage V re with resistor 223 and 224
The ratio of the emitter currents of the differential transistor pair 209 and 210 is determined by the ratio between the constant voltage obtained by dividing f and the variable voltage obtained by the semi-fixed resistor 220.

Therefore, by adjusting the semi-fixed resistor 220, the ratio of emitter currents of the differential transistor pair 209 and 210 can be adjusted.

The differential transistor pair 211° 212 and the resistors 225, 226, 227° 228 connected to the emitter terminals of the differential transistor pair 209, 210 constitute a load circuit (active load) for the differential input transistor pair 201° 202.
It constitutes a current mirror circuit that works as a. By changing the ratio of the emitter currents of the differential transistor pair 209, 210 of the offset adjustment circuit, the current ratio flowing through the differential transistor pair 211, 212 of the load circuit, and therefore the current ratio flowing through the differential input transistor pair 201, 202, can be changed. ,
In other words, the offset voltage can be adjusted.

Transistors 213, 214, 215, 216° 217
．． 218, 219, and resistors 229, 230, and 231 constitute an output stage of the operational amplifier. Capacitor 232 is for phase compensation.

In this adjustment device, the circuit portions (indicated by dashed lines) other than the semi-fixed resistor 220 for offset voltage adjustment are integrated.

[Problems to be solved by the invention] In the offset adjustment device shown in FIG.
Since the adjustment is carried out using 20, there is a drawback that it is difficult to automate the adjustment. Further, after adjustment, the slider of the semi-fixed resistor may move due to vibration or the like, and the offset voltage may deviate from the adjusted value. It is difficult to determine the offset voltage n1 after the camera is completed, and the only way to determine whether it is adjusted correctly is by measuring the photometry accuracy at low brightness. Therefore, it is not possible to adjust the offset voltage after the camera is completed. It's impossible.

Furthermore, since it is necessary to connect the adjustment resistor to the outside of the integrated circuit, the difference in temperature characteristics between the resistance inside the integrated circuit and the temperature characteristic of the adjustment resistor causes the offset voltage to have temperature characteristics. The device shown in Fig. 10 takes temperature characteristics into full consideration, but in order to completely eliminate temperature characteristics, the resistance values of resistors 220, 223, and 224 must be set so that the base currents of transistors 209 and 210 can be ignored. It has to be made smaller, which is not possible.

It is also possible to use a laser trimming resistor instead of the semi-fixed resistor 220, but this would solve the problem of deviation after adjustment, but the equipment for making the adjustment would be expensive and large. There is the inconvenience of putting it away.

The present invention has been made to address the above-mentioned circumstances, and its purpose is to provide an offset adjustment device for an operational amplifier that enables highly reliable offset adjustment with small and inexpensive equipment.

[Means for Solving the Problems] The offset adjustment device for an operational amplifier according to the present invention includes a differential transistor pair connected to a pair of differential input terminals of an operational amplifier, and a current ratio of each transistor in the differential transistor pair. A load circuit that determines the current ratio, a D/A conversion circuit that supplies an analog current corresponding to the digital input to the load circuit and determines the current ratio, and a data latch that stores the digital input value to the D/A conversion circuit. do.

[Operation 1] According to the present invention, a variable current is supplied from the current source circuit to the load circuit by the output of the D/A conversion circuit, and the offset voltage is adjusted by controlling the current ratio flowing through the differential input transistor pair. can. Therefore, by sequentially changing the output of the D/A conversion circuit to find a digital value that provides the optimal offset voltage, and storing that value in memory, from now on, when using the operational amplifier, the memory By setting data corresponding to the digital value stored in the data latch in the data latch, the offset voltage can always be controlled to an optimal value. In addition, since the entire adjustment mechanism can be configured within a single integrated circuit,
It is possible to easily cancel the temperature characteristics.

(Example) Hereinafter, an example of an offset adjustment device for an operational amplifier according to the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of the first embodiment.

The CPUI reads data stored in E2 FROM2, which is an electrically rewritable nonvolatile memory,
Through digital communication, the output terminals 3 a , 3 b + 3 c , 3 d *3 e of the data latch circuit 3
Set the level according to the data.

Output terminals 3a, 3b, 3c, 3d are MO for switching
Connected to the gate terminals of S transistors 6.7 and 8.9, respectively. Output terminal 3e is analog switch 21.2
It is connected to the second control terminal.

Transistors 14, 15, 16, 17, 18 constitute current mirror circuits with different magnifications. With respect to the current value supplied from the current source circuit 5, the transistor 15
2x, transistor 16 is 1x, transistor 17 is 2x
The transistors 18 allow four times as much current to flow through their respective collector terminals.

For example, when the MOS transistor 6 is on, that is, when the output terminal 3a of the data latch circuit 3 is at "L" level, the collector current of the transistor 15 is supplied from the drain terminal of the MO3I-transistor. Not flowing.

Conversely, when the transistor (MOS) transistor is off, that is, the output terminal 3a of the data latch circuit 3 is at "H° level," the collector current of the transistor 15 flows through the diode 10. output terminals 3b and 3c of the data latch circuit 3.
, 3d controls the flow path.

The currents flowing through the diodes 10, 11, 12, and 13 are added together and applied to the collector terminal of the transistor 19 of the current mirror circuit composed of the transistors 19, 20, and output from the collector terminal of the transistor 20. Therefore, the collector current of the transistor 20 is 0 to 15/2 times the current value supplied from the current source circuit 5, depending on the levels set at the output terminals 3a, 3b, 3c, and 3d of the data latch circuit 3. The current can be set in 1/2 increments.

Next, the configuration of the operational amplifier will be explained.

Transistor 25 forms a current mirror with transistor 24, and supplies current to the source terminals of MOS transistors 26 and 27 forming a differential input pair. The current supplied from the transistor 25 flows through the MOS transistors 26 and 27, and the ratio of flow through each is as follows.
It is determined by the current of a current mirror circuit as a load circuit constituted by transistors 28 and 29 and resistors 30 and 31.

The transistors 32, 34, 35, 36, 37 and the resistor 33 form the output stage of the operational amplifier, and the emitter terminal of the transistor 36 serving as the output terminal is a MOS) transistor 2.
It is connected (feedback) to the gate terminal of 6. The gate terminal of the MOS transistor 27 is the non-inverting input terminal (+), MO
S) The gate terminal of the transistor 26 is the inverted input terminal (-
).

In the camera's all-optical circuit, a photoelectric conversion element for light reception is connected between the non-inverting input terminal and the inverting input terminal, and a logarithmic compression diode is connected in the return path to obtain a compressed photocurrent output. Alternatively, connect a capacitor to the non-inverting input terminal to obtain the integrated output of the photocurrent.

Next, a configuration for adjusting the offset voltage and its principle will be explained.

Which of the analog switches 21 and 22 the collector current of the transistor 20 flows through is determined by the level of the output terminal 3e of the data latch circuit 3.

Here, it is assumed that the analog switch 21 is turned on and the collector current of the transistor 20 flows to the resistor 31 via the analog switch 21. In this case, an extra voltage equal to the product of the collector current of the transistor 20 and the resistance value of the resistor 31 is generated across the resistor 31 compared to the voltage across the resistor 30 . This extra voltage causes the base-emitter voltage VBE of the transistor 29 to decrease.
The collector current of transistor 29 decreases. The reduced current flows to the collector terminal of the transistor 28 and settles at a stable point of the current mirror circuit formed by the transistors 28, 29 and the resistors 30 and 31.

As a result, the source-drain current of the MOS transistor 27 decreases, and the source-gate voltage decreases, so that the base potential of the MOS transistor 27 increases. Since it is a differential pair, the current between the source and drain of the MOS transistor 26 increases and the base potential decreases. Therefore, the offset voltage of the operational amplifier changes in a direction in which the voltage (-) at the inverting input terminal decreases relative to the voltage at the non-inverting input terminal (+). The larger the collector current of transistor 20, the smaller the VBB of transistor 29, resulting in a larger offset voltage change.

That is, the output terminal 3a of the data latch circuit 3 corresponds to the amount of deviation of the offset voltage of the operational amplifier.

By setting the levels of 3b, 3c, and 3d, and setting the level of the output terminal 3e of the data latch circuit 3 according to the offset direction of the offset voltage, it is possible to obtain an optimal offset voltage. The direction and amount of deviation of the offset voltage of the operational amplifier are measured in advance1, and these are measured as E2.
Store it in FROM2. Specifically, the offset voltage M1 may be fixed while sequentially changing the data set in the data latch circuit 3, data that provides the optimum offset voltage may be determined, and this data may be stored in the E2 FROM 2.

The causes of offset voltage occurring in an operational amplifier with such a configuration include (a) the differential input MOS transistor pair 26. 27(7) Difference in VGS-I DS characteristics.

(b) Difference in voltage between the base and emitter of transistors 28 and 29, (C) Difference (variation) in resistance value of resistors 30 and 31, (d)) Insufficient correction of base current supply of transistors 28 and 29 There are many factors that can be cited. Although the offset voltage due to these factors has temperature characteristics, this embodiment can also compensate for the temperature characteristics. As mentioned above (
Among the causes of offset voltage generation in a) to (d), (d
) can be easily resolved based on the circuit configuration.
Here, for the causes (a) to (C), the causes of offset occurrence and temperature characteristics will be explained.

(a) MOS) The relationship between IDS and VGS of a transistor is expressed as follows.

IDS-(Is COX/2) (Z/L)
(VGS-VTR) 2・(5) Here, μS is the carrier mobility, Cox is the capacitance per unit area of the gate, Z is the gate width, L is the gate length,
VTH is the threshold voltage. In equation (5), Z and L cause offset voltage.

Although it is VTll, there is almost no problem with Z. The offset voltage caused by variations in gate length and threshold voltage VTII, that is, the difference in VGS, is I
It can be adjusted by changing the DS (5)
From the ceremony.

Considering the temperature characteristics, μS and Cox have temperature coefficients on the right side of equation (5), and VGS and VT
H is also proportional to absolute temperature. Therefore, in order to eliminate the temperature characteristics of the offset voltage, it is sufficient to keep the IDS ratio constant regardless of the temperature.

(b) The emitter-base voltage VBE of the transistor is expressed as follows.

VBE=VTN n (Ie/Is) −(6
) Here, VT is a coefficient proportional to absolute temperature, Ic is the collector current, and Is is the reverse saturation current of the transistor. As shown in FIG. 2, in the current mirror circuit, when a current Icl is supplied to the transistor 301, the collector current 1c2 of the transistor 302 is expressed as follows.

VBE-VT! I n (I cl/I 5l)
−VT p n (I c2/ I s2) −(
7) Ic2- Icl (Is2/Isl)
-(8) If the transistor pairing is good, I
sl -1s2, but it is generally said that it varies by about 10% at most. It is said that the temperature characteristic of Is approximately doubles per 10°C, but in equation (8), Is
The temperature characteristics of s2/Isl cancel each other out and become a constant.

(c) The temperature characteristics of a resistor vary depending on the integrated circuit process, but typically have a temperature characteristic of several thousand ppm/'C at room temperature. Variations in resistance values are generally considered to be divided into absolute errors and relative errors. The absolute error is an error with respect to the designed resistance value, and has a variation of about ±30%. Relative error is 2 designed to have the same resistance value.
This is the ratio of the resistance values of two resistors, and is approximately 1% to 3%, regardless of the magnitude of the absolute error. It is the relative error that causes the offset voltage.

The temperature characteristics of the apparatus shown in FIG. 1 will be considered in consideration of the above three factors. FIG. 3 is a diagram illustrating the temperature characteristics of the offset voltage shown in FIG. 1.

The resistance values of resistors 312 and 313 are each R1°R2, and the reverse saturation currents of transistors 308 and 309 are each 1 s.
1. If Is2, then the Be-X II emitter voltage VBEI of the transistors 308 and 309.

V BE2 is expressed as follows.

VBEI-VTIIn (Icl/Isl)
-(9)VBE2-VT Rn (Ic2/ l5
2) ...(10) From equations (9) and (10), the transistor 308, which is generated by adjusting the offset voltage,
The potential difference ΔVBE between the base and emitter voltage of 309 is expressed as follows.

ΔVBIE-VBEI-VBE2-VT (Rn (I cl/ I c2) + jl
n (Is2/l5l) -(11)Isl
/ I s2 is a constant whose temperature characteristics are canceled, so I n (I s2 / I 5l) − β ・ (1
2), equation (11) is transformed as follows.

I cl/ I c2 -exp (ΔV BE/V T-β) -(
13) In order for the offset voltage to have no temperature characteristics, it is sufficient to cancel the temperature characteristics of I cl/I c2, so ΔVI3E only needs to be proportional to VT.

On the other hand, resistance 312.313+: generated voltage VRI.

VH2 is expressed as follows.

VRI-R1・Icl...(14)
VH2-R2(IcZ+12) -(15
) Therefore, equation (11) is transformed as follows.

ΔV BE-V R2-V R1 Trout R2 (Ic2+ 12) -RI llIc1...
・(16) Since it is sufficient that this ΔVBE is proportional to VT, I cl, I c2. I 2 are each V
It is sufficient if it is proportional to T/R. R is the temperature characteristic of resistance.

Therefore, if a current source circuit proportional to VT /H is used as the current source circuits 304 and 305 of If, 12, Ic
l, Ic2 can be made very proportional to VT/R. The current source circuits 304 and 305 in 11.12 are the first
Current source circuit 5 and current mirror circuit 19.2 in the figure
Each corresponds to 0.

An example of a current source circuit proportional to VT/H is shown in FIG. Since the transistors 314 and 315 constitute a current mirror, the equation (17) is satisfied. In the transistors 318 and 319 and the resistor 320, VTD n (If /l5l) -VT l n (12/101s2) +R1112
...(18) holds true. Assuming that I sl -1s'2, (18
) by substituting the equation (17) into the equation, the following relationship is obtained.

If −(VT /R) linlO− (19) In this way, a current source circuit proportional to VT /H can be easily realized within an integrated circuit.

In this way, in the first embodiment, by adjusting the current ratio of the load circuit of the differential input pair using the output of the D/A conversion circuit,
It is possible to realize an offset adjustment device that is easy to adjust, highly reliable, and has excellent temperature characteristics without requiring an analog adjustment resistor.

A second embodiment will be described with reference to FIGS. 5 and 6. Fifth
The figure shows a photometry circuit that charges a photocurrent to a capacitor 403 and obtains an integral output, similar to FIG.

The non-inverting input terminal (+) of the operational amplifier 401 is connected to the reference voltage V.
raf, and a photoelectric conversion element 402 is connected between the non-inverting input terminal (+) and the inverting input terminal (-).

The integrating capacitor 403 is connected in the feedback path of the operational amplifier, and the operational amplifier output v out changes depending on the charge charged in the capacitor 403.

In the case of such a photometric circuit, the voltage at the non-inverting input terminal of the operational amplifier 401 is fixed to the reference voltage V ref', so the circuit configuration of the operational amplifier as shown in FIG. 6 is also possible. be. That is, the configuration is such that the current between the source and drain is not controlled by a current mirror circuit, but only by the resistors 407 and 408.

The present invention can also be applied to such a circuit. If the potentials of the non-inverting input terminal (+) and the inverting input terminal (-) are V (+) and V (-), respectively, the current source 4
09 current 1f-0, always V(-) > V (
+), the resistance value of the resistor 408 is made smaller than the resistance value of the resistor 407 in advance. In actual use, by flowing a current If to the current source 409, the potential of the inverting input terminal decreases, V(-) - V(+
).

If a digital current adjustment mechanism as shown in FIG. 1 is added to this current source 409, the same effects as in the first embodiment can be obtained. In order to compensate for the temperature characteristics, the current source 409 needs to generate a current 11 proportional to 1/R.

This invention is not limited to the embodiments described above and can be modified in various ways. For example, although MOS transistors are used as the differential input pair, bipolar transistors may also be used.

In FIG. 1, MOS) transistors 26 and 27 are connected to PN
P) If a transistor is replaced, it becomes an operational amplifier with a differential input pair made up of bipolar transistors. −
Generally, operational amplifiers with bipolar transistor inputs are MO
S) Compared to transistors, the offset voltage is small, so the offset voltage is not a problem in many cases, but when an offset of several m-■ becomes a problem for operational amplifier applications, or if the offset voltage is forced This invention can be effectively applied to cases where it is desired to generate.

[Effects of the Invention] As explained above, according to the offset adjustment device for an operational amplifier according to the present invention, by digitally adjusting the offset voltage of an operational amplifier, adjustment can be simplified, and the offset voltage can be adjusted at a high cost. Because it achieves reliability, it is suitable for applications that require high precision, such as camera photometry circuits. Furthermore, according to the present invention, the temperature characteristics of offset voltage can also be compensated for.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment of an offset adjustment device for an operational amplifier according to the present invention, FIG. 2 is a circuit diagram for explaining the characteristics of a current mirror circuit, and FIG. 3 is a temperature characteristic of the first embodiment. 4 is a circuit diagram of an example of a current source circuit for canceling temperature characteristics, and FIG. 5 is a circuit diagram of an example of a current source circuit for canceling temperature characteristics.
A circuit diagram of the operational amplifier of the embodiment, FIG. 6 is a circuit diagram of the offset adjustment device of the second embodiment, FIG. 7 is a circuit diagram of a conventional operational amplifier, and FIG. 8 is a timing diagram showing the operation of FIG. 7. FIG. 9 is a chart showing the reverse voltage-dark current characteristics of a PSD, and FIG. 10 is a circuit diagram of a conventional example of an offset adjustment device for an operational amplifier. 3...Data latch circuit, 5...Current source circuit, 6゜7.8.9...Switching MO8) transistor,
19.20...Current mirror episode! L21゜22...
・Analog switch, 26.27...Differential input MOS
Transistor pair, 28.29...active load,
38... Phase adjustment capacitor. Applicant's representative Patent attorney Jun Tsuboi Figure 2 Figure 3 Figure 4 Figure 7 Procedural amendment 63. l 1.22 Yoshi, Director General of the Japan Patent Office (Monday/Monday, Showa 1939) 1) Tsuyoshi Moon 1, Indication of the case Japanese Patent Application No. 63-231751 2, Name of the invention Offset adjustment device for operational amplifier 3, Person making the amendment Relationship with the case Patent applicant (037) Olympus Optical Industry Co., Ltd. 4, Agent 3-7-2 Kasumigaseki, Chiyoda-ku, Tokyo UBE Building 1
00 Telephone 03 (502) 3181 (main representative)
-----" (6881) Patent attorney Jun Tsuboi
゛(,1 5, spontaneous correction Y LJ-
7. Contents of the amendment (1) r210J written in the 12th line of page 6 of the specification and the 14th line of the section on the same page is corrected to r201J. (2) "Base" written in page 15, line 8 to line 9 of the same page of the specification is corrected to "gate." (3) "Base" written on page 15, line 11 of the specification is corrected to "gate." (9) Figures 3, 6, and 10 of the drawings will be corrected as shown in the attached sheet. Figure 3

Claims (1)

[Claims] In an offset adjustment device for an operational amplifier having a pair of differential input terminals and an output terminal that generates an output according to an input to the differential input terminals, a differential transistor pair connected to the pair of differential input terminals. a load that determines the current ratio of each transistor of the differential transistor pair; a D/A converter that supplies analog current corresponding to the digital input to the load and determines the current ratio; and the D/A converter. comprising a memory for storing digital input values to the means;
An offset adjustment device for an operational amplifier, characterized in that the offset voltage is adjusted by controlling the current ratio using the output current of the D/A conversion means.