JPH0282576A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To avoid the decline of a carrier mobility while a short channel effect is suppressed and avoid the decline of a gain factor and realize high speed operation by a method wherein an impurity concentration in a semiconductor substrate is made to be high and an effective ionized impurity concentration in the surface is made to be low. CONSTITUTION:P-type impurity is introduced into a p-type Si substrate 1 having a p<->-type substrate concentration (Nsub) 11 of 1X10<15>cm<-3> so as to provide a p-type introduced impurity concentration distribution (NA(x)) 16. With this process, a short channel effect induced in the p-type Si substrate 1 can be suppressed. However, the decline of a carrier mobility is induced in a channel region 5 by Coulomb scattering and a high electric field caused by high concentration ionized impurity. In order to avoid it, n-type impurity is introduced so as to provide an n-type introduced impurity concentration distribution (ND(x)) 26 having a surface concentration of 8.5X10<15>cm<-3> and an effective ionized impurity concentration (NEFF(o)) is suppressed by compensation to obtain a relation of NA(o)+Nsub-ND(o)=-2X10<15>cm<-3> and the effective impurity concentration distribution 36 is formed of NEFF(x) to avoid the decline of the carrier mobility.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention aims to suppress short channel effects and obtain high mobility in semiconductor integrated circuits using MOSFETs, especially as MOSFETs become smaller. The present invention relates to a semiconductor device and a method for manufacturing the same.

Recently, in semiconductor integrated circuits using MOSFETs, in order to meet the demand for higher density, the component MOS
FETs have been miniaturized.

In particular, when trying to reduce the size of the gate electrode (gate length), the PN junctions that form the adjacent S/D regions across the gate are connected to each other in the depletion layer, resulting in a short channel effect (lower threshold voltage). problems such as a decrease in the punch-through voltage and a decrease in the punch-through withstand voltage). Conventionally, methods have been used to prevent this from obsolete according to the scaling law, but it has become difficult to lower the operating voltage. Therefore, the concentration of the semiconductor substrate is increased to spread out the depletion layer of the PN junction, thereby suppressing the short channel effect.

(b) Prior Art FIGS. 3(a) and 3(b) are a sectional view and an explanatory view of a conventional semiconductor device in which the short channel effect is suppressed.

In the same figure (a), (101) is a p-type Si substrate, (1
02) is the S/'D region of the LDD structure, (103) is the insulating SiO* film, (104) is the gate electrode, (105) is the channel region where a channel can be formed by gate voltage, (106) is the p-type introduction This is an impurity region.

Figure (b) shows the impurity concentration distribution seen in the depth direction directly below the gate in figure (a). In this conventional example, Figure (a)
The spread of the depletion layer from the PN junction forming the S/D region (102) in Figure (a) is as follows:
106) (p-type impurity concentration distribution (NA(x
) ) (116), and the p-type Si substrate concentration (N
Since the short channel effect is effectively suppressed by the effective impurity concentration distribution (Ngtt(X)) by synthesis with sub), the short channel effect is effectively suppressed.

According to the above-mentioned relationship, if the gate length is further shortened, the p-type introduced impurity region (106) must also be made more highly concentrated.

(c) Problems to be Solved by the Invention However, according to the above-mentioned conventional example, as miniaturization progresses, the concentration of the p-type introduced impurity region (106) must be further increased. However, the effective p-type impurity existing near the surface of the semiconductor substrate is ionized in the channel region (105) when the channel region (105) is formed by the gate voltage, and becomes an effective ionized impurity that causes Coulomb scattering of carriers. cause, and also the channel area (1
05) Since the electric field inside becomes higher, it affects the Kihe-Ria mobility. Carrier mobility decreases as the effective amount of ionized impurities increases.

Therefore, as miniaturization progresses, the gain factor decreases, and furthermore, high speed cannot be achieved.

(d) Means for solving the problem The above problem is a compensation impurity region formed by compensating an impurity of one conductivity type and an impurity of the opposite conductivity type in a semiconductor substrate of one conductivity type directly under a gate electrode as a semiconductor device. a surface with the highest impurity concentration of one conductivity type is disposed at least from the vicinity of the surface of the semiconductor substrate of one conductivity type immediately below the gate electrode to a depth equivalent to the depth where the S/p region is formed; A low concentration impurity region of one conductivity type or the opposite conductivity type is arranged on the surface, and the method for manufacturing a semiconductor device includes a step of forming a first 5ift film on the surface of a semiconductor substrate of one conductivity type, and a step of forming a first 5ift film on the surface of a semiconductor substrate of one conductivity type. a step of forming an impurity region of one conductivity type into the semiconductor substrate by four people; and a step of introducing an opposite conductivity type impurity into the semiconductor substrate into which the one conductivity type impurity has been introduced, and forming an impurity region with the one conductivity type impurity. Synthesizing with the impurity of the opposite conductivity type, one conductivity type is formed at least from the vicinity of the surface of the one conductivity type semiconductor substrate directly under the gate electrode to a depth equivalent to the depth where the S/D region is formed. forming a compensating impurity region in which a surface with the highest impurity concentration is disposed, and a low concentration impurity region of one conductivity type or the opposite conductivity type is disposed on the surface; and removing the first Sin film. a step of newly depositing a second SiO film on the semiconductor substrate;
This is achieved by depositing a polysilicon film on the surfaces of the two films, introducing impurities of opposite conductivity type, and patterning the polysilicon film to form a gate electrode.

(*) In other words, in order to suppress the short channel effect, the present invention introduces impurities of the same conductivity type as the semiconductor substrate at high concentration into the semiconductor substrate directly under the gate as in the past, and suppresses the short channel effect due to the gate electric field. Canoa Coulomb scattering in the channel region can be reduced by compensating for the impurity concentration of one conductivity type only in the surface region of the semiconductor substrate, which has little effect on the semiconductor substrate, with an impurity of the opposite conductivity type (funbensate) and reducing the effective amount of ionized impurities. Since the electric field in the channel region can be reduced, its mobility can be increased.

Therefore, even if semiconductor integrated circuits are miniaturized, a decrease in the gain factor can be prevented, and furthermore, the speed can be improved.

(f) Example The present invention will be specifically explained below with reference to illustrated embodiments.

FIGS. 1(a) and 1(b) are explanatory diagrams of an embodiment of the semiconductor device of the present invention.

Figure (a) is a sectional view of the main part of the semiconductor device, and Figure (b) is the impurity concentration distribution (
The vertical axis is the logarithm of the impurity concentration (eTll-'), and the horizontal axis is the figure (
The depth measured from the surface of the semiconductor substrate shown in a) (X (μm
))).

In the same figure (a), (1) is a p-type Si substrate with a specific resistance of 10 to 14 Ωm, (2) is an n-type S/D region with an LDD structure, (4) is a gate electrode made of n-type polysilicon, (3
) is the insulating Sin film for insulating the gate electrode, (7) is the gate Sin film, (5) is the channel region formed by the gate voltage, and (6) is for suppressing the short channel effect and improving Kirlia mobility. This compensation impurity region (6) is formed with an impurity concentration distribution as shown in Figure (b) in detail. In other words, in this example, the p''' type substrate concentration (
A p-type Si substrate (1) having a p-type introduced impurity concentration distribution (NA(x) ) (16) (surface concentration 6 x 10 ''cm-'', depth 0.7
~0.8 μm) Introduce p-type impurity. Thus p-type S
The short channel effect that occurs inside the i-substrate (1) can be suppressed, but the surface concentration is high (N5ub+ NA(0)).
In the channel region (5), carrier mobility decreases due to Coulomb scattering and high electric field due to this high concentration of ionized impurities, so to prevent this, the surface concentration is set to 8.
．． 5 x 10"cm-" n-type introduced impurity concentration distribution (
N-type impurity is introduced so that Nゎ(x) ) (26) is introduced and the channel region (
5) by lowering the effective ionized impurity concentration (tbrr(0)) at the surface where NA(o)+N5ub is formed.
-N, +(o) = -2X 1016cm-' (The negative sign indicates that there are many n-type impurities and it becomes n-type.)
and N in figure (b). , (X) to prevent carrier mobility from decreasing by forming the effective impurity concentration distribution (36). Since this effect becomes remarkable when the surface concentration is 5XIQ cm- or less, it is desirable to set it in this way. Also, at this time, N□ inside the semiconductor substrate.

(X) must be kept at a high concentration to suppress the short channel effect, so N. (X) needs to be introduced shallowly. At this time, N. , the largest plane of (X) is 0.3 from the surface
μm and has a concentration of ~5 x 10 "am-'. It is desirable that the depth of this maximum plane is between the surface and the equivalent depth to the depth at which the S/D region is formed. The surface concentration must be determined based on the semiconductor substrate degree, gate length, required breakdown voltage, threshold voltage, etc.

In this way, it is possible to realize a semiconductor device that can prevent a decrease in gain factor, increase speed, and also be miniaturized.

Here, let ND(0) be, for example, 4X10"am-', and L
ry(o)(=NA(o)+N5ub-No(o>)
Even if the p-type surface layer has a low concentration of −2×10 “cm”, the effect of the invention remains the same.

FIGS. 2(a) to 2(e) are explanatory diagrams of an embodiment of the method for manufacturing a semiconductor device of the present invention.

(a-1) of the same figure (a) is a cross-sectional view of the semiconductor device;
2) represents the impurity concentration distribution expressed logarithmically in the depth direction from the main surface of the semiconductor substrate (indicated by zero in Figure (a-1)).

First, a first Si block film (13) is formed to a thickness of 500 on a p-type Si substrate (1) having a specific resistance of 10 to 14 Ωm. Next, boron is implanted by ion implantation through the first 5i0z film (13) for the block at an energy of 120K.
eV, dose amount 1.6X 10"cm-" and surface concentration (iXIQ16cm-', depth 0.7~0.
8 μm 1 maximum concentration surface depth 0.3 μm, f & large concentration 5
X10"e+t+ -" p-type introduced impurity region (56)
form. The concentration distribution is NA(X) shown by (16) in Figure (a-2).

Next, (b-1) of the same figure (b) is a cross-sectional view of the semiconductor device, (
b-2) represents the impurity concentration distribution expressed logarithmically in the depth direction from the main surface of the semiconductor substrate (indicated by zero in Figure (b-1)). As shown here, low-concentration phosphorus is implanted to a depth of ~0.1 μm and a surface concentration of ~4×1
0"'can-" n-type introduced impurity concentration distribution (No(x
) ) The driving energy is 40Ke to have (26).
V, is introduced at a dose of 2×10 I'cITI-ffi, and the p-type introduced impurity region (56) which has already been introduced is synthesized and compensated to form the compensation impurity region (6) ((b-2) of FIG. 3
6) has an effective impurity concentration distribution of Ntyp(X). The surface is p-type, NaFp(0) 2 X I Q
"cm-") is formed.

Next, as shown in the same figure (c), the first 5iOi film (13
) is removed to form a new gate Sin, film (see figure (
e) (7)) Form the second Sin film (17).

Thereafter, a polysilicon film (14) which will become a gate electrode is deposited, and phosphorus is introduced into the entire surface by diffusion of POCR.

Next, as shown in the same figure (d), a polysilicon film (14) is formed.
A gate electrode (4) is formed by patterning.

Next, using the gate electrode as a mask, the low concentration S/D region (2
2> is formed. For this formation method, a method may be used in which phosphorus of 60 KeV and a dose of 3×10 cm −” and poron of 80 KeV and a dose of 3×10 cm − are introduced in a stacked manner to compensate for the synthesis.

Next, as shown in the same figure (e), an insulating Sin film (3) is formed on the upper and side surfaces of the gate electrode, and then, using this as a mask, As is ion-implanted (implantation energy: 6).
0KeV, dose 5 x 10 "cm-")
A high concentration S/D region (32) is formed.

The semiconductor device manufactured as described above has a concentration distribution similar to that of the semiconductor device shown in FIG. 1 except that it is a p-type surface layer, and exhibits the same effects as described above.

(g) Effects of the Invention As described above, according to the present invention, the impurity concentration inside the semiconductor substrate can be made high and the effective ionized impurity concentration on the surface can be made low. It is also possible to prevent a decrease in Therefore, it is possible to prevent a decrease in gain factor, increase speed, and also achieve miniaturization.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are explanatory diagrams of an embodiment of a semiconductor device of the present invention, and FIGS. Figure 3 (a), (
b) is a cross-sectional view of a conventional semiconductor device in which the short channel effect is suppressed, and an explanatory view thereof. (Explanation of symbols) (1), (101)... p-type Si substrate, (2),
(102)...S/D area of LDD structure, (22)
, (32)...Low concentration, high concentration S/D region, (3
), (103)...Insulating Sin, film, (4). (104)...Gate electrode, (5), (105)
... Channel A channel region, (6) ... Compensation impurity region, (56), (106) ... Introduced impurity region,
(13), (17)...first and second Si0g films, (14)...n+ type polysilicon film, (11),
(111) (111)'''p-type Si substrate concentration (Nsu
b), (16), (H6)・P-type introduced impurity concentration distribution (NA(X)), (26)...n-type introduced impurity concentration distribution (ND(X)), (36), (136)
...Effective impurity concentration distribution (Ntyp(X)=NA(
X)+N5ub ND(X)), N... Impurity concentration (cTll-''), x''' Distance wA (μm) from the surface of the semiconductor substrate in the depth direction.

Claims (4)

[Claims] (1) A compensation impurity region formed by compensating an impurity of one conductivity type and an impurity of the opposite conductivity type is provided in a semiconductor substrate of one conductivity type immediately below the gate electrode, and at least a semiconductor substrate of one conductivity type immediately below the gate electrode. S/D from near the surface
A surface with the highest impurity concentration of one conductivity type is arranged between a depth equivalent to the depth where the region is formed, and a low concentration impurity region of one conductivity type or the opposite conductivity type is arranged on the surface. Characteristic semiconductor devices. (2) The largest surface according to claim 1 is 0.2 to
A semiconductor device with a depth of 0.5 μm. (3) The surface concentration of the low concentration impurity region of one conductivity type or the opposite conductivity type according to claim 1 is set to a maximum of 5×10^1^6 cm^-
Semiconductor device with ^3. (4) a step of forming a first SiO_2 film on the surface of a semiconductor substrate of one conductivity type; a step of introducing an impurity of one conductivity type into the semiconductor substrate to form an introduced impurity region of one conductivity type; An opposite conductivity type impurity is introduced into a semiconductor substrate into which an opposite conductivity type impurity is introduced, and the one conductivity type impurity and the opposite conductivity type impurity are combined and compensated to at least one conductivity type semiconductor substrate immediately below the gate electrode. S from near the surface
A surface with the highest impurity concentration of one conductivity type is arranged between a depth equivalent to the depth where the /D region is formed, and a low concentration impurity region of one conductivity type or the opposite conductivity type is arranged on the surface. forming a compensation impurity region; removing the first SiO_2 film and newly depositing a second SiO_2 film on the semiconductor substrate; depositing a polysilicon film on the surface of the second SiO_2 film. death,
A method for manufacturing a semiconductor device, comprising the steps of introducing impurities of opposite conductivity type and patterning the polysilicon film to form a gate electrode.