JPH0291888A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent deterioration of a specific selecting line and to easily increase the density of a semiconductor memory by providing a switching means which incorporates an address signal generation circuit and cooperates with a control circuit for switching an externally inputted address signal and internally generated address signal to each other. CONSTITUTION:An address signal generation circuit 100 constituted of an oscillation circuit 6 and counter 5 which divides the frequency of the output of the circuit 6 is incorporated in this semiconductor memory containing a memory cell array 1, external address signal decoding circuits 2, and control circuit 4 which controls the active and inactive states of the memory. The external address decoding circuit 2 is controlled by the control circuit 4 and switches an externally inputted address signal and internal generated address signal to each other. Therefore, an internal signal is fetched as an address signal and no specific selecting line is selected even when the chip is inactive. Thus deterioration of the specific selecting line can be prevented.

Description

[Detailed Description of the Invention] [Prior Art] Generally, in a semiconductor memory, a selection line (
X direction: word line, X direction: digit line)
The memory cells at the intersections are selected one by one.

Since the individual capacity of such semiconductor memories is smaller than the capacity required for the entire system, a plurality of semiconductor memories are used to obtain the desired storage capacity. For this reason, some of the semiconductor memories used in the device are in an active state and others are in an inactive state.

In an active semiconductor memory, addresses are generally selected almost evenly, but in an inactive semiconductor memory, an open address may be selected for a long time. In other words, because specific word lines and digit lines are selected for a long period of time, in bipolar semiconductor memories, etc., there is a possibility that current may continue to flow through specific word lines and digit lines for a long period of time. Electromigration is more likely to occur on word lines and digit lines.

[Problems to be Solved by the Invention] The above-mentioned conventional semiconductor memory has the problem that if a specific address is continued to be selected when inactive, specific word lines and digit lines deteriorate quickly and electromigration is likely to occur. There is.

As a countermeasure to this problem, there is a method of increasing the wiring width, but this method increases the area occupied by the wiring, making it impossible to achieve high density, and also increases the wiring capacity, making it impossible to achieve high speed. be.

[Differences between the invention and the prior art] In contrast to the above-mentioned conventional semiconductor memory, the present invention has a built-in oscillation circuit when inactive and an address signal generation circuit consisting of a counter, and an external address signal is fixed. Even in this case, the selection lines of the semiconductor memory are not fixed, but are sequentially selected.

Means for Solving Problem C] A memory cell array composed of a plurality of memory cells, an external address signal decoding circuit for selecting the memory cell, and controlling the active state and inactive state of the semiconductor memory. In a semiconductor memory including a control circuit, an address signal generation circuit is built-in, and switching means cooperates with the control circuit to switch between an externally input address signal and an internally generated address signal.

[Example code] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. Conventional semiconductor memory has a memory cell array 1
, address signal circuit 2, output circuit 3, and chip activation;
In this embodiment, in addition to the conventional semiconductor memory configuration,
The address signal generation circuit 100 is comprised of an oscillation circuit 6 and a counter 5 that divides the output of the oscillation circuit 6.

The address signal decoding circuit 2 is controlled by a control circuit to switch between an externally input address signal and an internally generated address signal. That is, when the chip is inactive, internal signals are taken in as address signals, and when active, external signals are taken in as address signals.

By doing this, the address signal is input even when the chip is inactive, a specific selection line is not selected, and deterioration is reduced.

For example, when considering 16KRAM, there are 128×12B selection lines, and electromigration is 128 times stronger than when a specific selection line is selected.

FIG. 2 is a block diagram showing a second embodiment of the invention.

In the first embodiment, the address generation circuit is always activated, but when the chip is activated, it is advantageous in terms of power consumption and noise to deactivate the address signal generation circuit. .

In the second embodiment, the address signal generation circuit 200 is also controlled by the control circuit 4, and when the chip is activated, the address signal generation circuit 200 is in an inactive state.
The address signal generation circuit 200 controls activation when the chip is inactive.

[Effects of the Invention] As explained above, the present invention has an address signal generation circuit, which generates an address even when inactive, and prevents a specific address from continuing to be selected, which causes deterioration of a specific selection line. Moreover, since the selection line width does not have to be increased, it is effective for semiconductor memories, which will be further miniaturized in the future.

Furthermore, miniaturization reduces wiring capacitance and increases speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the invention, and FIG. 2 is a block diagram showing a second embodiment of the invention. 1 ・ ・ ・ φ ・ ・ 2 ・ ・ ・ ・ ・ . 3 ・ ・ ・ ・ ・ 4 ・ ・ ・ ・ ・ 5 ・ ・ ・ ・ ・ 6 ・ ・ ・ ・ ・ ・ 100, 200

Claims (2)

[Claims] (1) A semiconductor memory including a memory cell array composed of a plurality of memory cells, an external address signal decoding circuit for selecting the memory cell, and a control circuit for controlling the active state and inactive state of the semiconductor memory. A semiconductor memory comprising a built-in address signal generation circuit and switching means for switching between an external input address signal and an internally generated address signal in cooperation with the control circuit. (2) A semiconductor memory according to claim 1, wherein the address signal generation circuit is controlled by the control circuit.