JPH03108750A - Semiconductor memory integrated circuit - Google Patents

Abstract

PURPOSE:To enable reduction in the output wiring region of a Y decoder and in effectualization of layout design of a semiconductor memory integrated circuit by disposing a Y decoder circuit at a position adjacent to at least one of a Y selector circuit and a sense amplifier circuit. CONSTITUTION:The title integrated circuit comprises non-volatile semiconductor memory devices capable of varying memory contents electrically, a semiconductor memory device array 105 that is a array of these semiconductor memory devices, a Y decoder circuit 102 which selects a column direction of the array 105 and a Y selector circuit 104 which switches the column direction line of the above-mentioned semiconductor memory device and the sense amplifier circuit 103. The Y selector circuit 104 is disposed adjacent to the array 105, and the sense amplifier circuit 103 opposite the array 105 with the circuit 104 in between. The Y decoder 102 is disposed adjacent to at least one of the Y selector circuit 104 and the sense amplifier circuit 103.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory integrated circuit, and more particularly to a semiconductor memory integrated circuit including a nonvolatile semiconductor memory device whose storage contents can be changed electrically.

[Prior art] Conventionally, this type of semiconductor memory integrated circuit has an X decoder 30.
1. Y decoder 302. Sense amplifier 303. Y selector 304. A layout diagram of the semiconductor memory device array 305 is shown in FIG. FIG. 5 shows units of reading and writing, usually nibbles and bytes, of an electrically writable and erasable semiconductor memory device.

The way it is called differs depending on the number of pits in the word, etc.
Here, the unit is expressed as 4 pits. In an electrically writable and erasable semiconductor memory device, as shown in FIG. The word line which is the output of the X decoder circuit has its drain connected to the digit line 501.
It consists of a semiconductor device 504 connected to a semiconductor device 504, and a semiconductor device 505 that selects gates for 4 bits. As described above, since the semiconductor device 505 for selecting the gate is required, the semiconductor memory devices for 4 bits are arranged adjacently on the semiconductor substrate.

In the arrangement shown in FIG. 3, the wiring of the output of the However, the width from one end of the semiconductor memory device array to the other end and the height region 310 of the Y decoder outputs are the same, and the area of the wiring area is not large enough, and the wiring is limited due to the storage capacity. Since the parasitic capacitance changes, from this,
The operating speed and power consumption of the decoder 302 change.

Further, FIG. 4 is a layout diagram of another conventional example. In this layout diagram, the X decoder 402 is an array 405 of semiconductor memory devices.
The output wiring of the X decoder 402 runs parallel to the Y selector 404 across the digit line.
There are as many wires as there are outputs of the decoder, occupying an area indicated by 410, and the length of this wire is equal to the number of outputs of the semiconductor memory device.
The number of word lines changes depending on the storage capacity of 05, which changes the wiring length of the Y decoder and changes the wiring parasitic capacitance. That is, as the storage capacity increases, the wiring area 410 for the output of the Y decoder becomes thicker.

FIG. 7 shows a conventional example of a nonvolatile semiconductor memory device that is electrically writable and erasable with ultraviolet light.

In the case of nonvolatile semiconductor memory devices that are electrically writable and erasable with ultraviolet light, there is no restriction that semiconductor memory devices that can read and write simultaneously are placed adjacent to each other as shown in FIG. In the example shown in the figure, semiconductor memory devices that read and write simultaneously are arranged every four pits.

The configuration shown in FIG. 7 will be explained. An X decoder 701 is adjacent to the left side of the semiconductor memory device array 705, a Y selector 704 is adjacent to the top side, and a Y selector 70 is located adjacent to the top side of the semiconductor memory device array 705.
There is a Y decoder output wiring area 708 on the upper side of the wiring area 708, and a sense amplifier 703 is arranged adjacent to the upper side of the wiring area 708.

The X decoder 702 is arranged above the X decoder 701 and to the left of the sense amplifier 703, and is connected to the Y selector 704 through a wiring region 710. At this time,
The decoder 702 has a size in the X direction (horizontal direction in the figure) determined by the X decoder 701 and the semiconductor memory device array 705, and the semiconductor memory device array 705. The wiring area 710 exists in an area with a size in the Y direction (vertical direction in the figure) determined by the Y selector 704, the wiring area 710, and the sense amplifier 703, or the sense amplifier 7
03. The power supply line to the X decoder 701 cannot be arranged well due to the presence of wiring.

[Problem to be solved by the invention] The conventional semiconductor memory integrated circuit described above is shown in FIG.

In the example shown in Figure 4, the wiring length of the Y decoder output changes depending on the storage capacity of the semiconductor storage device, which changes the wiring parasitic capacitance, which changes the operating speed and power consumption of the Y decoder. Finally, a wiring area is required to connect the gate of the Y selector to be selected and the output of the Y decoder, and in the example of FIG. Alternatively, the example shown in FIG. 4 has the disadvantage that the area required is determined by the height of the array of the semiconductor memory device and the number of output lines of the Y decoder. Furthermore, in the electrically writable and ultraviolet erasable nonvolatile semiconductor memory device shown in FIG.
It is used as a storage device for storing professional programs for microcomputers, and is formed on the same semiconductor substrate as the microcomputer or the peripheral circuits of the microcomputer, and has come to be used as a tool for developing professional programs for microcomputers. It's coming. In other words, the professional program depacking process involves storing a professional program for a microcomputer developed by a user in an electrically writable non-volatile semiconductor storage device, and modifying the professional program so that the microcomputer operates as expected. used in the process. When the depacking of the pro program is completed, the user sends the pro program code to the semiconductor manufacturing side as before, and the microcomputer with a built-in read-only semiconductor memory device codes the pro program code onto the semiconductor substrate during the semiconductor manufacturing process. Computers are manufactured and used in large quantities at low cost. Therefore, there is a need for a wide variety of microcomputers with built-in semiconductor storage devices whose storage contents can be changed electrically.In particular, semiconductor storage devices whose storage contents can be changed electrically at a voltage higher than the power supply voltage used by normal semiconductor integrated circuits, e.g. 12.5V or 21V.
Voltages such as V are applied to semiconductor integrated circuits, which not only complicates the process, but also imposes various constraints on the layout design, increasing the complexity of the layout design and making it difficult to improve the efficiency of the design. It has the disadvantage of being a hindrance.

The present invention has been made in view of the above-mentioned conventional circumstances, and it is an object of the present invention to provide a semiconductor memory integrated circuit that reasonably solves the above-mentioned drawbacks.

[Differences between the invention and the prior art] Compared to the above-mentioned conventional semiconductor memory integrated circuit, the present invention requires less wiring area for connecting the output line of the Y decoder and the gate of the Y selector. Even if the storage capacity changes, the operating speed due to the parasitic effects of the wiring
The change in power consumption is small, and the semiconductor memory integrated circuit of the present invention has a substantially rectangular shape regardless of the size of the storage capacity, so it is easy to design the layout of the semiconductor integrated circuit. do it first,
Floor plan design that determines the relative placement of semiconductor integrated circuits can be easily performed, and the layout design of the semiconductor memory integrated circuit portion is almost completed simply by arranging the above-mentioned functional blocks mutually, so high voltage The difference is that layout design constraints can be handled within the above functional blocks, reducing design complexity and increasing design efficiency.

[Means for Solving the Problems] A semiconductor memory integrated circuit of the present invention that achieves the above object includes a nonvolatile semiconductor memory device whose storage contents can be changed electrically, and one or more of the semiconductor memory devices described above. A semiconductor memory device array in which the semiconductor memory devices are arranged in an array, a Y decoder circuit for selecting in the column direction of the array, a sense amplifier circuit and the Y decoder circuit. It consists of a Y selector circuit that switches between the column direction line of the semiconductor memory device and the sense amplifier circuit by an output, the Y selector circuit is arranged adjacent to the array, and the sense amplifier circuit is connected to the semiconductor memory device with the Y selector circuit in between. The present invention is characterized in that the Y decoder circuit is arranged at a position opposite to the storage device array, and the Y decoder circuit is arranged at a position adjacent to at least one of the Y selector circuit or the sense amplifier circuit.

Embodiment FIG. 1 is a layout diagram of an embodiment of the present invention. The semiconductor integrated circuit of this embodiment has an X decoder 101 and a Y decoder 1.
02. Sense amplifier 103. YSe9-IO-Lefter104. Semiconductor storage device array 105° control gate voltage supply line 106. Y selector and sense amplifier wiring area 107. Y address input line 108. X
It consists of an address input line 109. The layout diagram in FIG. 1 shows the layout of each of the above-mentioned circuits on a semiconductor substrate. In this embodiment, the Y decoder 102 is the sense amplifier 1
03 and 107 in the wiring area above the Y selector 104
is placed between. Y in the position shown in Figure 1.
By arranging the decoder 102, the wiring area 10
Wire Y across 7 to the gate of Y selector 104
No area is created for the wiring of the output line of the decoder 102, and the wiring length hardly changes even if the storage capacity of the semiconductor memory device changes. Furthermore, although FIG. 1 shows the case where the output of the sense amplifier 103 is 4 bits, it is 8 bits.
This can be achieved with any number of output bits, whether bit or 16 bits. Note that by arranging the Y decoder 12 as in this embodiment, the wiring from the Y selector 104 to the sense amplifier 103 becomes longer; however, this increase is smaller than the original wiring area 107. There is almost no effect on operating characteristics.

If each circuit is arranged as in the prior art, the wiring area required for connecting the output of the Y decoder 102 and the gate of the Y selector 104 becomes large as the storage capacity increases. In an embodiment of the present invention, Y
As for the dedicated wiring area between the decoder and the gate of the Y selector, the area 310 in FIG. 3 of the conventional example is no longer needed.
The area of this part, [(number of output lines of Y decoder)
×(Wiring width + Wiring spacing)]X[(Number of digit lines)×
(the width of the memory cell in the lateral direction)] is reduced.

In addition, in the conventional example shown in FIG. 4, the area 410 is unnecessary, but the area of this part is [(number of output lines of the Y decoder)×
(wiring width+wiring interval)]X[(number of word lines)×(vertical width of memory cell)] is reduced.

The number of output lines of the Y decoder is 16, the wiring width is 212-μm, the wiring spacing is 2μm, the number of digit lines is 128,
Number of word lines: 128, memory cell width in lateral direction: 8μ
If the width between m and μm is 16 μm, in the case of the conventional example shown in FIG. 3, it becomes 16X4X128X8=655361Lm2, which is about 0. The chip size outside the square area of 26mm+2 can be reduced, and in the case of the conventional example shown in FIG. 4, it becomes 16X4X128X16=131072μm2,
The area outside the square area of about 0.36 μm2 can be reduced.

In addition, in the embodiment shown in FIG. 1, the following functional blocks:
X decoder 101. Y decoder 102, sense amplifier 103. By preparing the Y selector 104.degree. semiconductor memory device array 105 and wiring area 107 as layout data individually and arranging each functional block, it is possible to design the layout of the semiconductor memory integrated circuit. In the conventional example shown in FIG. 3, the arrangement of the Y decoder 302 and the connection area between the Y decoder 302 and the wiring area 310 had to be modified when changing the storage capacity, but in this example In the case of Y Tecotor 102
Including C, the main part of the layout design of a semiconductor memory integrated circuit, including the arrangement of functional blocks D), can be completed, so it can be fully adapted to automated design.

In addition, when designing a large-scale S product circuit, prepare a large number of macrocells (layer I/data that is designed as a circuit block with a certain function is called a macrocell), and select the necessary ones from among those macrocells. In recent years, it has become common practice to design new large-scale integrated circuits by using only macrocells and interconnecting those macrocells.
In these cases, the size of the semiconductor chip of the large-scale integrated circuit is the sum of the size of the cells arranged in the X direction and the wiring area. As mentioned above, when a semiconductor memory integrated circuit is used as a macro cell, the wiring area within the macro cell is greatly reduced, which in many cases also contributes to reducing the area of the semiconductor chip, and the macro cell can be designed to be nearly rectangular. This also contributes to reducing the usable portion of the semiconductor chip 13 4 left between the macrocells and the wiring area between the macrocells.

FIG. 3 is a layout diagram of another embodiment of the invention of FIG. 2;

In this embodiment, the Y decoder 202 is located on the opposite side of the Y selector 204 with the sense amplifier 203 in between. By arranging the X decoder 202 at the position shown in FIG. 2 and wiring it across the wiring area 207 to the gate of the Y selector 204, a region for wiring the output line of the X decoder 202 is created. Moreover, even if the storage capacity of the semiconductor memory device changes, the wiring length hardly changes. Similar to the embodiment shown in FIG. 1, regardless of the number of output bits of the sense amplifier, this embodiment has been described for the case where there are two Y addresses, four Y decoders, and four sense amplifiers. The number of sense amplifiers may not be the same. The number of sense amplifiers is determined by the number of information output simultaneously, and Y
The number of decoders is determined by how much storage capacity is required, so the numbers do not need to be the same.
The present invention can also be implemented in general cases.

5- Also, as in the embodiment of FIG. 1, the following functional blocks: X decoder 201, X decoder 202, sense amplifier 203. )" By preparing the body memory device array 205 and the wiring area 207 individually as layout data for the selector 204° and half 3, it is possible to improve the efficiency of design.

FIG. 6 is a layout diagram of still another embodiment of the present invention.

Similar to FIG. 1, FIG. 6 shows the arrangement of each circuit shown in FIG. 1 on a semiconductor substrate. In this embodiment, the X decoder 602 is located adjacent to the sense amplifier circuit 603 and both face the Y selector 604. Both the X decoder 602 and the sense amplifier 603 are Y
Since it faces the selector 604, the X decoder 60
2 to Y selector 604. The wiring length from the sense amplifier 603 to the Y selector 604 is short and does not change depending on the storage capacity of the semiconductor memory device.

Further, as in the two embodiments described above, by preparing layout data for each functional block, design efficiency can be improved.

FIG. 9 is a layout diagram of an embodiment in which the present invention is applied to an electrically writable/ultraviolet erasable nonvolatile semiconductor memory integrated circuit. Like FIG. 1, FIG. 9 also shows the arrangement of each circuit on the semiconductor substrate. The configuration of this embodiment will be explained. The X decoder 901 has a Y selector 904. The sense amplifier 903 is arranged adjacent to the semiconductor memory device array 905, and the sense amplifier 903 is arranged across the Y selector 904 and the Y decoder output wiring area 908. It is located. The X decoder 901 is operated by an X address input line and a control signal 907, and the X decoder 902 is operated by an X address input line and a control signal 906. The digit line 909 is connected to the digit line 801 of the semiconductor memory device shown in FIG.
are connected as many times as required. A control gate line 802 is connected to the output of the X decoder 901, and a source line 80
3 are all connected to GND in common to the semiconductor memory devices.

By arranging each functional block as shown in FIG. 9, the layout design of the semiconductor memory integrated circuit is almost completed by arranging the functional blocks mutually, making it possible to improve the efficiency of the design. The layout design can be prevented from becoming complicated by making layout design constraints for the high voltage used when changing the memory contents in the design within the functional block. Also X
The wiring length from the decoder 902 to the Y selector 904 is also constant, and can be shortened by passing through the sense amplifier 903. The wiring length changes depending on the position, and the wiring area does not increase, making it possible to design a layout with uniform design quality. In addition, in FIG. 9, the X decoder 902 and the sense amplifier 9
The relative position of 03 can also be as shown in FIGS. 1 and 6.

17-8 [Effects of the Invention] As explained above, it is possible to arrange the Y decoder at a position similar to that of the Y selector or sense amplifier (
By rubbing, it is possible to reduce the wiring area for the output of the Y decoder compared to the conventional technology, so there is an effect that a semiconductor memory integrated circuit with the same characteristics can be realized in a smaller area. In addition, by preparing layout data for each functional block constituting a semiconductor memory integrated circuit and arranging the layout data of each functional block adjacently so that the specified number of pits and outputs are achieved, the semiconductor memory integrated circuit can be This has the effect of making layout design more efficient.

[Brief explanation of drawings]

FIG. 1 is a layout diagram of each circuit of a semiconductor memory integrated circuit according to a first embodiment of the present invention, FIG. 2 is a layout diagram of each circuit of a semiconductor memory integrated circuit according to a second embodiment of the present invention, and FIG. A layout diagram of each circuit of a semiconductor memory integrated circuit in the prior art, FIG. 4 is a layout diagram of each circuit of a semiconductor memory integrated circuit in the prior art, and FIG. 5 is a diagram of an electrically writable and erasable semiconductor memory. Schematic diagram of a collection of devices,
FIG. 6 is a layout diagram of each circuit of a semiconductor memory integrated circuit according to the third embodiment of the present invention, FIG. 7 is a layout diagram of a semiconductor memory integrated circuit according to the prior art, and FIG. 8 is an electrically written and erased with ultraviolet rays. Possible semiconductor record 1! The circuit diagram of the device, FIG. 9, is a layout diagram of a semiconductor memory integrated circuit according to a fourth embodiment of the present invention. 101, 201 601.901...X decoder 102.202
゜602.902...Y Tecotor 103, 20
3゜603.903...Sense amplifier, 104, 20
4゜604.904...Y selector-2〇- 105,205゜605.905...Semiconductor storage device array, 106
．． 206,606...Control gate line, 107, 207°607.908...Wiring area, 108, 2
08゜608.906...Y address human force line, 109,
209; 609.907...X address input line, 110.
210°610, 909・・・・・digit line.

Claims (3)

[Claims] (1) A nonvolatile semiconductor memory device whose storage contents can be changed electrically, an assembly of semiconductor memory devices in which one or more of the semiconductor memory devices are selected at once, and an array of the semiconductor memory devices. a Y decoder circuit that selects the column direction of the array, a sense amplifier circuit, and an output of the Y decoder circuit that switches between the column direction line of the semiconductor memory device and the sense amplifier circuit. comprising a selector circuit, the Y selector circuit is arranged adjacent to the array, and the sense amplifier circuit is arranged at a position opposite to the semiconductor memory device array with the Y selector circuit in between,
A semiconductor memory integrated circuit characterized in that a Y decoder circuit is arranged adjacent to at least one of a Y selector circuit or a sense amplifier circuit. (2) Claim 1, characterized in that the nonvolatile semiconductor memory device whose storage contents can be electrically changed is an electrically writable and erasable nonvolatile semiconductor memory device. semiconductor memory integrated circuit. (3) Claim 1, characterized in that the non-volatile semiconductor memory device whose memory content can be changed electrically is a non-volatile semiconductor memory device that can be written electrically or erased with ultraviolet light. The semiconductor memory integrated circuit described in Section 1.