JPH0313079A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To eliminate the need for lot of high speed S/H circuits and to constitute the entire device inexpensively by extracting a signal including an effective signal component and a noise component and a signal with the noise component only from two output signals obtained from a solid-state image pickup element having two horizontal charge transfer sections. CONSTITUTION:An electric charge generated by photoelectric conversion at a photodetector picture element 10 is transferred to two horizontal direction charge transfer sections 12, 13 by a vertical charge transfer section 11. The horizontal charge transfer sections 12, 13 are driven normally by two horizontal transfer pulses having a phase difference of 180 deg.. Noise at changeover is eliminated from an output of a 1st signal changeover synthesis circuit 3 by a 1st averaging circuit 5 and a reset noise and a 1/f noise are superimposed on an effective signal component. On the other hand, a pulse component due to induction of a reset pulse is eliminated from an output of a 2nd signal changeover synthesis circuit 4 by a 2nd averaging circuit 4 and the reset noise and the 1/f noise are obtained. The noise component is eliminated by a subtraction circuit 9 and only the effective signal component is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a solid-state imaging device applied to a television camera or the like, and specifically relates to a signal readout circuit.

[Prior Art] FIG. 9 is a block diagram showing the configuration of a signal readout circuit in a conventional solid-state imaging device disclosed, for example, in Japanese Patent Publication No. 62-55349. In the figure, (100) is a solid-state image sensor, <101), (102) (103)
are sample and hold circuits (hereinafter referred to as 578 circuits), and (104) is a differential amplifier, respectively.

Next, the operation of the above configuration will be explained.

The output of the solid-state image sensor (100) is divided into two 578 circuits (1
01) and (102,) are respectively input, while (7) and 578 circuits (101) receive sample pulses (sl).
The effective signal portion including noise is sampled from the output of the solid-state image sensor (100). The other 578 circuits (
102) samples an ineffective noise portion of the output of the solid-state image sensor (100) using a sample pulse (S2).

Next, the output of the S/H circuit (1 (12)) is input to the S/H circuit (to3), and this S/H circuit (103) is controlled by the sample pulse (Sl) to output the S/H circuit (to3).
The output of the H circuit (101), that is, a valid signal including noise, and the output of the S/H circuit (1 (13), that is, the noise component) are synchronized, and then only the noise component is extracted by the differential amplifier (104). This method of reading out low noise signals is well known as the correlated double sampling method.

[Problems to be Solved by the Invention] Since the conventional solid-state imaging device is configured as described above, it is necessary to incorporate a low-noise signal readout circuit as described above into a solid-state imaging device having a plurality of horizontal charge transfer sections. When applied, many high-speed S/H circuits are required, which increases device cost. In addition, when the transfer frequency of the horizontal charge transfer section of the solid-state image sensor is high, the sample period is short, so
There was a problem that malfunctions were likely to occur.

This invention was made to solve the above-mentioned problems, and only effective signals among the output signals from a solid-state image sensor having a plurality of horizontal charge transfer sections are transferred to the S/H.
An object of the present invention is to provide a solid-state imaging device that can be read out using a simple circuit that does not use any circuits.

[Means for Solving the Problems] A solid-state imaging device according to the present invention detects an effective charge signal among two charge signals having a phase difference of 180 degrees extracted from a solid-state imaging device having two horizontal charge transfer sections. comprising first and second signal synthesizing means for respectively extracting and synthesizing portions containing signals and portions not containing signals; and arithmetic means for calculating between these first and second synthesized signals. It is characterized by

[Operation] According to the present invention, from among two charge signals taken out from a solid-state image sensor, an effective signal including a noise portion and a signal containing only a noise portion are separated by the first and second signal synthesizing means, respectively. In addition to extracting, synthesizing, and outputting,
By performing calculations between the two composite signals, it is possible to remove the noise portion and output only the valid signal.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a signal readout circuit in a solid-state imaging device according to an embodiment of the present invention. In the figure, (1) indicates a plurality of vertical charge transfer sections and two
Solid-state image sensor having two horizontal charge transfer units, (2)
is a driving circuit for the solid-state image sensor (1), which drives the solid-state image sensor (1) so as to extract two charge signals having a phase difference of 180 degrees from the two horizontal charge transfer sections.

(3) and (4) are two charge signals extracted from the solid-state image sensor (1) according to the horizontal transfer pulse (H) for driving the solid-state image sensor (1) generated in the drive circuit (2). (SL), (S2) and a first and second signal switching/synthesizing circuit which switch and synthesize;
), (S) are the first and second averaging circuits corresponding to the first and second signal switching and combining circuits (3) and (4), respectively, and (7) is the second averaging circuit (6). ), (8) is a delay circuit, and (9) is a subtraction circuit.

FIG. 2 is a diagram showing the specific configuration of the solid-state image sensor (1), in which (1o) is a light receiving pixel, (11) is a vertical charge transfer section, and (12) and (13) are two (14) and (15) are floating charge detection sections; (16) and (17) are reset sections that reset the charge detection sections (14) and (15); (18) and (17) are floating charge detection sections; (19) is an output buffer.

Next, the operation of the solid-state image sensor (1) having the configuration shown in FIG. 2 will be explained.

Charges generated by photoelectric conversion in the light receiving pixel (lO) are transferred by a vertical charge transfer section (11) to two horizontal charge transfer sections (12) and (13). From the vertical charge transfer section (11) to the horizontal charge transfer section (12)
, (13) The charge transfer to (13) is as shown by the arrow in Fig. 2 (
As shown in x) and (y), charges transferred by adjacent vertical charge transfer sections (11) are sent to mutually different horizontal charge transfer sections (12) and (13).

Next, two horizontal charge transfer sections (12).

The charge carried out by (13) is transferred to the charge detection section (14).
.

(15) and output buffer (la
), (19) result in output signals (51), (S2) of the solid-state image sensor (1).

The above two horizontal charge transfer sections (12) and (13)
transfers charges with a phase difference of 180 degrees, so the two output signals (Sl) and (S2
) has the waveforms shown in FIGS. 3(a) and (b). In FIG. 3, the shaded part is the effective signal part corresponding to the charge generated by photoelectric conversion in each light receiving pixel (10), and this effective signal part of the two output signals (Sl) and (52) is The signal parts appear in waveforms that interpolate with each other.

Next, the operation of the embodiment having the above configuration will be explained with reference to the signal waveform diagram of FIG. 4.

Output signal (Sl) of solid-state image sensor (1) shown in diagram N3
, (32) are waveforms that do not contain noise, but in reality they are caused by reset noise due to the reset operation of the charge detection sections (14) and (15) and the output buffer (1
8) By adding 17f noise etc. in (19),
For example, the waveforms are as shown in Fig. 4-(^) and (B).

A horizontal charge transfer section (12) of a solid-state image sensor (1).

(13) is normally driven by two horizontal transfer pulses with a phase difference of 180 degrees, so the solid-state image sensor (1)
The timings of the output signals (SL), (S2) and the horizontal transfer pulse (H) coincide, for example, as shown in FIG. 4(C).

First and second signal switching synthesis circuits (3), (4)
are controlled by the horizontal transfer pulse (l()), and select (AI) and (A2) respectively when the horizontal transfer pulse (I) is at a high potential "H", and when the horizontal transfer pulse (I) is at a high potential "L", (Bt) and (B2), respectively. Therefore, the output of the first signal switching and combining circuit (3) is the two output signals (St) and (S
2), only valid signal portions are alternately selected and output, resulting in an output waveform as shown in FIG. 4(D).

On the other hand, the second signal switching and combining circuit (4) uses a solid-state image sensor (
Of the two output signals (51) and (S2) of 1),
Only the portions other than the valid signals are alternately selected and output, resulting in an output waveform as shown in FIG. 4(E).

Subsequently, the output of the first signal switching and combining circuit (3) is
The switching noise is removed by the averaging circuit (5), and the output is a superimposition of reset noise and 1/f noise on the effective signal component, as shown in Figure 4 (F). .

On the other hand, the second averaging circuit (6) removes the pulse-like component caused by the induction of the reset pulse of the reset operation from the output of the second signal switching/synthesizing circuit (4), and the output is as shown in FIG. ), this results in reset noise and 1/f noise.

The noise component obtained from the second averaging circuit (6) is inputted to the delay circuit (8) after passing through the amplifier (7).
In this delay circuit (8), the output signal is synchronized with the output from the first averaging circuit (5), as shown in FIG. 4()I). Next, the first averaging circuit (9) is input to the subtracting circuit (9), and the effective signal component and noise component are superimposed.
The difference between the output of 5) and the output of the delay circuit (8) consisting only of noise components is taken, and as shown in FIG. 4(I), the noise components are removed and only effective signal components are left. is output.

The amplifier (7) is provided to make the noise components of the two signals input to the subtraction circuit (9) equal in magnitude. Therefore, the amplifier (7) may be provided not between the second averaging circuit (6) and the delay circuit (8) but between the first averaging circuit (5) and the subtracting circuit (9). good.

Further, in the above embodiment, two averaging circuits (5)
A delay circuit (8) was provided to synchronize the noise components output from , (8), but in order to reduce the visually noticeable 1/f noise that becomes sideways noise on the screen, Part 1
Since the /f noise has large power in the low frequency region, sufficient effects can be achieved even if the delay circuit (8) is omitted.

Further, the delay circuit (8) may be omitted if the delay is adjusted in the first and second averaging circuits (5), (8) or the amplifier (7).

Furthermore, in the above example, along the flow direction of No. 43,
Second averaging circuit (6), amplifier (7), delay circuit (8)
), but the same effect can be obtained even if the order of arrangement is changed.

FIG. 5 is a block diagram showing the configuration of a signal readout circuit in a solid-state imaging device according to another embodiment of the present invention. In the same figure, (20), (21), (22)
.

(23) are level shift circuits, (24) and
(25) is a four-quadrant multiplier, (26) and (2B) are negative clip circuits that clip below a predetermined reference voltage;
(27), (29) are positive clip circuits that clip above a predetermined reference voltage, (30), (31)
, (32) are adder circuits, and the other configurations are the same as in FIG. 1, so the corresponding parts are given the same reference numerals and their explanation will be omitted.

Next, the operation of the configuration shown in FIG. 5 will be explained.

First, level shift circuits (20) and (22)
4-quadrant multiplier (24), clip circuit (28), (
The operation of step 27) will be explained with reference to the coefficient waveform diagram of FIG.

The output signal (Sl) of the solid-state image sensor (1) is set to a potential higher than a predetermined reference potential (V ref, ) by the level shift circuit (20), as shown in FIG. 6(A), and The horizontal transfer pulse (Hl) generated in the drive circuit (2) is shifted vertically around the reference potential (V ref, ) by the level shift circuit (22) as shown in FIG. 6 (8). is set to

Then, the four-quadrant multiplier (24) calculates the reference potential (V r
The potential exceeding the reference potential (V re
f,) is configured to operate with a lower potential as a negative potential, and multiplies the output of the level shift circuit (20) and the output of the level shift circuit (22) to
A waveform as shown in Figure (C1) is output.This Figure 6 (C
), the valid signal part including noise is above the reference potential (V ref, ), and the other part is above the reference potential (V ref, ).
V ref, ).

Continuing, the negative clip circuit (26) is connected to the reference potential (V r
Since the signal below ef, ) is clipped, only the effective signal portion containing noise is output from the negative clipping circuit (26), as shown in FIG. 6 ([)). On the other hand, since the positive clipping circuit (27) clips the voltage above the reference potential (V ref, ), only the noise component is output from the positive clipping circuit (29), as shown in FIG. 6(E). be done.

In addition, the other level shift circuit (21), (23),
The operations of the four-quadrant multiplier (25), negative clipping circuit (28), and positive clipping circuit (29) are also similar to those described above, and the signal waveforms of each part are as shown in FIG.

To explain this simply, the output signal (Sl) of the solid-state image sensor (1) is raised to a potential higher than the reference potential (V ref, ) by the level shift circuit (21), as shown in FIG. 7 (8). At the same time, the horizontal transfer pulse (Hl) is set by the level shift circuit (23) so as to shift vertically around the reference potential (V ref, ) as shown in FIG. 7(B). , by multiplying these Ryokawa forces in the 4-quadrant multiplier (25), the result shown in Fig. 7 (C) is obtained.
As shown in FIG. 2, the effective signal component including noise and the other portions are separated into the upper side and the lower side of the reference potential (V ref, ).

Next, the negative clip circuit (28) is used as shown in FIG.
), while only valid signal components including noise are extracted, the clipping of the positive clipping circuit (29)
As shown in FIG. 7(E), only the noise component part is extracted. Note that the two output signals of the solid-state image sensor (1), (
Since (Sl) and (Sl) have a phase difference of 180 degrees, the horizontal transfer pulse (Hl) input to the level shift circuit (23) is different from the horizontal transfer pulse (Hl) input to the level shift circuit (22). Hl) having a phase difference of 180 degrees is used.

Two negative clip circuits (2
6) The output signals from (28) are input to the adder (30) and added, and as shown in FIG. 8(A), only the effective signal portion including noise is synthesized and output. , the output signals from the two positive clip circuits (27) and (29) are input to an adder (31) and added together,
As shown in FIG. 8 (8), a signal in which only the noise component portion is synthesized is output.

Then, the outputs of the adders (30) and (31) are sent to the first and second averaging circuits (5) and (6), respectively.
The waveform is smoothed by the waveform shown in FIG. 8(C) and CD). The output from the second averaging circuit (6) passes through the amplifier (7) and then is input to the delay circuit (8), where it is synchronized with the output from the first averaging circuit (5). .

Note that, like the embodiment shown in FIG. 1, the amplifier (7) separates the noise components contained in the output of the first averaging circuit (5) and the noise components contained in the output of the delay circuit (8). The sizes are set to be equal.

Since the noise component of the output of the delay circuit (8) is inverted, by adding the output of the first averaging circuit (5) and the output of the delay circuit (8) in the adder (32),
The noise components cancel each other out, and only effective signal components are output as shown in FIG. 8(F).

In addition, also in the embodiment shown in FIG. 5, the arrangement of the second averaging circuit (6), the amplifier (7), and the delay circuit (8) may be replaced. Furthermore, the amplifier (7) may be provided between the first averaging circuit (5) and the adder (32) instead of between the second averaging circuit (6) and the delay circuit (8). .

Furthermore, regarding the reduction of 1/f noise, a sufficient effect can be obtained even if the delay circuit (8) is omitted, and the first and second averaging circuits (5), (6) or the amplifier (7) If configured to adjust the delay circuit (8), the delay circuit (8) can be omitted.

Furthermore, in each of the above embodiments, a horizontal transfer pulse is used to drive the solid-state image sensor (1), but it is not necessary to use this pulse in particular, and the pulse is synchronized with the output signal of the solid-state image sensor (1). Other pulses may be used as long as they are the same.

In addition, the reference potential (V ref,) is set to the solid-state image sensor (1
) output signal (SL), if set lower than the potential of (52), the level shift circuit (20), (21)
can be omitted, and if the reference potential (V ref, ) is set at the center of the horizontal transfer pulse, the level shift circuit (22),
(23) can be omitted.

Also, the horizontal transfer pulses ()12) and (Hl) input to the level shift circuits (22) and (23) should be replaced, or the level shift circuits (20) and (
21), the output signal (51) of the solid-state image sensor (1),
(S2) is set below the reference potential, only non-inverted noise components are obtained from the negative clip circuit (2B) and (28), and the positive clip circuit (27
), (29) yields a portion of the effective signal component that includes the inverted noise, resulting in a good noise-removed and inverted signal from the adder (32).

[Effects of the Invention] As described above, according to the present invention, a signal containing an effective signal component and a noise component is selected from among two output signals obtained from a solid-state image sensor having two horizontal charge transfer sections. The structure extracts and synthesizes a signal with only a noise component and a signal with only a noise component, and removes the noise component by performing calculations between these synthesized signals, so it is possible to eliminate the large number of high-speed signals required in the conventional correlated double sampling method. An S/H circuit can be eliminated, and the entire device can be constructed at low cost.

Moreover, even if the horizontal transfer frequency becomes high, a malfunction unlike the conventional example using an S/H circuit does not occur, and a low-noise signal can be stably read out.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a configuration of a signal readout circuit in a solid-state imaging device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a specific configuration of a solid-state imaging device, and FIG. 3 is similar to FIG. The output waveform diagram of the solid-state image sensor shown in FIG.
5 is a block diagram showing the configuration of another embodiment of the present invention, and FIGS. 6, 7, and 8 are each an embodiment shown in FIG. 5. FIG. 9 is a block diagram showing the configuration of a signal readout circuit in a conventional solid-state imaging device. (1)...solid-state image sensor, (3), (4)...
Signal switching synthesis circuit, (5), (5)...Averaging circuit, (7)...Amplifier, (8)...Delay circuit, (9
)...subtraction circuit, (11)...vertical charge transfer section, (12), (13)...horizontal charge transfer section,
(20), (21), (22), (23)
...Level shift circuit, (24), (25)...
・4-quadrant multiplier, (2B), (28)...negative clip circuit, (273, (29)...positive clip circuit,
(30). (31), (32)...Adder. Note that the same reference numerals in each figure indicate the same or corresponding parts. Fig. 4 Output η Fig. Fig. 6 Fig. Fig. ref

Claims (1)

[Claims] (1) A solid-state image sensor having a plurality of vertical charge transfer sections and two horizontal charge transfer sections that receive every other charge signal from the vertical charge transfer sections; A drive circuit that extracts two charge signals with a phase difference of 180 degrees from the directional charge transfer section, and a first synthesis that extracts and synthesizes the portions containing valid signals from the two extracted charge signals. A first signal synthesizing means outputs a signal, and a second signal synthesizing means extracts and synthesizes a portion of the two charge signals that does not include a valid signal.
a second signal synthesizing means for outputting a synthesized signal;
and arithmetic means for calculating between the second composite signals and outputting only valid signals.