JPH03147039A - Address conversion device for data processing system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing system, and particularly to an address translation device suitable for operating a system by logically dividing it into a plurality of partitions.

[Conventional technology]

2. Description of the Related Art Conventionally, a system for operating a data processing system by logically dividing it into a plurality of partitions is disclosed in Japanese Patent Laid-Open No. 37636/1983. This is one implementation form of a virtual computer system that can operate a plurality of operating systems (OS) under a so-called one real computer system. This is now called a logically partitioned virtual computer system.6 In a virtual computer system, the real computer system that realizes it (hereinafter referred to as the host real computer system) and the same or similar architecture. Multiple virtual machines (VM: V
virtual machine).

Each VM can run concurrently, and its operating system runs on the VM.

In such a virtual machine system, the O8 on each VM generates a logical address when performing memory access. This logical address is ultimately converted into an address in the system's main memory (this is referred to as a system main memory address) in order to access the system's main memory. In order to perform this address translation, the host real computer uses an address translation buffer (TLB: Tra
nslationLook-aside Buffer
). The system main memory address corresponding to the above-mentioned logical address is registered in the TLB. Therefore, if the logical address is registered in the TLB, address translation can be performed at high speed. Furthermore, if it is not registered in the TLB, conversion is performed using a conversion table configured by O8 in the main memory.

These are well known facts.

Now, in a virtual machine system, O8 on multiple VMs generates logical addresses at the same time, so this is
There arises a need to distinguish between

Even if the logical address is the same between VMs,
This is because they generally correspond to different system main memory addresses.

For this purpose, in addition to the logical address, 7M
It is fine to have an identifier, but the VMfi used by the software
The identifier is, for example, an 8-byte name or a 4-byte VM control block address, and the number of bits is too large to be included in the TLB.

For this reason, conventionally, as shown in Japanese Patent Application Laid-Open No. 360-57449, the 7M identifier used by software is stacked in a memory such as a local storage, and the entry number of the stack is registered in the TLB. For example, if the total number of entries in the stack is 16, the TLB contains 4 entries.
It is sufficient to prepare the bits in advance, and the number of required bits of the TLB can be reduced. This stack entry number is used by the hardware TLB as a 7M identifier.

The same TL also applies to logically partitioned virtual machine systems.
It is presumed that B is used.

In this logically partitioned virtual computer system, the main storage of the system is divided into areas, as shown in Figure 2.
Each area is used as the main memory of the virtual machine. Therefore,
In such a system.

Since there is a one-to-one correspondence between an area and a virtual machine, the area identifier and the virtual machine identifier have equivalent meanings.

[Problem to be solved by the invention]

Although the above-mentioned conventional technology allows distinguishing logical addresses between VMs, this method, ie.

Having a stack of software VMi identifiers has the following problems.

(1) The overhead of checking the contents of the stack is large.
When starting a VM, it must check whether its software VMm identifier exists in the stack. If it exists, the entry number at that time, that is, the hardware VJI identifier, must be determined; if it does not exist, it must be newly registered and the entry number must be determined.

(2) There are various problems in the processing when the above-mentioned stack overflows. When the above stack overflows, any entry in the stack must invalidate one entry, and then the corresponding TLB entry must also be invalidated.

When choosing which entry to invalidate, for example, it is common practice to select the oldest used entry. To do this, the stack structure must be such that the oldest used entry can be easily found. There must be. Therefore, the overhead of stack processing increases.

To avoid this, there is a method of purging the entire stack when the stack overflows, but at this time, all TLBs must also be purged. Therefore, the performance of the system will be degraded.

In this way, in the conventional technology, by having a stack, the number of bits of the hardware VM identifier in the TLB can be reduced, but on the other hand, the problem is that the overhead for maintaining the stack increases. There is.

The purpose of the present invention is to solve these problems. That is, it is possible to provide a method for keeping the number of bits of a hardware VM identifier in a TLB relatively small in a logically partitioned virtual computer system without using a stack of software VMra identifiers. 9. This is an object of the present invention.

[Means to solve the problem]

In order to achieve the above object, the present invention uses the following means.

In other words, in a logically partitioned virtual computer system,
Divide the system's main memory into multiple areas. Each area is used as the VM's main memory. Here, each region may satisfy certain boundary conditions. This is because in order to guarantee the performance of O8 on the VM, a certain amount of space must be provided.

For example, there are 1 megabyte (MB) boundaries, 16MB boundaries, 32MB boundaries, and 64MB boundaries. Currently, the maximum main memory of the system is 2 gigabytes (QB).
That is, 202O48 (i.e. 31 bits),
Therefore, the starting point address (α) of the above area is IMB (
In other words, when the boundary is 20 bits, it is 11 bits (10 bits).
=31-20). Similarly, the starting point address α is

In case of 16MB boundary, 32MB boundary, 64MB boundary,
Each starting point address α has 7 bits.

It will be expressed in 6 bits and 5 bits.

On the premise of the above restriction on the starting point address α, the following means are provided.

(1) Means for holding in the CPU the starting point address α of the main storage area owned by the currently running VM (2) In the TLB, the starting point address α of the main storage area owned by the VM currently running
Means for registering the starting point address of the main storage area of M (3) In the TLB coincidence judgment control logic, the starting point address of the main storage area of the currently running VM in the CPU and the TLB
By providing these means, it is possible to exclude the conventional software VMi identifier stack in the address translation logic of the host real computer. Furthermore, by limiting the boundary conditions of the starting point address of the area, the number of bits for expressing the starting point address can be reduced.

Furthermore, by registering this reduced starting point address in the TLB and using it as a hardware-based VM identifier, it is also possible to prevent an increase in the number of bits in the TLB.

Thereby, conventional problems can be solved.

Furthermore, when the host actual computer operates on a single O8,
This is called a native mode, and in this native mode, the main storage device is not logically divided.

Furthermore, VM@Besshi Shirako itself becomes a key point.

Therefore, the region origin address field in the TLB is not required.

Such native mode also includes means for concatenating the region start address field in the TLB and the system main memory address field to increase the number of bits that can represent the system main memory address.

At this time, in the match determination control when searching the TLB, there is also a means for not performing the comparison determination of the starting point address.

By these means, when the real computer operates in native mode, the number of bits representing the system main memory address in the TLB can be increased. This gives the TLB the ability to address larger system main memory.

[Effect]

These means operate as follows.

(1) First, when starting a VM in an area.

The starting point address α of the area is set in the register.

(2) When the O8 on the VM generates a logical address, it first tries to convert it to a system main memory address by searching the TLB. This is a well-known address translation operation.

(3) At the beginning of system operation, nothing is registered in TLB, so by searching the address translation table created by O8 in main memory 2, the logical address is transferred to the system master. Convert to storage address. This address translation table is created by O8 on the above VM,
This is a table to manage. These are also well known address translation operations.

(4) As a result of the above, the system main memory address corresponding to the converted logical address is registered in the TLB. This is also a well-known operation.

(5) Furthermore, in the present invention, the starting point address α of the area is also registered as the XMffi identifier in the TLB at the same time as 'I-8' in (4).

(6) From now on, when the same logical address is generated from the same VM, in the address translation by TLB, the matching condition of the above area starting point address is also determined at the same time as the matching condition of the logical address. Converts a VM's logical address to a system main memory address.

As described above, it is possible to distinguish logical addresses between VMs by the start address of the area, eliminate the need for a stack of software VM identifiers, and reduce the number of bits of the VM white as hardware in the TLB. .

Furthermore, when the actual computer is in native mode, the TLB
The above-mentioned v M il identifier, that is, the area start address field and the system main memory address field can be concatenated to form one system main memory address with a larger number of bits.

This allows 'T" t even when in native mode.
, B can be effectively used.

〔Example〕

Hereinafter, one embodiment of the present invention will be explained with reference to FIG.

FIG. 1 is an address translation device that includes one feature of the present invention in a data processing system. In FIG. 1, the difference from the conventional one is that the address translation buffer (TLB) 21 is
The starting point address (α) of the area is included as a VM identifier used by the hardware. The feature of the present invention is the registration of the area starting point address α in the TLB 21 and the comparison logic of this α when searching the TLB 21. In other respects, there is no difference from the conventional technology.

In order to explain the above-mentioned area, FIG. 2 will be explained.

40 in FIG. 2 is the main storage device of the real computer (that is, the host computer) that supports the virtual computer system, and it is the area 0. Area 1. . . . indicates a state where the area is divided into area 4.

This area is logically divided. How to divide is managed by the hypervisor existing in area 4. Area I (occupies the high-order address part of main memory 10. Its starting point address) (o is fixed at system startup.) From Io, in the first place, there is software called a hypervisor, and each VM schedule.

For example, area 1 occupies the main memory from address αl to α2 (excluding α2). VM], the main memory 41 is mapped to area 1, and its addresses range from 0 to α2-
up to α1 (not including α2-α1). Furthermore, V
When the OS 1 on M1 configures the virtual space 42, the OS 81 configures an address translation table on its main memory 41, thereby mapping the virtual space 42 to the main memory 41. The method shown in FIG. 2 above is a well-known technique.

As is clear from the above, the VM identifier and the area identifier have equivalent meanings.

Further, FIG. 3 will be described to discuss the starting point address of each area.

The starting point address (α) of each area in FIG. 2 has a - constant boundary restriction. Figure 3 shows 1 megabyte (IMB=2
20B) Boundary, 16MB Boundary, 32MB B Boundary, 64M
It shows the number of bits of α in case of B boundary. That is, in the above order, the number of bits of α is 11 bits, 7 bits, and 6 bits.

It is 5 bits.

The number of bits for this α is determined by the TLB 21 shown in FIG.
It is highly dependent on the capacity of In other words, if the capacity of the field that registers α in TLB 21 is 7 bits at most, the boundary conditions are 16 MB boundary, 32 MB boundary, 6
4MB boundaries are allowed.

The boundary condition of this area starting point address α is determined by the hypervisor reading the CPU feature when starting up this logically partitioned virtual computer system.

The size of the registration field of this α in TLB21 is C, PU
Since each feature is different, it is given as a CPU feature.

When the hypervisor starts up the system, it reads this information and determines the boundary conditions for the area starting point address α.

A system operator then determines each region based on the boundary conditions. Alternatively, based on the VM directory, when the VM is logged on, an area that satisfies the main memory size defined in the directory is determined.

As shown in FIG. 3, providing a boundary condition at the starting point address α of the area is no different from the prior art.

In the logically partitioned virtual computer system shown in FIG. 2, the present invention is based on the fact that as the size of the system main memory 40 increases, the area size also increases, as shown in the TLB 21 in FIG. In the operation of , the number of bits for expressing α tends to become smaller. Paying attention to this point, in the present invention, the α
This means that it is registered.

Here, returning to FIG. 1 again, the operation will be explained.

When the hypervisor starts a VM in an area, the system main memory read data causes the start address α of the area to be S A R (StartAddress
Register) is set to 10, and the end address β of the area is E A R (End Address R
egister) is set to 11. In order for O8 to configure its virtual space on the VM, it configures a segment table and sets its start address (STO) to STOR (Se
gment Table Origin Register
er) Load into 12. The logical address generated by O8 on the VM is LAR (Logical Addr).
ess Register) is set to 13. These operations are the same as before.

The logical address (x) in LAR13 is initially TLB
21, and is therefore converted into a system main memory address by the dynamic address translation mechanism DAT20. DAT20 is the current area starting point address α in 5AR10, the current area ending point address β in EAR11, and 5TOR.
The starting address STO of the segment table configured by O8 on the currently running VM in 12, the page address part LA of the logical address (x) in LAR13 is input, and the O8
The segment table and page table of the LA are searched to determine the corresponding system main memory page address PA.
and set it in register MAR19 via line 35. At this time, the address DX within the page is the line 37
It is directly set to the lower level of MAR19 via . Furthermore, the area end address β in register EARII is used to check whether there is an access outside the area, and if there is an access, an address exception signal is generated on line 34 and a program interrupt is generated. generate. The above operation of the DAT 20 is the same as the conventional one.

Address conversion by DAT20 is successful without exception and MA
Assume that it is set to Rl9. At this time.

The converted system main memory page address PA in MAR19 is written to the corresponding entry in TLB21 via line 38. TLB2]-, that is, the corresponding column of TLB21, is determined by hashing a portion of the page portion LA of the logical address of LAR13.

This Ram decision is TLB@Obe TLB, C14
L: I will do more. In this way, T
The area starting point address α, which is the contents of 5ARIO, the segment table starting point address STO in 5TOR12, and the page portion LA of the logical address in LAR13 are also set in the corresponding column of LB2I. After the logical page address LA and the corresponding system main memory page address PA are registered in the TLB 21 as described above, the logical address in the LAR 13 is quickly converted to a system main memory address by the TLB 21, regardless of the DAT 20. be done.

Among the above operations, the only difference from the conventional method is that the starting point address α of the area is registered in the TLB 21, and the rest is the same as the conventional method.

The address translation method using TLB will be described below.

The logical address (x) in the LAR 13 is converted into a system main memory address by the TLB 21 using a well-known set-associative method. That is, X is the page address portion LA
and an address part within the page.

The control unit TLBC14 of the TLB 21 receives the LA and hashes a part of it, thereby controlling the TLB 21.
Decide where (column) to register.

Contents α of the starting point address field of the TLB entry in that column, contents STO of the segment table starting point address field, contents LA of the logical address field,
Contents of the corresponding system main memory address field PA
9, comparator 15, comparator 16. Comparator 17.
It is read out to memory address register MAR19. At this time, at the same time, the comparator 15 compares α sent from the TLB with the contents (α) of the register 5ARIO containing the starting point address of the area of the currently running VM, and the result is shown on the line 33. The signal is sent to the AND gate 18 via the . Moreover, the STO read from TLB21 is
It is compared with the segment table starting point address ST○ in the register 5TOR12 of the currently running VM by the comparator 16, and the result is sent to the same AND gate 18 as described above.

Further, the LA read from the TLB 21 and the LA in the logical address register LAR13 are compared by the comparator 17, and the result is sent to the same <AND gate 18.

The output of AND gate 18 is sent to memory address register 19.
The content of PA is determined. That is, comparator 15,
16. Only when all comparisons in 17 match, MARl
, 9 is determined. At this time, the in-page address DX in the logical address 13 remains unchanged as MARl.
It is set at the lower end of 9. The above is T L B 2-]-
This is an address conversion method based on

The difference between the above TLB address conversion operation and the conventional one is as follows.
The only difference is that the starting point address α of the area is used as a comparison condition, and the rest is the same as the conventional method.

As understood from the above, logical addresses in an area can be distinguished by the starting point address (α) of the area, and there is no need to separately provide a stack of VM identifiers as seen in the prior art.

Since the number of bits for expressing the starting point address (α) of the area can also be significantly reduced, the number of bits of the TLB can also be suppressed. This allows the overhead of managing a stack of VM identifiers to be eliminated. Furthermore, it is possible to prevent an increase in the number of bits in the field used as the 7M identifier of the TLB.

FIG. 4 shows a second embodiment of the invention.

The difference from FIG. 1 is that there is a native mode flag 45, and the start address of the TLB 21 area (
There is a selector 41 that selects the value to be input into the storage field of α).

The inputs of the selector 41 are the area starting point address (α) and the upper part of the register MAR'19'. The former is given via line 31 from register 5 ARIO, and the latter is
is provided via line 40.

Register MAR'19' is register MA in FIG.
Only the upper part is longer than R19. The upper part is
It has the same size as the storage field for the area start address (α) of the TLB 21.

When the content of the flag 45 is f=1, the output of the selector 41 is as follows:
The data is output and input to the relevant section of the TLB.

Furthermore, there is a selector 42, which includes TLB21
The value of the area address (α) field of is input via line 32. When the output of the selector 42 is the content f=1 of the flag 45, that is, the native mode, the input value is output to the line 46 side and set in the upper part of MAR'19'.

Furthermore, there is an OR gate 43, which has the above f=1,
That is, in native mode there is always a 1 on line 33'.
is output. As a result, in the above case, the comparator 15
results are ignored.

When the value f=o of the flag 45, that is, in non-native mode, the output of the selector 41 is the starting point address of the area (
α), and the contents of register 5ARIO are input to selector 41 via line 31.

It is output to the TLB21 side.

Furthermore, when f=o, the output of the selector 42 is:
is applied to comparator 15. That is, the area starting point address (α) of the TLB 21 is input to the comparator 15, and is compared with (α) of the area starting point address (the contents of the register 5ARIO) of the currently running VM. Furthermore, when f=o,
The output of the OR gate 43 is the same as the output of the comparator 15, and is input to the AND gate 18 via a line 33'. Further, when f=o, the output of the selector 42 is not output to the line 46 side.

Nothing is set in the upper part of MAR'19',
It remains at the initial value O.

As is clear from the above, when the flag f=0, it is a non-native mode, and the system operation of FIG. 4 at that time is exactly the same as the system operation of FIG. 1.

f=1. That is, when in native mode.

The contents of register 5ARIO have no effect on the operation.
The area start address field (α) of TLB 21 is concatenated with the system main memory address field PA to represent a larger system main memory address. At this time,
The field α occupies the upper address bits. The system main memory address concatenated in this way is the register MA
It is set to R'19'.

As can be seen from this, when f=1, TLB2
The area address storage field (α) within 1 can be used as a means of representing a larger system main memory address.

f=1. That is, in the native mode, the area is not divided into the system main memory and the area, so the area starting address in the TLB is not necessary.

However, the native mode flag 45 and selector 41.
42. Due to the action of OR gate 43, the origin address field can be used to represent a larger system main memory address. This allows effective use of the TLB field.

〔Effect of the invention〕

According to the present invention, there are the following effects.

(1) In a logically partitioned virtual computer system, VM
Eliminating the need to create a stack of identifiers, this
Maintenance overhead of the stack in address translation can be eliminated.

(2) Reduce the number of bits required to represent the starting point address of the area into which the system main memory is divided, and register it as the VMm identifier or area identifier of the address translation buffer (TLB). This makes it possible to distinguish logical addresses between VMs, and to limit the number of bits in the VMi identifier field of the TLB.

[Brief explanation of the drawing]

1 and 4 are hardware block diagrams of an address translation device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing division of main memory in a logically partitioned virtual computer system, and FIG. 3 is an area starting address FIG. 3 is a diagram showing the number of bits of α. 10...Register containing area start address α (SAR
), 11...Register containing area end address β (E
AR), 12... Register containing the segment table starting point address (STOR), 13... Register containing the logical address (LAR), 14... Address translation buffer (TLBC), 19... Address after address translation register (MAR), 20... dynamic address translation mechanism (DAT), 21... address translation buffer (T
LB), 40...System main storage device. Susispay-i1tsudenden:l:112. . 4) Kaiyu -, lrfu 1st prisoner lρ Jakugou

Claims (1)

[Scope of Claims] 1. Operating a plurality of operating systems, logically dividing the main storage device of the data processing system into a plurality of areas, and using the area as its main storage area by the operating system; In a data processing system in which the operating system generates a logical address in its main memory area and has an address translation buffer that converts the logical address to a main memory address of the data processing system, the origin of the main memory area is located in the address translation buffer. An address translation device for a data processing system, comprising means for storing an address as a virtual machine identifier or an area identifier. 2. The address translation device for a data processing system according to claim 1, wherein the data processing system has a native mode, and in the native mode, a field and a system for storing a starting point address of the main storage area in the address translation buffer. 1. An address conversion device for a data processing system, comprising means for connecting a field storing a main memory address of the data processing system and using the field as a field representing one main memory address of the data processing system. 3. The address translation device for a data processing system according to claim 1, comprising means for storing the number of bits for representing the virtual machine identifier or area identifier in the address translation buffer as a feature of the CPU, and means for reading it. An address translation device for a data processing system characterized by: