JPH03150850A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PURPOSE:To improve the reliability by forming sidewalls consisting of the residual of an insulator along the sidewalls of a gate electrode and implanting low-concentration impurities with the sidewalls used as masks and thermally diffusing low-concentration impurities to form low-concentration impurity regions. CONSTITUTION:Sidewalls 15 consisting of the residual of a first insulator are formed along the sidewalls of a gate electrode 4 and low-concentration impurities implanted with the sidewalls 15 used as masks are thermally diffused to form low-concentration impurity regions 5. Therefore, the effective gate length can be increased, the sufficient voltage resistance can be maintained, fewer hot carriers are produced, and the electric field of a drain region is relaxed. Thereby deterioration of a semiconductor device is arrested and the reliability improves.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device and a method for manufacturing the same.

[Conventional technology]

As semiconductor devices become more highly integrated, patterns become finer and driving performance improves. However, as the electric field strength of the depletion layer in the drain region increases, transistors tend to deteriorate due to hot carrier effects. Therefore, in order to alleviate the electric field strength of the depletion layer in the drain region, Lightly Doped Dr.
ain (LDD) structure is generally used, and Complem of the structure adopting this LDD structure
antaly Metal Oxide 5esico
2. Description of the Related Art Semiconductor devices having (0MO3) type transistors and the like are being manufactured.

FIG. 3 shows a cross-sectional structure of a semiconductor device having an MO5 type transistor adopting an LDD structure.
An element region A surrounded by field oxide films 2 for element isolation formed by thermal oxidation is set on the main surface of a semiconductor substrate (hereinafter referred to as a silicon substrate) 1 made of silicon single crystal. ing. And this element area A
A thin gate oxide film 3 is formed at the center of the surface, and a gate electrode 4 made of a polysilicon film of a predetermined thickness is formed to cover this.

Further, inside this element region, low concentration impurity (p-) regions 5, 5 are formed by implanting and thermally diffusing a low concentration impurity such as boron using the gate electrode 4 as a mask. On the other hand, side walls 6.6 are provided on the sides of the gate electrode 4, which are formed by anisotropically etching an insulating film such as silicon oxide deposited by CVD or the like. Further, the gate electrode 4 is formed around these low concentration impurity regions 5.5.
A high concentration impurity (p) region 7.7 is formed by implanting and thermally diffusing boron as a high concentration impurity using the side wall 6.6 as a mask. and the low concentration impurity region 5
A source/drain region 8.8 is formed by each of these regions.

On the other hand, the surface of the element SI 31i A including the gate electrode 4 and the sidewalls 6.6 is covered with a silicon oxide film 9 of a predetermined thickness deposited by CVD or the like. A contact hole 10.10 formed by selectively removing the source/drain region 8.
8 Each surface is exposed. Then, a contact hole 10° is formed on the silicon oxide film 9 by selectively removing a conductive film of a predetermined thickness made of aluminum or the like deposited by the Yubafuta method or the like using a photolithography technique. Wiring layers 11 and 11 are formed which are electrically connected to the source/drain regions 8 and 8 via 10, respectively.

[Problem to be solved by the invention]

Incidentally, in the semiconductor device having the conventional structure, although it is possible to reduce the gate length and improve the drive capability through miniaturization, the effective gate length is As a result, the short channel effect increases and it may become impossible to maintain a sufficient breakdown voltage. Also,
As the drive capability increases, the generation of hot carriers increases, resulting in deterioration of the transistor due to hot carrier capture not only in the gate oxide film 3 but also in the sidewall 6. This also led to the inconvenience that credibility was compromised.

Furthermore, it is difficult to form the conventional LDD structure with the optimum concentration distribution, and it is difficult to simultaneously form the PMO5 type and NMO3 type O3 transistors in the best performance when constructing the 0MO3 type transistor. Therefore, if the gate lengths are made equal, it is necessary to reduce the performance of one of them, or to use PMOs with different gate lengths.
A 0MO3 type transistor must be formed by a 3 type and an NMO3 type O3 transistor, and this has become one of the factors that hinders the improvement in performance and miniaturization of semiconductor devices.

The present invention was devised in view of these disadvantages, and an object of the present invention is to provide a semiconductor device and a manufacturing method thereof that can improve reliability, achieve high performance, and achieve miniaturization. It is an object.

[Means to solve the problem]

A semiconductor device according to the present invention includes: a gate electrode formed on a surface of an element region of a semiconductor substrate; a low concentration impurity region formed inside the element region along sidewalls of the gate electrode; a high concentration impurity region formed around the region, a remaining portion of a first insulator remaining along the sidewall of the gate electrode and covering the low concentration impurity region, and a periphery of the remaining portion of the first insulator. and a remaining portion of the second insulator remaining in the second insulating material and covering a portion of the high concentration impurity region.

Further, the method for manufacturing a semiconductor device according to the present invention includes a step of forming a gate electrode on the surface of an element region of a semiconductor substrate, and covering the entire surface of the element region including the gate electrode with a first insulator. a step of etching the first insulator to leave only a portion along the sidewalls of the gate electrode; and a step of etching the first insulator to leave only a portion along the side walls of the gate electrode, and etching a layer inside the element region using the gate electrode and the remaining portion of the first insulator as a mask. a step of implanting a concentrated impurity and then thermally diffusing it; a step of completely covering the surface of the element region including the gate electrode and the remaining portion of the first insulator with a second insulator; etching the material to leave only the peripheral portion of the remaining portion of the first insulator, and etching the inside of the element region using the gate electrode and the remaining portions of the first insulator and the second insulator as masks. This method is characterized by including a step of injecting high concentration impurities and then thermally diffusing the impurities.

[Effect]

In the present invention, a sidewall made of the remaining portion of the first insulator is formed along the sidewall of the gate electrode, and low concentration impurities are implanted using this sidewall as a mask and then thermally diffused. Since high concentration impurity regions are formed, the distance between the low concentration impurity regions formed facing each other, that is, the effective gate length increases, making it possible to maintain sufficient breakdown voltage and Generation of carriers will be reduced, and the electric field in the drain region will be relaxed.

〔Example〕

Embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described below with reference to the drawings. In explaining this embodiment, first, the configuration of the semiconductor device will be explained, and then the manufacturing method thereof will be explained.

FIG. 1 is a cross-sectional view showing the structure of a semiconductor device l including an MO3 type transistor adopting an LDD structure, and FIG.
a) to (e) are process cross-sectional views showing the steps of the manufacturing method. In addition, these figures 1 and 2 (a) to (e)
In the figure, parts that are the same as or correspond to those in FIG. 3 showing the conventional example are given the same reference numerals.

This semiconductor device includes, for example, an N-type silicon substrate 1, on the main surface of which a field oxide film 2.sub.2 for an element component surrounding an element region A is formed.

A thin gate oxide film 3 is formed at the center of the surface of the element region A, and a gate electrode 8i4 made of a polysilicon film of a predetermined thickness is formed to cover this thin gate oxide film 3.

In addition, a low concentration impurity (p-) 6N region 5.5 is formed by implanting and thermally diffusing low concentration impurities inside the element region A along the side wall of the gate electrode 4, while around it. High concentration impurity (p) formed by implanting and thermally diffusing high concentration impurity
A +i region 7.7 is formed, and each of the high concentration impurity layer 7 and the low concentration impurity layer 5 constitutes a source/drain region 8.8.

Furthermore, a sidewall 15.15 is provided along the sidewall of the gate electrode 4 formed on the element region A, and is formed by anisotropically etching a first insulating film made of a silicon oxide film or the like. Each sidewall 15 covers the low concentration impurity region 5. Additionally, sidewalls 16.16 are provided around each of these sidewalls 15.15, which are formed by anisotropically etching a second insulating film made of a silicon oxide film or the like. covers a part of high concentration impurity region 7.7.

Furthermore, the gate electrode 4 and the side walls 15 to 1
The surface of the element region including 6 is covered with a silicon oxide film 9 of a predetermined thickness, and contact holes 10.10 formed in this silicon oxide film 9 lead to the surfaces of the source and drain regions 8.8. is exposed. A wiring layer 11.11 made of aluminum or the like is formed on this silicon oxide film 9, and is connected to the wiring layer 11.11 along these wirings and the source/drain regions 8, 8 through contact holes 10, 10. It is conductive.

Next, a method for manufacturing a semiconductor device according to this embodiment will be explained based on FIGS. 2(a) to 2(e).

First, for example, a field oxide film 2 for element isolation surrounding the element region A is placed on the main surface of the N-type silicon substrate 1.
．． After forming gate oxide film 2 by thermal oxidation, a thin gate oxide film 3 is formed at the center of the surface of element region A. and,
After depositing, for example, a polysilicon film doped with phosphorus and having a predetermined thickness over the entire surface of the element region A including the gate oxide film 3, using a CVD method or the like, this polysilicon film is deposited using a photolithography technique. The gate electrode 4 as shown in FIG. 2(a) is formed by patterning. Note that doping with phosphorus has the effect of reducing wiring resistance.

Next, the surface of the element region A including the gate electrode 4 is completely covered with a first insulating film made of a thin silicon oxide film or the like formed by a CVD method or the like.
Then, this first insulating film is anisotropically etched by reactive ion etching or the like to leave only the first insulating film along the side walls of the gate electrode 4, thereby forming a second insulating film.
A sidewall 15.15 made of the remaining portion of the first insulating film is formed as shown in FIG. 15(b). Further, the gate electrode 4 and the remaining portion of the first insulator, that is, the sidewall 1
5.15 as a mask, a low concentration impurity such as boron is implanted into the inside of the element region A. When the implanted impurity is thermally diffused, a low concentration impurity region 5.5 as shown in FIG. 2(c) is formed.

After that, gate electrode 4 and sidewall 15.15
The surface of the element region A including the second insulating film is entirely covered with a second insulating film made of a silicon oxide film or the like having a predetermined thickness formed by CVD or the like.

Then, this second insulating film is anisotropically etched by reactive ion etching or the like to leave only the peripheral portion of the sidewall 1515 formed along the side wall of the gate electrode 4, as shown in FIG. 2(d). A sidewall 16.16 made of the remaining portion of the second insulating film is formed as shown in FIG. Subsequently, a high concentration impurity such as boron is implanted into the element region A using the gate electrode 8ii4 and the sidewalls 15 to 16 as masks. Then, when the implanted impurity is thermally diffused, a high concentration impurity region 7.7 as shown in FIG. 2(e) is formed, and this high concentration impurity region 7 and the previously formed low concentration impurity The region 5 constitutes a source/drain region 8.8.

Furthermore, the gate electrode 4 and the side wall 15
After forming a silicon oxide film of a predetermined thickness on the surface of the element region A including the areas A to 16 by CVD or the like, contact holes 10, 10 are formed by selectively removing this silicon oxide film by photolithography. Form. Thereafter, a conductive film made of aluminum or the like having a predetermined thickness is deposited on the silicon oxide film 9 by sputtering or the like, and this conductive film is selectively removed by photolithography to form the contact hole 10. , 10, wirings 111i1111 are formed to be electrically connected to the source/drain regions 8.8, respectively. As a result, a semiconductor device having the configuration shown in the cross-sectional view of FIG. 1 is obtained. Note that on this wiring layer 11.11, a second wiring layer, a third wiring layer, etc. are formed as necessary.

By the way, in the above explanation, silicon base #Ii,
1 is of N type, and the source/drain region 8.8 consisting of a low concentration impurity region 5.5 and a high concentration impurity region 7.7 is of P type.
Needless to say, the present invention is applicable only to semiconductor devices having MO3 type transistors; for example, CMO3 type source/drain regions may be formed. The present invention can also be applied to semiconductor devices having O5 type or Bi-CMO5 type O5 transistors.

〔Effect of the invention〕

As explained above, according to the present invention, a sidewall made of the remaining portion of the first insulator is formed along the sidewall of the gate electrode, and the implanted low concentration impurity is heated using this sidewall as a mask. Since a low concentration impurity region is formed by diffusion, the effective gate length can be increased and a sufficient breakdown voltage can be maintained. This reduces the generation of hot carriers and relaxes the electric field in the drain region, thereby suppressing deterioration of the semiconductor device and improving reliability.

In addition, since it is possible to form the source/drain regions with the optimal concentration distribution, the gate lengths of the PMO3 type and NMO5 type O5 transistors when configuring the CMO3 type O3 transistor can be made equal, which improves their performance. As a result, it becomes easy to form both in the best condition at the same time, and as a result, an excellent effect can be obtained in that the performance and miniaturization of the semiconductor device can be improved.

[Brief explanation of the drawing]

1 and 2 (a) to (e) relate to an embodiment of the present invention, and FIG. 1 is a sectional view showing the configuration of a semiconductor device,
FIGS. 2(a) to 2(e) are process cross-sectional views showing the manufacturing method. Further, FIG. 3 is a sectional view showing the structure of a conventional semiconductor device. In the figure, numeral 1 is a silicon substrate (semiconductor substrate), 4 is a gate electrode, 5 is a low concentration impurity region, 7 is a high concentration impurity region, 15 is a side wall (remaining part of the first insulator),
16 is a side wall (remaining portion of the second insulator), and A is an element region.

Claims (2)

[Claims] (1) A gate electrode formed on the surface of an element region of a semiconductor substrate, a low concentration impurity region formed inside the element region along the sidewall of the gate electrode, and a region formed around the low concentration impurity region. a remaining portion of the first insulator remaining along the sidewall of the gate electrode and covering the low concentration impurity region; a remaining portion of the first insulator remaining around the remaining portion of the first insulator; and a remaining portion of a second insulator covering a portion of the high concentration impurity region. (2) forming a gate electrode on the surface of the element region of the semiconductor substrate; completely covering the surface of the element region including the gate electrode with a first insulator; Etching to leave only a portion along the sidewalls of the gate electrode, and implanting a low concentration impurity into the element region using the gate electrode and the remaining portion of the first insulator as a mask, and then thermally diffusing the impurity. a step of completely covering the surface of the element region including the gate electrode and a remaining portion of the first insulator with a second insulator; and etching the second insulator to remove the first insulator. A process of leaving only the peripheral portion of the remaining portion of the gate electrode and the remaining portions of the first insulator and the second insulator as masks, implanting a high concentration impurity into the element region, and then thermally diffusing the impurity. A method for manufacturing a semiconductor device, comprising the step of: