JPH03152967A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH03152967A JPH03152967A JP29274489A JP29274489A JPH03152967A JP H03152967 A JPH03152967 A JP H03152967A JP 29274489 A JP29274489 A JP 29274489A JP 29274489 A JP29274489 A JP 29274489A JP H03152967 A JPH03152967 A JP H03152967A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- integrated circuit
- chip
- circuit device
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 abstract description 3
- 229910000679 solder Inorganic materials 0.000 abstract description 2
- 238000007789 sealing Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Combinations Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は混成集積回路装置に関し、特にICチップの高
密度実装構造を有する混成集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit device, and particularly to a hybrid integrated circuit device having a high-density mounting structure of IC chips.
第4図は従来の混成集積回路装置の一例の縦断面図であ
る。FIG. 4 is a longitudinal sectional view of an example of a conventional hybrid integrated circuit device.
従来の混成集積回路装置は、第4図に示すように、IC
チップ1を配線基板2にダイボンディングし、そのIC
チップ1上に形成しである電極パッド5と配線基板2の
配線4とをボンディングワイヤ8で電気的に接続してい
た。A conventional hybrid integrated circuit device, as shown in FIG.
Chip 1 is die-bonded to wiring board 2, and the IC
Electrode pads 5 formed on chip 1 and wiring 4 of wiring board 2 were electrically connected by bonding wires 8.
上述した従来の混成集積回路装置は、ICチップ上の電
極パッドと、配線基板上のポンディングパッドとの一対
の接続を他の対とは別個に1回のワイヤボンディングと
して行うため、接続の数だけワイヤボンディングを行わ
なければならず、接続の数に比例して、ワイヤボンディ
ングに要する時間が長くなる。このため、接続数の多い
ICチップや多数のICチップを用いた混成集積回路装
置を製造する際、時間が多くかかるという欠点がある。In the above-mentioned conventional hybrid integrated circuit device, the number of connections is small because the connection between the electrode pad on the IC chip and the bonding pad on the wiring board is performed in one wire bonding process separately from other pairs. wire bonding must be performed, and the time required for wire bonding increases in proportion to the number of connections. For this reason, there is a drawback that it takes a lot of time when manufacturing an IC chip with a large number of connections or a hybrid integrated circuit device using a large number of IC chips.
又、ワイヤボンディングを用いているため立体的な実装
構造をとることが困難であり、立体的な実装構造にして
混成集積回路装置を作ったとしても厚さの厚いものにな
ってしまっていた。Furthermore, since wire bonding is used, it is difficult to create a three-dimensional mounting structure, and even if a hybrid integrated circuit device is made with a three-dimensional mounting structure, it will be thick.
本発明の目的は、薄い立体的実装構造を短時間で実現す
ることができる混成集積回路装置を提供することにある
。An object of the present invention is to provide a hybrid integrated circuit device that can realize a thin three-dimensional mounting structure in a short time.
本発明の混成集積回路装置は、配線基板の少くとも一部
と該配線基板に搭載されたICチップとを同時に覆う配
線板が導体バンプを介して前記配線基板と前記ICチッ
プに電気的に接続されていることを特徴とする
〔実施例〕
以下、本発明の実施例について図面を参照して説明する
。In the hybrid integrated circuit device of the present invention, a wiring board that simultaneously covers at least a part of a wiring board and an IC chip mounted on the wiring board is electrically connected to the wiring board and the IC chip via conductor bumps. [Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第1図は本発明の第1の実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of a first embodiment of the invention.
第1の実施例は、第1図に示すように、配線基板2に凹
部を設け、ICチップ1の上面と、配線基板2の凹部の
上面の高さが同一になるように配線基板2を形成し、そ
の凹部にICチップ1を搭載する。In the first embodiment, as shown in FIG. 1, a recess is provided in the wiring board 2, and the wiring board 2 is placed so that the top surface of the IC chip 1 and the top surface of the recess of the wiring board 2 are at the same height. The IC chip 1 is mounted in the recess.
このICチップ1を搭載した配線基板2の上面より、平
らな板の上に回路が形成された配線板3を、互いの配線
4又は電極パッド5が向い合うように合わせ、各接合部
の上面又は下面に形成された導体バンプ6を介してひと
つ又は複数のICチップ1と配線基板2を同時に覆うよ
うに接続する。From the top surface of the wiring board 2 on which this IC chip 1 is mounted, the wiring board 3, which has a circuit formed on a flat board, is aligned so that the wiring 4 or electrode pad 5 faces each other, and the top surface of each joint is Alternatively, one or more IC chips 1 and the wiring board 2 are connected so as to be covered at the same time via the conductor bumps 6 formed on the lower surface.
これらの接合は、例えば導体バンプ6としてはんだバン
プを用い、これを加熱溶融させることにより一括して接
続をすることができる。These connections can be made all at once by using, for example, solder bumps as the conductor bumps 6 and heating and melting them.
第2図は本発明の第2の実施例の縦断面図である。FIG. 2 is a longitudinal sectional view of a second embodiment of the invention.
第2の実施例は第2図に示すように、ICチップ1は、
配線基板12の上にダイボンディングされ、内部に配線
4の形成された四部を有するケース状の配線板13で覆
われ、配線板13とICチップ1.配線基板12とは導
体バンプ6を介して電気的に接続される。In the second embodiment, as shown in FIG.
The wiring board 12 is die-bonded onto the wiring board 12 and covered with a case-shaped wiring board 13 having four parts with wiring 4 formed therein, and the wiring board 13 and the IC chips 1. It is electrically connected to the wiring board 12 via conductor bumps 6.
配線基板12とケース状の配線板13の外周の間には封
止用樹脂7が流し込まれ、内部は密封される。A sealing resin 7 is poured between the wiring board 12 and the outer periphery of the case-like wiring board 13 to seal the inside.
このため、この実施例では、通常の平板の配線基板12
を用いることができ、−括の電気的接続、かつ、封止が
できる利点がある。Therefore, in this embodiment, the ordinary flat wiring board 12
It has the advantage that it can be used for electrical connection and sealing.
第3図は本発明の第3の実施例の縦断面図である。FIG. 3 is a longitudinal sectional view of a third embodiment of the invention.
第3の実施例は、第3図に示すように、部分的な構造は
第1の実施例と同じであるが、配線基板2の両面に配線
を施し、この配線基板2が第1の実施例における配線板
3の役目を兼ねられるようにし、第1の実施例と同様の
接続方法によりもう1つの配線基板22と接合し、多層
化される。As shown in FIG. 3, the third embodiment has the same partial structure as the first embodiment, but wiring is provided on both sides of the wiring board 2, and this wiring board 2 is similar to the first embodiment. It can also serve as the wiring board 3 in the example, and is bonded to another wiring board 22 using the same connection method as in the first example to form a multilayer structure.
このため、この実施例では、ICチップ1を立体配置し
た混成集積回路を容易に、又、薄く形成することができ
る。Therefore, in this embodiment, a hybrid integrated circuit in which the IC chips 1 are arranged three-dimensionally can be formed easily and thinly.
つまり、ボンディングワイヤを用いた接続では、ボンデ
ィングワイヤのループ高さ、又、ボンディングワイヤが
他の部分に触れないための余分な高さが必要であり、こ
れらの合計は0.5mm以上になるが、この実施例の構
造をとるとバンプ接続のため高さは0.1.mm以下と
なり、−層につき差し引き0.4mm以上厚さが薄く形
成でき、又、ボンディングワイヤの倒れによる電気的短
絡等のボンディングワイヤに起因する不良なしに構造で
きる。In other words, in connection using bonding wire, the loop height of the bonding wire and an extra height to prevent the bonding wire from touching other parts are required, and the total of these is 0.5 mm or more. , if the structure of this embodiment is adopted, the height is 0.1. mm or less, the thickness can be made thinner by 0.4 mm or more per layer, and the structure can be constructed without defects caused by the bonding wires such as electrical short circuits due to the falling of the bonding wires.
以上説明したように本発明は、ICチップと配線基板の
少くとも一部を同時に覆う配線板を用い、導体バンプに
より各部分の接合を行うことによって、複数のICチッ
プにわたる多数の電気的接続を一括して行うことができ
る効果がある。As explained above, the present invention uses a wiring board that covers at least part of an IC chip and a wiring board at the same time, and connects each part with conductor bumps, thereby making a large number of electrical connections across multiple IC chips. There is an effect that can be done all at once.
又、この構造を積層することにより、容易に、かつ、薄
<ICチップの立体実装構造を実現することができる効
果が有り、結果的に配線基板が多層化されるため、さら
に、高密度な混成集積回路装置がつくれる効果が有る。In addition, by stacking this structure, it is possible to easily realize a three-dimensional mounting structure for thin and thin IC chips, and as a result, the wiring board becomes multilayered, which further increases the density. This has the effect of making a hybrid integrated circuit device.
第1図は本発明の第1の実施例の縦断面図、第2図は本
発明の第2の実施例の縦断面図、第3図は本発明の第3
の実施例の縦断面図、第4図は従来の混成集積回路のI
Cチップ搭載部の一例の縦断面図である。
1・・ICチップ、2,12.22・・・配線基板、3
、]3・・・配線板、4・・・配線、5・・・電極パッ
ド、6・・導体ハンプ、7・・封止用樹脂、8・・ボン
ティングワイヤ。FIG. 1 is a longitudinal sectional view of a first embodiment of the present invention, FIG. 2 is a longitudinal sectional view of a second embodiment of the invention, and FIG. 3 is a longitudinal sectional view of a third embodiment of the invention.
FIG. 4 is a vertical cross-sectional view of an embodiment of the conventional hybrid integrated circuit.
FIG. 3 is a longitudinal cross-sectional view of an example of a C chip mounting section. 1...IC chip, 2,12.22...wiring board, 3
,] 3... Wiring board, 4... Wiring, 5... Electrode pad, 6... Conductor hump, 7... Sealing resin, 8... Bonding wire.
Claims (1)
Cチップとを同時に覆う配線板が導体バンプを介して前
記配線基板と前記ICチップに電気的に接続されている
ことを特徴とする混成集積回路装置。At least a part of the wiring board and an I mounted on the wiring board
A hybrid integrated circuit device characterized in that a wiring board that simultaneously covers a C chip is electrically connected to the wiring board and the IC chip via conductor bumps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29274489A JP2737318B2 (en) | 1989-11-09 | 1989-11-09 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29274489A JP2737318B2 (en) | 1989-11-09 | 1989-11-09 | Hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03152967A true JPH03152967A (en) | 1991-06-28 |
| JP2737318B2 JP2737318B2 (en) | 1998-04-08 |
Family
ID=17785770
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29274489A Expired - Fee Related JP2737318B2 (en) | 1989-11-09 | 1989-11-09 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2737318B2 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06334113A (en) * | 1993-05-21 | 1994-12-02 | Sony Corp | Multichip module |
| US5495394A (en) * | 1994-12-19 | 1996-02-27 | At&T Global Information Solutions Company | Three dimensional die packaging in multi-chip modules |
| US5705425A (en) * | 1992-05-28 | 1998-01-06 | Fujitsu Limited | Process for manufacturing semiconductor devices separated by an air-bridge |
| US5821762A (en) * | 1994-02-28 | 1998-10-13 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device, production method therefor, method for testing semiconductor elements, test substrate for the method and method for producing the test substrate |
| DE19549705B4 (en) * | 1994-02-28 | 2008-07-10 | Mitsubishi Denki K.K. | High-density packaging multi-chip semiconductor module - includes signal transmission substrate with wiring layer for transmitting signals and feeder substrate with containers for accommodating semiconductor bare chips which are bonded to wiring layer |
| JP2010097999A (en) * | 2008-10-14 | 2010-04-30 | Fuji Electric Systems Co Ltd | Semiconductor device, and method of manufacturing semiconductor device |
| JP2012212832A (en) * | 2011-03-31 | 2012-11-01 | Kyocer Slc Technologies Corp | Method for manufacturing composite wiring board |
| US9173299B2 (en) | 2010-09-30 | 2015-10-27 | KYOCERA Circuit Solutions, Inc. | Collective printed circuit board |
| WO2020049989A1 (en) * | 2018-09-07 | 2020-03-12 | 株式会社村田製作所 | Module and method for producing module |
-
1989
- 1989-11-09 JP JP29274489A patent/JP2737318B2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5705425A (en) * | 1992-05-28 | 1998-01-06 | Fujitsu Limited | Process for manufacturing semiconductor devices separated by an air-bridge |
| JPH06334113A (en) * | 1993-05-21 | 1994-12-02 | Sony Corp | Multichip module |
| US5821762A (en) * | 1994-02-28 | 1998-10-13 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device, production method therefor, method for testing semiconductor elements, test substrate for the method and method for producing the test substrate |
| DE19549705B4 (en) * | 1994-02-28 | 2008-07-10 | Mitsubishi Denki K.K. | High-density packaging multi-chip semiconductor module - includes signal transmission substrate with wiring layer for transmitting signals and feeder substrate with containers for accommodating semiconductor bare chips which are bonded to wiring layer |
| US5495394A (en) * | 1994-12-19 | 1996-02-27 | At&T Global Information Solutions Company | Three dimensional die packaging in multi-chip modules |
| JP2010097999A (en) * | 2008-10-14 | 2010-04-30 | Fuji Electric Systems Co Ltd | Semiconductor device, and method of manufacturing semiconductor device |
| US9173299B2 (en) | 2010-09-30 | 2015-10-27 | KYOCERA Circuit Solutions, Inc. | Collective printed circuit board |
| JP2012212832A (en) * | 2011-03-31 | 2012-11-01 | Kyocer Slc Technologies Corp | Method for manufacturing composite wiring board |
| WO2020049989A1 (en) * | 2018-09-07 | 2020-03-12 | 株式会社村田製作所 | Module and method for producing module |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2737318B2 (en) | 1998-04-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |