JPH03165146A - 4-phase demodulation circuit - Google Patents

Abstract

PURPOSE:To attain digital filtering with a fast operating speed and low degree by employing a digital multiplier and a digital low pass filter LPF, interposing a D/A converter between a phase detector and a VCO and adopting the operating speed being four times the carrier for the LPF. CONSTITUTION:A 4-phase demodulator QPSK signal is converted into a digital quantity at an A/D converter 31, passes through digital multipliers 27, 28 and digital LPFs 29, 30, is sent to binarizing devices 21, 22 and a phase difference detector 23. Only the component of cosphi is extracted from the LPFs 29, 30. Since the operating speed of the LPFs 29, 30 is four times that of the QPSK carrier, when number of degrees of the filters is selected to be an even number, e.g. 4 degrees, the optimum filter characteristic is obtained. The phase of the carrier at the generating side of the QPSK signal and the phase of the recovered carrier generated from a VCO 24 are compared by a phase difference detector 23 and the signal applying D/A conversion is fed to the VCO and the multiplier to make the difference to be zero thereby applying digital processing. Thus, the operating speed is fast and the filter degree is reduced.

Description

Detailed Description of the Invention "Field of Industrial Application" The present invention relates to a four-phase demodulation circuit for demodulating audio signals in a satellite broadcasting receiver, and in particular to an improvement of a low-pass filter (LPF) after multiplication. It is related to.

"Prior Art" Generally, as shown in Fig. 6, a satellite broadcasting receiver receives radio waves from a broadcasting satellite (1) with a parabolic antenna (2), and converts them into intermediate frequency bands in the IGHz band with a BS converter (3). and sent to the BS tuner (4).

In this BS tuner (4), the desired channel is selected by the channel selection circuit (5), FM demodulated by the FM demodulation circuit (6), and then separated into a video signal and an audio signal by the video-audio separation circuit (7). do. Of these, the original video signal is reproduced by a de-emphasis circuit (8) and an energy diffusion signal removal circuit (9), and is applied to a video input terminal (11) of a television receiver (10).

On the other hand, the audio signal is demodulated by a four-phase demodulation (hereinafter referred to as QPSK) circuit (12) and a PCMtI modulation circuit (13), and then reproduced into the original audio signal by a de-emphasis circuit (14). Then, it is applied to the audio input terminal (15) of the television receiver (10). In this way, satellite broadcasting can be received.

In the satellite broadcasting receiver as described above, the QPSK circuit (
12) was constructed as shown in FIG. 5, and demodulated the audio signal using analog processing. This conventional QPSK circuit (12)
, the QPSK signal is passed through a multiplier (17) (1B),
L P F (19) (20)
) (22) and a phase difference detector (23). The phase difference detector (23) compares the phase of the carrier wave on the generation side of the QPSK signal and the phase difference between the reproduced carrier wave generated from the V CO (24), and adjusts the phase of the V CO (24) so that the difference becomes O.
Add a control signal to The oscillation signal from this V CO (24) is sent to one multiplier (17) through a -90° phase shifter (25
) sent via. It is also sent as is to the other multiplier (18) and multiplied by the input QPSK signal. Then, the phase difference gradually becomes O, and the signal is output from the binarizers (21) and (22) as a reverse rJR signal. Note that (26) is a pit clock regeneration circuit.

As shown in Figure 3, the above QPSK circuit (12) has
In order to detect the phase component of the QPSK signal, a multiplier (17
) or (18) and L P F (19) or (20
) are connected dependently. Here, the QPSK signal is expressed as cos(ωat÷φ), and the recovered carrier wave is cosω
When expressed as at, the multiplication result by the multiplier (17) is +(
cos(2ωct+φ)+cosφ), and the subsequent L
P F (19) or (20) removes the high frequency component and extracts only the cosφ or sinφ component.

``Problem to be solved by the invention'' However, since the conventional QPSK circuit (12) processes all analog signals, there are variations in the circuit parameters, the operation is somewhat unstable, and the V CO (
Since the output from 24) is a sine wave, a 90° phase shifter (
25), there were problems such as an error occurring in the amount of phase shift.

In order to solve the conventional problems, the applicant has proposed a circuit for digitally demodulating QPSX, as shown in FIG.

The difference between this circuit in Figure 4 and the conventional circuit in Figure 5 is that Q
PSK input terminal (16) and digital multiplier (27)
An A/D converter (31) is inserted between (2g), and 1 multiplier (27) (28) and L P F (29)
(30) uses a digital type, and furthermore, a D/A converter (32) is interposed between the phase difference detector (23) and the VCO (24).

QPSK circuit for such digital signal processing (12)
After the QPSK input signal is A/D converted by the A/D converter (31), it is multiplied by the recovered carrier wave by the multipliers (27) (28), and the result is L P F (29) (3
0). These L P F (29) (30)
operates at twice or more the frequency of the QPSK input signal, allowing infinite selection. As mentioned above, the QPSK signal wave is C
o5 (ωat÷φ) (φ changes depending on the transmitted data)
If expressed as
ωCt is generated and multiplied by multipliers (27) and (28). The multiplication results are +(cos(2(11ct+
φ) + cosφ), + (sin(2(13Ct+φ)
-sinφ), which is the spectral characteristic diagram shown in FIG. 3, where Δ indicates the amount of spectrum that has spread due to the change in φ of the QPSK signal wave due to data transmission.
L P F (29) (30) removes high frequency components from this spectrum, and therefore L
The sampling frequency of P F (29) (30) is 2
It is sufficient if it is equal to or greater than (ωC+Δ).

By the way, in the past, it was difficult to make logic circuits with high speed and the power consumption was high, so the operation speed was made as slow as possible, which caused the following problems.

(1) The filter needs to have a high Q characteristic to compensate for the sacrifice of speed.

(2) A digital filter with a high Q characteristic has a high order.

Another object of the present invention is to obtain a digital filter with high operating speed and low order.

"Means for Solving the Problem" The present invention provides two
The outputs of the two LPFs are sent to the VCO via a phase detector, and the signal of this VCO is sent to the demodulation output terminal via a multiplier, an LPF, and a binarizer, respectively. The QPSK input terminal is controlled so that the phase difference between the input carrier wave and the reproduced carrier wave becomes O by sending it to the multiplier via a phase shifter and sending it as it is to the other multiplier. and a multiplier, an A/D converter is interposed between the multiplier and the LPF, and a digital type is used for the multiplier and the LPF, and an A/D converter is interposed between the phase detector and the VCO.
/A converter, and further.

The LPF has an operating speed four times that of the carrier wave.

"Operation" The QPSK signal input to the QPSK input terminal is converted into a digital quantity by an A/D converter, and the signal passes through a digital multiplier and a digital LPF.

The signal is sent to a binarizer and a phase difference detector. Here, the recovered carrier wave is cos ωct and QPSK signal cos ((Ll
ct+φ) is digitally multiplied by a multiplier and becomes +(
cos (ωct+φ)+cosφ), and only the component of cosφ is extracted from the LPF. Since the operating speed of the LPF is four times that of the QPSK carrier wave, optimal filter characteristics can be obtained by setting the filter order to an even number, for example, the fourth order.

The outputs of the two LPFs are sent to a phase difference detector, which detects the phase of the carrier wave on the generation side of the QPSK signal, and
The phase difference of the reproduced carrier wave generated by the VCO is compared, and the D/A converted signal is added to the VCO so that the difference becomes O. That is, since it is difficult for a VCO to operate digitally, it is converted into an analog signal and added. The VCO outputs a rectangular wave, which is essentially a digital signal.

This is applied via a -90° phase shifter and directly to a multiplier for digital processing.

"Example" An embodiment of the present invention will be described below.

Assuming that the operating speed of the logic circuit can be increased as much as possible, in the above example, it is preferable to use one that can remove the 2ωC spectrum most efficiently.
A linear phase filter of R is used, and its frequency characteristic H(
e”) is of even order, H(e”)=Σh(n)
From this formula, ω becomes cos (ω(rr−1))
: π, that is, unconditionally H(e
”) becomes O. Also, in general, those filters have ω:π
After that, the characteristics turn around, so it can be seen that the minimum Q is sufficient under this condition. Therefore, it is optimal to make the operating speed of the filter four times that of the QPSK carrier wave and set the filter order to an even number. An example of this is shown in FIG. 1, where L P F (29) (30
) are delayers (35) (36) (37), multipliers (
38) (39) (40) (41), adder (42)
(43) It is composed of (44). Here, the multipliers (38), (39), (40),
If the multiplication coefficients in (41) are a, b, b, and a, then H(z) = a (z=+l) + b(z-+z
−3)=z −”(a (Z−+÷z ”)÷b <
:z++z+)>H(e””) = e −””(
2a cAs (first two) + 2b cos C thousand)
) = 2e-”” (a cos (+) + b e
os (“¥-))”.

L P F (29) (30) configured in this way
The frequency characteristic of is shown in Fig. 2. Specifically, the carrier frequency is 5.72 MHz, Δ is IMHz (7) QPS
In the case of K signal transmission (transmission symbol rate is also I MHz), although the suppression of high frequency components is more than 40 dB,
The order is only 4th.

"Effects of the Invention" Since the present invention is configured as described above, the operating speed is fast.
Furthermore, high frequency components can be sufficiently removed while lowering the filter order.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the LPF according to the present invention, FIG. 2 is a characteristic diagram of the LPF, FIG. 3 is a spectrum characteristic diagram, and FIG. 4 is a block diagram of a four-phase demodulation circuit for digital processing. FIG. 5 is a block diagram of a four-phase demodulation circuit for analog processing, and FIG. 6 is a block diagram of a general satellite broadcasting receiver. (1)... Broadcasting satellite, (2)... Parabolic antenna, (3)... BS converter, (4)... BS tuner, (5)... Tuning circuit, (6)... ... FM demodulation circuit, (7) ... video-audio separation circuit, (8) ... de-emphasis circuit, (9) ... energy diffusion signal removal circuit, (10) ... television receiver, (11)...
Video input terminal, (12)...4-phase demodulation circuit, (
13)..., (14)... de-emphasis circuit,
(15)...Audio input terminal, (17) (18)...
・Multiplier, (19) (20)...LPF, (21)
(22)... Binarizer, (23)... Phase difference detector, (24)... VCOl (25) -----90'
Phase shifter, (26)... pit clock regeneration circuit, (
27) (28)... Multiplier, (29) (30)...
・LPF, (31)...A/D converter, (32)...
・D/A converter.

Claims (2)

[Claims] (1) The QPSK signal input to the QPSK input terminal is branched into two and sent to the demodulation output terminal via a multiplier, LPF, and binarizer, respectively, and the outputs of the two LPFs are sent via a phase detector. The signal from the VCO is sent to one of the multipliers via a phase shifter, and sent to the other multiplier as it is, so that the phase difference between the input carrier wave and the reproduced carrier wave becomes 0. In the device, an A/D converter is interposed between the QPSK input terminal and the multiplier, the multiplier and the LPF are of digital type, and an A/D converter is provided between the phase detector and the VCO. D/
A four-phase demodulation circuit including an A converter, and further comprising: an LPF having an operating speed four times that of a carrier wave. (2) The four-phase demodulation circuit according to claim (1), wherein the LPF comprises a delay device, a multiplier, and an adder.