JPH0316228A - Field-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the controllability and the uniformity at the time of forming a recess structure by providing different three semiconductor layers on a semiconductor layer on which a gate layer is put and which contains Al as an ingredient, and etching the first layer and the third layer selectively. CONSTITUTION:Different three layers of semiconductor layers 8, 7, and 6 are provided on a semiconductor layer 5 on which a gate electrode 15 is put and which has Al as an ingredient, and a semiconductor layer 7, which has Al an ingredient is introduced as a middle layer. When recess-etching the gate electrode 13 or its vicinity into two stages, dry etching method is used, and the semiconductor layer 8 of the first layer, for the semiconductor layer 7 of the second layer, and further the the semiconductor layer 7 of the second layer, and further the semiconductor layer 6 of the third layer, for the semiconductor layer 5 which is positioned below that and on which the gate electrode is overlaid, are etched selectively. At this time, the semiconductor layers 7 and 5, which contain Al, work as the stopper layers at the time of selectively etching the semiconductor layers 8 and 6 of the first and third layers. Hereby, the uniformity and the process-controllability of each step of the second-stage recess improved rapidly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Political and Business Field] The present invention relates to the structure of a field effect transistor and its manufacturing method.

[Conventional technology]

A method for realizing a two-stage recess structure in a charge effect transistor is described by IEEE, International
Electron Device Meeting Proceedings (19
1988) Pages 172 to 175 (1) f? l
h, 1hl) M. 1988, p
p. 172-175). In this conventional example, since the recess structure is formed by a wet etching method, there are problems in terms of controllability and uniformity of the recess shape after forming. [Problems to be Solved by the Invention] The present invention aims to improve the instability of controllability and uniformity when forming a recess structure, which are the problems of the prior art. Means to solve cam] The above purpose is 't! ! ! In order to achieve this, the author used the following technical means.

1. On the semiconductor layer on which the gate wire is deposited, three different
A large amount of semiconductor scrap is provided, and a semiconductor layer containing a certain amount of Al is introduced into the intermediate layer. 2. A dry etching method is used to perform two-stage recess etching near the gate electrode.

At this time, the first round of semiconductor M is selectively etched with respect to the second scrap semiconductor layer. Furthermore, the third semiconductor chip is selectively etched with respect to the semicircular rib covering the gate electrode located thereon.

[Effect]

1. Among the three layers of semiconductor chips provided on the semiconductor layer on which the gate electrode is deposited, the semiconductor layer containing Al acts as a stopper M when selectively etching the first semiconductor layer. 2. By selectively etching the first and third semiconductor layers, the uniformity of each step of the two-step recess and process controllability are significantly improved.

〔Example〕

Hereinafter, the present invention will be referred to as A Q (j a A s / G a
An example of application to the As system 21)l{G FE '1' will be explained with reference to the pseudo-upper diagram a''8.

As shown in FIG. 1a, G a A s. j On the A board, undoped GaAs > M (4000 people) 2, undoped A Qo. sG ao. 7A s Jfi (2
0 people) 3, Si-doped A Q o. aGa 0.7A
S circumference (2 x soil 01 & CII+-8300λ) 4
, undoped A Q o. aO. :l O. 7A
S1 (100 people) b, Si dove (j a A s j
+'l ( 1 ×1017ω''''”/OOA)6,S
i dope A Q o. iISG ao. asA s
kl (2
Si dove GaAsA'# (2X top 0"cm-'100
0 people) Let 8 grow to a certain length. ttb epitaxial analysis is performed with MBEi.

Customer 5, as shown in Fig. 1b, ho 1 - lithography?
A source electrode 10 and a drain electrode 9 are formed using a process and a vacuum evaporation method. The electrodes were made of Au (1000)/Ni (IOOA)/AuGe (5000A).
) and conduct alloying at 400°C for 1 minute.

Next, as shown in FIG.
i! It is provided between the pole 10 and the drain electrode 9. Subsequently, the Si-doped GaAs scrap 8 is selectively etched through the opening. A dry etching method was used for nuclear etching, and the etching gas included C C Q z F2 and He.
Use a mixture of gases.

Next, as shown in Fig. 1d, Si-doped GaAs
A window of the photoresist 12 is provided in the portion where the photoresist 18 has been removed, closer to the source electrode 10 side. Subsequently, the photoresist 1
Si-doped AQO. l5G ao. A portion of the asAs layer 7 and the Si-doped Cia As swt 6 are etched.

For etching, a mixed solution of 200,000 mm, Oa: H:0: H20 is used. Remaining Si-doped Ga As %
6 selectively. A dry etching method is used for this etching.

Next, as shown in FIG.
After injecting Al (5000 pieces) through the window, it is lifted off to form Ga+-mt+44t3.

By the above method, an offset gate and a two-stage recess structure can be formed. The recess depth of the second stage is always G a A
s l'l 6 and A Q o. taGao. aa
As i'J'! Since it becomes incalculable as the sum of the 1 ri,
Table 1r11 The influence of the potential can be eliminated without being too small and with extremely good uniformity even on large-diameter wafers E. Therefore, 21JEG? Since deterioration of the mutual conductance is suppressed even when the claw gate bias is applied at E'l', the output gain during large signal operation is improved by about 20%.

By the way, as mentioned above, in order to eliminate the influence of the surface potential in just the right amount, G a A s ) pi 6 and A Q o. xsG ao. s+sA s Ml'
It is assumed that the sum of the thicknesses of / is set to a thickness that is approximately calculated based on the spread of 1°lI of the depletion due to Table +1TI potential. Actually, A Q o*xsG a
Q. Since lI3A s k4'7 is desirably thin, it is approximately ignored, and the thickness t of G a A s l'J 6 is set by the following formula.

Here, ε is the concentration of the GaAs layer 6, N is the concentration,
q is the cable vfL load. Vs is Table 1m potential (approximately 0.'
/V).

In the above embodiment, the main emission is AffiGaAs/
Although the case where it is applied to the G a As system} I E: M 'i' has been described, the present invention also applies to other 2 1) E G
}−'． ? : 'i' can also be used as Sacheon. As an example 1
n A Q A s / L n G a As 2 L) E: a i-' b: T or A Q G
a As / . L n Ga As system 2 1
) M G Fh: 'L' is mentioned.

〔Effect of the invention〕

According to the present invention, since the two-stage recess structure can be formed with good controllability and uniformity, the following effects can be obtained. ■． Variations in the characteristics of the cables can be reduced, and the characteristics when integrating elements are improved.

2. The main purpose of providing the second step in a two-step recess structure is to eliminate the influence of the surface + hi potential, but by improving etching controllability, the influence of the surface potential can be eliminated without too much. This improves the cord properties.

[Brief explanation of drawings]

Figures 1a-e show that the present invention is based on AlGaAs/GaAs system 2.
υE GF . h: It is a cross-sectional view of the processing process of the cable t part, explaining an example carried out in the manufacture of 'l'. 1...
・G a A s semi-insulating cutting board, 2...Do not dope a a A s k'l, 3... Do not dope A t
lo. sGao. 7As separate, 4-Si Dove 8Q
o. aG ao. vA S X, b-. No dope A Q o. aG a 0.7A S A't, 6
・-S i dope (ja As 71'/, ゛/・
...Si dove A A o. tsG ao. asA
s layer, 8...Si doped (j a As s layer, 9...
・Drain electrode, 10... Source electrode, 11, 12.
...To photoresist 1, step 3...gate electrode.

Claims (1)

[Claims] 1. In a field effect transistor, the semiconductor layer on which the gate electrode is deposited contains Al as a component, and three different semiconductor layers are provided on the semiconductor layer, and A field effect transistor characterized in that, in the vicinity of the gate electrode, one layer and two layers on the surface of the three semiconductor layers are removed to form a two-stage recess structure. 2. The field effect transistor according to claim 1, wherein an intermediate layer between the three different semiconductor layers contains Al as a component. 3. In the method for manufacturing a field effect transistor according to claim 2, the second semiconductor layer on the front surface is used as a stopper layer for dry etching.
selectively etching the layer, then wet etching a portion of the second semiconductor layer and the third semiconductor layer,
A method for manufacturing a field effect transistor, characterized in that the third semiconductor layer is then selectively etched with respect to the semiconductor layer on which the gate electrode is deposited.