JPH03172947A - Microcomputer system - Google Patents

Abstract

PURPOSE: To prevent lock-up by disabling the control of system bus from a peripheral device through a control means when a processor starts a lock instruction sequence. CONSTITUTION: The peripheral device controls a local bus 62 and when a microprocessor 48 starts the lock instruction sequence, a control means 40 defines the preparation completion input line of the microprocessor as false until the peripheral device stops controlling the local bus 62. While the preparation completion input line is defined as false, since the microprocessor 48 handles a system bus 56 as an input bus containing valid data, the system bus 56 is not driven by data. Therefore, the peripheral device can access a cache memory 42 through a transceiver 52 and the system bus 56.

Description

[Detailed Description of the Invention] [Object of the Invention] <Industrial Application Field> The present invention relates to a cache memory, and more specifically, the present invention relates to a cache memory that operates in a copyback φ mode to control a cache memory that operates in a copyback φ mode to improve a microcomputer system. The present invention relates to a cache memory salary controller in a computer.

<Prior Art> Cache memory is a small capacity, high speed auxiliary memory used in computer systems. Using well-known algorithms, the contents of selected memory locations within the computer system's main memory are periodically copied into the cache memory.

The central processing unit reads and writes from cache memory if possible. This reduces cycle time since cache memory is a faster memory than main memory. Additionally, when a remote bus master device, such as a direct memory access (DMA) device, accesses main memory, the processor may store cache memory during the access to main memory by the remote bus master device. run using
In other words, it can continue to operate. This can further facilitate throughput and enhance the performance of the computer system.

Until recently, cache memory was commonly used in mainframe
Used only in computers and minicomputers. Microprocessors used in personal computers or microcomputers were too slow to benefit from cache memory. Intel
el) With the advent of 32-bit microprocessors such as the 80386, microprocessor clock speeds have increased sufficiently that cache memory now allows for significant increases in throughput in microcomputer systems. There is. As a result, cache memory is used in microcomputer systems having high speed microprocessors such as the Intel 80386. Additionally, an Intel 80286 compatible chip with a 25 MHz clock was recently developed. This microprocessor has a sufficiently fast clock speed that it is advantageous to use cache memory as well.

Cache memory generally consists of high speed random access memory (RAM). This is controlled by the cache memory controller, which decides what to write to or read from the cache memory. As previously discussed, cache memory is accessed in place of main memory, if possible, to reduce overall memory access time and thereby increase throughput.

When a processor attempts to write to main memory, the cache controller compares the address of a main memory location with the memory address stored in its tag memory and determines whether the contents of this main memory location are stored in cache memory. Decide whether it is. (The "tag memory" is a RAM memory in which the cache controller stores the address of the main memory storage location most recently stored in the cache memory.) If its contents are stored, the "tag memory" J has occurred. If it has not been stored, a "write error" has occurred.

When the processor is operating in the well-known "write-through" mode, only write hits are written to cache memory, whereas all processor write requests are written to main memory. In contrast, when a cache controller is operating in the well-known "copy-pack" mode, the processor writes only to cache memory in the event of a write hit, and only writes to cache memory in the event of a write hit, except under certain circumstances. Write to main memory if . Updating main memory for write hits is delayed until a read miss occurs which causes old data to be "copy packed" into main memory to make room for new cache data. The cache memory may or may not be updated for write misses according to the cache memory update plan or method being used.

There are two cases in which reversion to a slower write-through mode must occur. The first case is when there is main memory on the expansion bus whose function cannot be inhibited if there is a path snoop hit, which will be described later. In the second case, the memory location to be written to is R for video display.
This is the case with Matsubuto I10 storage locations in memory such as AM.

Writing to main memory by the processor is often performed by "post-write." As explained in more detail below, write-after refers to fixing the address of the addressed main memory memory location in the cache controller and fixing the data in the buffer art bus transceiver. is necessary. The processor can now perform the next bus operation, and the cache controller handles the remaining write operations.

When the processor attempts to read from a main memory location, the cache controller compares the address of the main memory location with its [tag memory J] so that the contents of the addressed memory location are cached. Determine whether it is written to memory. If it has been written, this is called a "read hit." During a read hit, the cache roller disables main memory and causes the cache memory to respond as if it were main memory. In this way, the processor reads the cache memory. A "read miss" occurs if the memory location that the processor attempts to read has not been written to cache memory.

In this case, the processor reads the main memory location, and the contents of this main memory location are also written to a cache memory in a common manner.

The cache controller then updates its tag memory to indicate that this main memory location is currently stored in cache memory.

Until now, cache memories operating in copy-pack mode have been used only in larger computer systems such as mainframe computers and minicomputers. Cache memories used in microprocessors could only be operated in write-through mode.

One such cache memory controller for a microcomputer system based on the Intel 80386 chip or its equivalent is the Intel 82385 cache controller.

Another example of such a cache memory controller is the Auspek 38152.

These two cache controllers have limitations that limit the throughput improvements that can be obtained by using cache memory. (Improvement in throughput refers to the reduction in the time required for the microcomputer Φ system to execute a program by reducing the time required for memory access.The more memory accesses are performed when executing a program, the more ,
Throughput is significantly improved by reducing the time required to access memory. ) These limitations include the inability to operate in copy-pack order mode and with cache sizes up to 32 kilobytes.

The most important limitation is believed to be the inability to operate in copy-pack order mode. While write-through techniques guarantee real-time coherence, ie, that a cache memory is consistent with its corresponding main memory location, it imposes a penalty in the form of system bandwidth.

During read hits in write-through mode, the cache memory provides fast access to the CPU, but also requires a DMA controller (very common in modern PC systems, especially higher performance PC systems). ``free'' cycles are given to the system bus for use by another bus master, such as a very common bus master, increasing system bus bandwidth and system throughput. However, during a write hit in write-through mode, all writes to the cache are written to the main memory at the same time (substantially at the same time for "later" writes), so symmetrical benefits cannot be obtained. This is to prevent the remote mask from reading main memory locations that have been updated in the cache memory but not copied back into main memory.

In the copy-pack instruction mode, processor writes to cache memory are copied to the main memory only on read misses. On a read miss, the cache controller first checks the cache memory location to be written to see if the data from the addressed main memory location is "dirty."

A cache memory location is dirty if it has been updated but its corresponding main memory location has not. If the selected cache memory location is dirty, a cache roller writes the contents of the selected cache memory location to the corresponding main memory location. The cache controller then causes the contents of the addressed main memory location to be written to the selected cache memory location and provided to the processor.

The cache controller also updates its tag RAM to indicate a new main memory location that will correspond to the selected cache memory location.

The copyback mode is particularly useful for DMA operations on the system bus, such as disk accesses, because it frees up important bus bandwidth for other operations. However, Intel 82385 and Auspec Φ compatible chips not only cannot operate in copyback mode, but Intel's datasheet states:
It has been shown that copyback mode is also not available for the 80386 microprocessor.

Intel has announced that in its latest microprocessors, commonly known as Intel 486, the cache controller can operate in copyback mode.
It offered design features not present in microprocessors. In particular, this 486 is
(BOFF) input. If the BOFF input is true during a DMA operation, the 486 abandons the operation it is currently performing and provides the bus for the DMA operation. After the DMA operation is completed, the 486 again performs the bus operation that it was performing at the beginning of the DMA operation. This makes it possible to resolve deadlocks in copyback mode, which were considered unresolvable in devices without a BOFF input.

If a remote bus master attempts to read main memory, such as when DMA is occurring, copyback
A problem arises that does not exist in write-through mode. The problem is that main memory is much less coherent with cache memory when copyback is used than when write-through is used. As a result, when DMA occurs,
The contents of the addressed main memory location are incorrect, i.e. data has been written to the cache memory location corresponding to the addressed main memory location, but the data is is not written.

SUMMARY OF THE INVENTION The present invention relates to the use of a cache controller in a microprocessor system consisting of a microprocessor capable of executing a "lock instruction sequence." A locked instruction sequence is a sequence of instructions that cannot be interrupted during execution. A microprocessor is connected to the first data bus, which in turn is connected to cache memory. The system also has a peripheral device connected to a second data bus connected to the main memory. The system also drives a first data bus with data from the second data bus, and
Transceiver means are provided for driving said second data bus with data from a data bus. That is, the transceiver means allows the peripheral device to access the cache memory and allows the microprocessor to access the main memory.

In such a system, the peripheral device is connected to the second
A lock write instruction in which the microprocessor accesses main memory via the first bus, transceiver means and a second data bus when attempting to access the cache memory via the first bus, transceiver means and a first bus. However, if the processor does not have a backoff pin, the microprocessor system may lock up.

The present invention seeks to solve this problem.

SUMMARY OF THE INVENTION According to one embodiment of the invention, every microprocessor lock instruction sequence begins with a read lock instruction. Control means are provided for determining whether the peripheral device is currently controlling the second data bus. the peripheral device controls the second data bus, and the microprocessor (always starts with a lock read instruction)
When initiating a lock command sequence, the control means causes the microprocessor's ready input line to be false until the peripheral device relinquishes control of the second data bus.

While the ready input line is false, the microprocessor treats the first data bus as an input bus containing valid data and therefore does not attempt to drive the first data bus with data.

This allows the peripheral device to access the cache memory via the transceiver means and the S1 data bus.

If a lock command sequence is being executed when the peripheral device requests control of the second data bus, the control means controls control of the second data bus by the peripheral device during the lock sequence. I will deny it.

By following this protocol, no lockups will occur.

Embodiment A cache memory is configured according to its set associativity. Set associativity determines which locations in main memory can write to which locations in cache memory. This ranges from direct mapping to full set associativity. Direct mapping allows a given main memory location to be written to only one cache memory location, whereas full set associativity allows all main memory locations to be written to any cache memory location. can.

According to its set associativity, the cache memory is divided into one or more banks. Direct Matsubuto cache has only one bank. A cache with 2-way Φ set associativity has two banks, and a cache with 4-way set associativity has 4 banks.

Main memory is divided into sections called pages, which are the same size as the cache banks. For example, as shown in FIG. 1, if the cache memory size is 32, each page will be 32 in the direct Matsubuto configuration. In a cache memory with two-way reset associativity, each page has one-half the size of the cache memory, or 16 for a cache memory of 32, and a four-way reset associativity, as shown in FIG. - In a cache memory with set associativity, each page is one quarter of the size of the cache memory, or 32 to 8 cache memories, as shown in FIG.

Each page in main memory or each bank in the cache consists of several blocks.

Each block has its own tag in the cache controller's tag RAM, also referred to as the cache directory. Therefore, contiguous blocks in the physical space of the cache may become logically non-contiguous. As shown in FIGS. 1-3, the data traverse for each tag includes a tag field, a "dirty" block bit, and a "valid" bit for each subblock within the block. The tag field identifies the associated block address in main memory. The dirty block bit is set or cleared to indicate that any of the subblocks has been updated and is not coherent with the corresponding memory location in main memory. The valid bit is set or cleared to indicate whether the associated sub-block is used or available.

Also as shown in FIGS. 1-3, each block consists of a fixed number of sub-blocks grouped together under a single tag within the cache directory. A subblock is the smallest amount of information exchanged between main memory and cache memory when transferring data from main memory to cache memory or for updates from cache memory to main memory. The size of each subblock changes in proportion to the size of the cache memory. All subblocks of a block are based on sequential memory locations because the block's tag contains the block's base address.

It is important to note the difference between subblocks and words. As described above, a subblock is the smallest unit of information exchange between the cache memory and the main memory. Defines the largest unit of information exchange between a central processing unit (CPU) and either cache memory or main memory. The size of the subblocks is directly proportional to the size of the cache memory, since the total number of blocks in the cache memory and the number of subblocks per block remain constant due to the constant number of tags and valid bits available. Change.

Direct mapping is the simplest type of set associativity. As shown in FIG. 1, the main memory is logically divided into pages of equal size to the cache memory banks. Each cache memory location is indexed by a tag and an offset. The tag identifies a block and the offset identifies a storage location of a subblock within the block. In fact, the tag is an address pointer whose content points to the page in the main memory, on the basis of which the block stored at that location in the cache memory is copied.

Since the tag of each block can contain the address of any page, consecutive blocks of the cache can be randomly selected from any page.

However, in a direct mapping configuration, the memory location of each block of the cache memory must directly map or correspond to its memory location in a page in main memory. Furthermore,
Since the position of a sub-block within a block is determined by its offset, sub-blocks within a block that are copied to the cache memory must likewise correspond between main memory and cache memory.

In operation, the CPU provides the complete address of the main memory location to be accessed in a read or write cycle.

To determine a hit, a tag comparator in the cache controller compares the contents of the tag to higher order address bits that determine the page in main memory. If there is a hit, the cache memory is enabled by the output of the appropriate comparator and the remaining address bits drive the address lines of the cache memory to access the selected memory location.

An n-way set associative mechanism divides the cache memory into n banks, as shown in FIG. 2 for two-way set associativity and FIG. 3 for four-way contention set associativity. In this case, the same offset storage location is available for n pages of main memory, since each of these storage locations belongs to a different cache bank. Direct mapping is essentially one-way set associativity.

FIG. 4 is a block diagram of a microcomputer system based on an Intel 80386 microprocessor and having a cache memory controlled by a conventional Intel 82385 cache controller. Microcomputer system 10 includes a central processing unit (C), which is, for example, an Intel 80386 microprocessor.
PU) has 12. Microcomputer system 10 also has a "local" bus 34 and a "system" bus 32. As is well understood, microcomputer systems have an internal or local bus and an external or system bus.

The local bus consists of address signals, data signals, status signals and control signals at the pin locations of the microprocessor. The system bus is a buffer portion of the local bus and may differ somewhat from the local bus in the way it handles status and control lines and timing.

Microprocessor 12 is connected to cache memory 14 and 32-bit transceiver 1 via local bus 34.
Data port D31 connected to the processor side input of 8
-0. The term "port" is used to refer to something that can optionally function as both an input and an output. The chipset 20 includes a 32-bit working transceiver 18.
The transceiver side data port D31-0 is connected to the chipset side data port D31-0 of the transceiver side data port D31-0.

As anyone familiar with the design of personal computers and workstations will readily understand, a "chipset" is a component that handles interconnected (interrupt) processing, timers/counters/clocks, bus timing, bus management, and memory. Management (memory management)
1 that integrates into a small number of components (approximately 6 or fewer) the elements necessary to perform various peripheral system functions, such as and possibly interfacing with external devices.
Refers to a set of large scale integrated (LSI) components. Such chipsets can be purchased as a set or as individual components. One example of a chipset that can be used in the present invention is a chipset manufactured by Texas Laboratories (T.
There is a TACT 83000 manufactured by Exas Instruments.

The microprocessor 12 also has inputs to a 16-bit buffer 22, a 32-bit buffer 24, and a cache controller 30 via a local bus 34.
It has an address output A31-2 connected to the address port A31-2 of the address port A31-2.

The output of the 16-bit buffer 22 is stored in the cache RAM.
14 address input CA13-0. For example, the cache controller 30 is an Intel 82
385 cash controller. The output of the 32-bit buffer 24 is connected to the address input A31-2 of the chipset 20. microprocessor 12
is further connected to the 8-bit φ latch 2 via the local bus 34.
It has a bus control output 26 connected to 8 inputs. The output of 8-bit latch 28 is connected to the bus control input of chipset 20.

Chipset 20 has a system address output 5A31-0 connected to system address line 5A31-0 of system bus 32. System address line 5
A31-0 is also connected to snoop address input 5A31-0 of cache controller 30. The chipset 20 also has a system data port 5D3 connected to the data line 5D31-0 of the system bus 32.
It has 1-0. Connected to system bus 32 are remote command bus mask devices such as DMA device 36 and main memory 38 . The cache controller 30 further includes a control input OE/ of the cache memory 14.
It has a cache memory control output OE/WE/C3 connected to WE/C8. (The representation of the input and output of the cache controller 30 is based on Intel 82385
Can be found in datasheets regarding cash controllers. ) In operation, cache controller 30 must respond appropriately to three types of memory accesses: processor reads, processor writes, and remote busmask writes.

The remote master device that accesses main memory is often an MA device, such as a disk controller, and such accesses can be expressed in the form of DMA reads and writes.

When writing to a processor, data is always written to the Intel 82
385 is written to main memory 38 when cache controller 30 operates only in write-through mode. When a processor write occurs, cache controller 30 compares the main memory address presented by processor 12 on address line A 31-2 of local bus 34 with the main memory location stored in its tag RAM to identify the write hit. determine whether something is happening. In that case, the data is similarly written to the appropriate storage location within cache memory 14.

During a processor read, the cache controller similarly compares the address of the main memory location from which data is to be read with its tag RAM to determine if a read hit has occurred.

If so, cache controller 30 causes the read to occur from cache memory 14 rather than from main memory 38 . In the event of a read miss, the read is performed from main memory 38 and the contents of the addressed main memory location are similarly copied to the appropriate location within cache memory 14.

Because cache controller 30 operates only in write-through mode, cache memory 14 is always coherent with main memory 38. As a result, in the event of a read miss, the contents of the addressed main memory location are stored in the appropriate memory location of the cache memory 14 in the main memory location to which this cache memory 14 memory location corresponds. It is possible to write data without worrying that the data is more recent than the current data, ie, that it is not coherent with the corresponding main memory.

In write-through Φ mode, DMA reads and writes are performed directly to or from main memory. During a DMA read, the contents of the addressed main memory location are read. Cache memory 14 remains unaffected and processor 12 can continue to operate with cache memory 14 until a read miss or two processor writes occur.

During a DMA write, the write is also performed directly to main memory. Data is not written to cache memory. As a result, controller 30 determines that the addressed main memory memory location is also cache RAM.
16 to determine whether the DM
A writing must be monitored. This is the so-called snooping. If the addressed main memory memory location was also stored in the cache memory 14, this cache memory 14 memory location is no longer the corresponding main memory memory location. It will not have coherence with the memory location. Controller 30 determines this and clears the "valid" bit of the tag RAM associated with this cache memory 14 location. This can be written such that the contents of this cache memory location are no longer available for reading and an attempt to read the main memory location corresponding to this cache memory 14 location results in a read miss. It shows that it is possible. The "snubbing" method described above is used by the Intel 82385. In another embodiment, the processor can be held for an entire DMA cycle, and DAM writes can be written to cache memory on write hits as well. However, this method further reduces the throughput improvement achievable by using cache memory.

FIG. 5 shows a microcomputer having a cache memory or cache RAM 42 controlled by a cache controller 44 constructed in accordance with the present invention.
System 40 is shown in a simplified block diagram. The microcomputer system 40 also includes a CP, which is an Intel 80386 microprocessor, for example.
It has a U48, a chipset 50, and a 32-bit transceiver 52. The fact that the Intel 80386 was cited as an example of the CPU 48 makes the present invention applicable to the Intel 8038.
It is clear that the present invention is not limited to a particular microprocessor such as 6. Microcomputer system 40 has a processor or local bus 62 and a system bus 56. The local bus 62 connects the cache controller 44 and the 32-bit Φ transceiver 5.
2 is provided on the way and is driven to the chipset 50 as an extended local bus 58. That is, the cache controller 44 is interposed between the CPU 48 and the system bus 56. Cache controller 44 is CPU
48 and system bus 56, and propagates them appropriately. Data passes outside of cache controller 44 into 32-bit transceiver 52 and is driven into or out of cache RAM 42 as appropriate.

The CPU 48 receives the CPU side address input A31 of each cache controller 44 via the local bus 62.
-2 and control/status input C/S. The microprocessor 48 is
It further has a data port D31-0 connected to the data port D31-0 of the cache memory 42 and the CPU side data port D31-0 of the 32-bit transceiver 52 via the local bus 62. The chipset 50 is
Address port A31- connected to chipset side address port A31-0 of cache controller 44
0, and a data port D31-0 connected to the chipset side data port of the 32-bit transceiver 52.

The chipset 50 also has a data port 5D31-0 and an address port 5A3 connected to the system bus 56.
1-0. The main memory 60 is connected to the DMA device 4
6, it is connected to the system bus 56.

The cache controller 44 is a cache memory 42
has a cache memory address output CA13-0 connected to a cache memory φ address input CA13-0 of the memory address input CA13-0. Cache controller 44 also has cache memory control outputs OE/WE/C8 connected to control inputs OE/WE/C5 of cache memory 42, respectively. Additionally, cache controller 44 has a control port 80 connected to control port 81 of chipset 50 and a control output 82 connected to a control input 83 of 32-bit transceiver 52. The chipset has a control output connected to the system bus.

FIG. 6 shows a cache controller 4 for a design consisting of
4 is a block diagram detailing the hardware interfaces for various control inputs and outputs to CPU 48, chipset 50, and 32-bit transceiver 52 of PCB 4. The mnemonic codes used to identify each input and output of the device of FIG. 6 are listed in the attached Table A.

The mnemonic codes of Table A not listed in FIG. 6' can be used for pins of cache controller 44 when used with other types of CPUs and in other configurations. Here,
The "#" after the mnemonic code indicates that the input, output, or signal is true at a low logic level.

Cache controller 44 supports direct mapping, two-way set associativity, and four-way set associativity. As described in Table A, the cache controller 44 has 4WAY input and 2W/
D# input.

If the 4WAY input is high, 4way set associativity is selected. When the 4WAY input is low, the 2W/D# input controls set associativity, and when it is high, it selects 2-way set associativity, and when it is low, it selects direct mapping.

In addition, the cache controller 44 is changed to 32 to 164,
Supports cache memory sizes up to 128K and 256K. Cache controller 44 has an input MO-1 that selects the size of cache memory 42 that cache controller 44 controls as shown in Table A.

Cache controller 44 must ensure coherency between main memory 60 and cache memory 42. Its WTM as listed in Table A
It does so by either write-through mode or copy pack mode depending on the state of the WTO (write-through mode) and the WTO (write-through only). In the write-through only mode, the cache controller 44 operates in the same manner as the conventional Intel 82385 cache controller, so a detailed description of the write-through only mode will be omitted.

In the copy pack mode, data from the CPU 48 is written only to the main memory 60 when there is a write miss by the processor, and only to the cache memory 42 when there is a write hit by the processor. The cache controller 44 controls the cache memory 4 at the time of a read miss and when the selected cache memory 4
A CPU 48 update of cache memory 42 is written to main memory 60 only if the storage location of No. 2 is not coherent with the corresponding main memory storage location at that time. As a result, the cache controller 44
The contents of the cache memory location to be replaced are
These cache memory locations must be updated to their corresponding locations in main memory 60 before being overridden with new data. To do this, the "dirty j" bit of the tag for each block indicates whether the block has a memory location that has been updated by CPU 48 but not copied to main memory 60.

Writes to cache memory 42 locations performed by CPU 48 do not simultaneously update the corresponding main memory locations. Instead, the appropriate "dirty" bit is set for the block containing this byte.

If a writing error occurs during writing by the CPU 48,
Cache controller 44 disables write enable signal WE to cache RAM 42 and locks the data and address from CPU 48 into 32-bit transceiver 52 and its internal address latches, respectively, as post-write. This frees up the local bus 62,
This allows the CPU 48 to execute the next cycle without waiting for the completion of the write. Local bus 62 is also available to cache controller 44 so that it can serve snoop hits from remote busmask devices as described below. After a second consecutive write miss, the CPU 48 will hold the PRE until the previous write to main memory 60 is complete, since the latch can only sustain one post-write.
Assuming that ADY# is false, it must be made to wait.

If a reading error occurs when reading the CPU 48,
The cache controller 44 first
Make Y# signal false. If direct mapping is not used, the cache controllers may be two (for two-way set associativity) or four (for two-way set associativity).
4-way set associativity), examine its LRU bit (FIG. 7) and select from main memory 60 the block to be updated. If the dirty bit of the tag RAM memory location for the selected block is set, cache controller 44 uses the selected block to determine which sub-blocks should be copied to main memory 60. Check the valid bit of the tag RAM memory location for the sub-block. Cache controller 44 copies to main memory 60 a sub-block that is indicated as valid, ie, has its valid bit set, and then clears all valid bits for the sub-block within said selected block; Clear dirty bits for selected blocks.

At this stage, cache controller 44 controls 32-bit transceiver 52 to drive data from the subblocks marked valid onto extended local bus 58. Cache controller 44 also monitors the EREADY# signal from chipset 50 and initiates successive subblock copy-pack cycles until all valid subblocks of the dirty block have been written to main memory 60.

The cache controller 44 then receives the read cycle command address and control signals from the extended local bus 5.
8, the read request from the CPU 48 is sent to the main memory 60 and the cache memory 42
The content is read from a memory location in main memory 60 (referred to as a ``replacement subblock'') to be written to the appropriate subblock of the selected block. Cache controller 44 extends the EREADY# signal to the extended local for the appropriate bus cycle so that CPU 48 can read the appropriate word in the replacement subblock or addressed main memory 60 memory location. from bus 58 to local bus 2.

Cache controller 44 also sets the valid bit for the just-updated sub-block in cache memory 42 in its appropriate tag RAM storage location. Cache controller 44 must also ensure that memory accesses by remote bus mask devices remain coherent.

For example, a remote bus mask device may attempt to read a main memory location that has been updated in cache memory 42 but not transferred to main memory 60. Also, the lack of coherence means that
Even though the cache controller 44 is not a bus master,
The result is that the remote busmask device writes to main memory 60. In this case, if the addressed main memory location to be written is currently being copied into the cache memory 42, then the data in the cache memory 42 corresponding to the addressed main memory location is becomes old.

To maintain coherency, cache controller 44 monitors system bus 56 via chipset 50 for EHOLD signals or requests from remote bus masters to monitor reads resulting from reads and writes by remote bus mask devices. Snob hits and write hits. If cache controller 44 has not received a lock signal from CPU 48, described below, it generates an EHLDA acknowledge signal to the remote bus master and begins snooping, as described below.

In snooping for reads, cache controller 44 examines the main memory read cycle address and determines which main memory stores are stored in cache memory 40 in the block that has its corresponding set of "dirty" bits. Determine if the remote bus mask device is attempting to read data from the location. When snooping for a write hit, the cache controller 44 checks the address of the main memory location based on the address pointed to by the remote busmask device and determines the address of the addressed main memory location. is stored in cache memory 42. If so, a snoop write hit occurs.

In the event of a snob read hit, cache controller 44 drives the appropriate data from cache memory 42, disables main memory output to system bus 56 as the memory disable (MEMD IS) signal is true, and It drives the output of cache memory 42 through a 32-bit transceiver 52. This data is stored until EREADYI # on expansion local bus 58 is true, indicating the end of the current read cycle.
It is maintained in an enabled state in the chipset 50. That is, any remote bus mask device, such as DMA device 46, will receive the correct data as if the data were in main memory 60.

If a snoop write hit occurs while cache controller 44 is in copyback mode, the affected subblock has been updated by CPU 48 but has not been copied back to the corresponding main memory 60 location. Contains data. This is detected if the "dirty" bit of the block to which the affected sub-block belongs is set. Cache controller 44 then updates the affected sub-blocks by executing writes to cache memory 42 at the same time as writes are executed in main memory 60 .

Because the CPU 48 operates asynchronously with a remote bus mask device connected to the system bus 56, snoop hits occur while the processor is performing read/write operations on the local bus 62 outside of the cache memory 42. there is a possibility. If a snoop hit occurs while CPU 48 is performing a read, cache controller 44 asserts that the READYO# line on local bus 62 connected to the READY# input to CPU 48 is false and sends a message to cache memory 42. until the remote bus mask device access is completed.
Stops the CPU from reading for an additional cycle. In snoop read hit, cache memory 44
In a snoop write hit, the remote data is written into cache memory 42 in one cycle, while the data from the remote is read and sent through 32-bit transceiver 52. This allows CPU4
The time penalty for 8 is minimal.

If a snoop hit occurs during a write operation or idle time of the CPU 48, the cache controller 44 sets the HOLD line on the local bus 62 true and the CPU
Assert the HOLD input of U48 as true. The CPU 48 is
Write by writing to cache memory 42 or by pinning the address to the internal address latches of cache controller 44 (FIG. 7) and pinning the data to 32-bit transceiver 52 for later writes to be performed at a later time. The operation continues until the process is completed. After CPU 48 completes the write operation, it is maintained by its HOLD input being true and asserts hold confirmation signal HLDA to cache controller 44.

The remote bus master then immediately accesses cache memory 42 and proceeds to read or write to it. At this time, data from the CPU 48 is fixed in the 32-bit transceiver 52, and the cache controller 44 instructs data transmission between the cache memory 42 and the chipset 50.
It passes through a bypass, which is understood to be part of a two-bit transceiver 52. In this case, the data from the charash snoop read hit is stored in the latch for later writes, since the latch already contains data.
cannot be fixed. The processor in this case must be maintained until the end of the DMA operation. D
EHL after EHOLD from MA device becomes false
DA goes false, the processor's HOLD is released, and a post-write is initiated if necessary.

Microprocessors such as the Intel 80386 have so-called "lock sequences" of bus operations that can lead to deadlocks in systems with cache memory. When performing a lock sequence of bus operations,
The microprocessor refuses to relinquish control of the local bus until it completes a lock sequence of bus operations. The deadlock occurs when a snoop hit occurs while the CPU 48 is writing as part of a lock sequence of bus operations.

Because CPU 48 is executing a lock sequence of bus operations, it is unaware that its HOLD input is being asserted true by cache controller 44 and, as a result, does not hold until the write is complete. Therefore, cache controller 44 cannot control controller bus 62 and is therefore useless for snoop hits.

Cache controller 44 monitors CPU 48 for read operations when cache controller 44 is not masking system bus 56, since the lock sequence of bus operations always begins with a read.
Resolve this deadlock. Cache controller 44 responds to the EHOLD request with its EHLDA output true if system bus 56 is not masked;
Indicates relinquishing control to a remote bus mask device on system bus 56. A snob hit occurs only when cache controller 44 gives an EHLDA confirmation and relinquishes control of system bus 56. As a result, if the cache controller 44 determines EHLDA to be true and detects a lock read operation by the CPU 48, the cache controller 44 sends the READY# input to the CPU 48, and the DMA device 46
The signal D remains false until control of the system bus 56 is relinquished by making it false.

Since CPU 48 waits until its READY# input is no longer false before completing a read operation, this frees up local bus 62 for use by cache controller 44 to contribute snoop hits. In another embodiment, cache controller 44 does not provide EHLDA and CPU 48
If it is detected that the OCK# output is true, the cache controller 44 outputs the LOC of the CPU 48.
By refusing to provide EHLDA until the K# output goes false, it effectively disables or disables itself. Since the cache controller 44 serves as a mask for the system bus 56, no memory accesses by remote bus mask devices occur.

In direct mapping mode, cache controller 44 responds to main memory accesses by CPU 48 as follows. The tag RAM of cache controller 44 has a tag for each block within cache memory 42 . The tag includes a tag field identifying the address of the associated block in main memory, and any subblock within the block that has been updated and its corresponding main memory storage location, as described above. A dirty block bit that is set or cleared to indicate whether it has no coherency and a dirty block bit that is set or cleared to indicate that the associated subblock is used or can be used. A valid bit for each sub-block. (Table B
summarizes subblock, block, bank, and page sizes and/or counts for various cache sizes and selected mappings supported by cache controller 44. ) Cache controller 44 decodes the A31-2 address line from local bus 62 into three fields. (i) a 17-bit tag field to determine which of the 217 (128K) pages was being accessed; (it) a 10-bit tag field to select one of the 104 blocks of cache memory 42;
a block address of bits, and (i i i) three additional bits to select any of the eight sub-blocks in the selected block. Cache controller 44 then compares the 17-bit tag field with the 17-bit tag field of the tag stored in its tag RAM to determine whether a cache hit, read or write hit, has occurred. .

In the case of a cash hit, cache controller 44 drives cache memory 42 with the remaining 13 address lines to write data to or read data from cache memory 42, as the case may be.

In the two-way set associativity contention mode, cache memory 42 is divided into two equally sized bangs. Each page in main memory is the same size as the bank of cache memory 42. A tag in the tag RAM is associated with each block in each cache bank. To illustrate, each tag field has a width of 18 bits that identifies 218 (256K) pages. The structure of the tag stored in the tag RAM changes accordingly. The number of pages is doubled compared to direct mapping since the page/bank size is reduced by half. The single dirty bit for each block and the 8 valid bits for the 8 subblocks remain unchanged.

When CPU 48 is addressing memory and cache controller 44 is in two-way set associativity mode, cache controller 44 decodes the A31-2 address line from local bus 62 into three fields.

(i) an 18-bit tag field that determines which of the 218 pages was being accessed;
) a 9-bit block address that selects one of the 512 blocks in the cache bank; and (ii) a 9-bit block address that selects one of the 8 sub-blocks within the selected block. There are two additional bits. In this case, the cache controller 44 has 18
The tag field of bits is compared to the tag's 18-bit tag field stored in tag RAM to determine if a cash hit has occurred.

In the case of a cash hit, cache controller 44 drives cache memory 42 with the remaining 12 address lines to
2 or read data from the cache memory 42.

In the 4-way set associativity Φ mode, cache memory 42 is divided into four equally sized banks. Each page of main memory has the same size as each bank of cache memory 42. Tag R
A tag in the AM is associated with each block of each cache bank. To illustrate, each tag has a width of 19 bits that identifies 214 (512K) pages. Similarly, tag R
The structure of the tags stored in the AM must change accordingly. The number of pages is four times as large compared to direct mapping since the page/bank size is reduced by a factor of four. One dirty bit for each block and valid bits for the eight sub-blocks remain unchanged.

The CPU 48 addresses the memory, and the cache controller 44 performs four-way set associativity.
When in mode, cache controller 44 decodes the A31-2 address line from local bus 62 into three fields. (i) a 19-bit tag field that determines which of the 219 pages was being accessed; (ii) an 8-bit block address that selects any of the 256 blocks in the cache bank; i i i) 3 additional bits to select any of the 8 sub-blocks within the selected block. In this case, the cache controller 44 sets the 19-bit tag field to the tag RA.
The 19-bit tag field of the tag stored in M is compared to determine whether a cash hit has occurred. In the case of a cash hit, the cache controller 44 stores the remaining 11 cache memories 42.
address lines to write data to or read data from the cache memory 42, as the case may be.

Figure 7 shows the microcomputer system 4 in Figure 5.
2 is a block diagram of a cache controller 44 of No. 0. FIG.

Cache controller 44 includes address multiplexing logic 100 having inputs connected to address lines A31-A2 of local bus 62, inputs/outputs connected to address lines 5A31-8A2 of expansion local bus 58, and Address input CA15-CA
Cache memory address output CAI connected to O
5-CAO and inputs connected to address lines 5AI-8AO of expansion local bus 58. It should be noted that cache memory 44 has 16 cache memory command address lines (CA15-CAO) to support cache memory sizes up to 256K.

The address multiplexing logic 100 includes tag RAMs 102 and 104.
．． 106.108 (tag RAM0-3) input and tag comparator 110.112.114.116 (tag C
OMPO-3), the valid bit decoder 118 input, the byte selection logic 120 input, and the LRU-RA
and an output connected to the input of M124. Tag RA
M102.104.106.108 each have an output connected to an input of a tag comparator 110.112.114.116. Tag comparator 110.11
2.114.116 has an input connected to the output of valid bit decoder 118 and output control logic 122.
and an output connected to an input of tag data generator 130 . The tag data generator 130 includes tag RAMs 102.104.
106.108 and an output connected to the input of the address multiplexing logic. LRU-RAMI24 is LR
Input and output control logic 122 of U@RAM 124
LRU logic 128 has an output connected to an input of LRU logic 128 and has an output connected to an input of LRU logic 128 .

The LRU logic 128 also includes the output control logic 12.
2 inputs connected to the 2 hit status outputs.

The hit status output of output control logic 122 is also connected to an input of control logic state machine 132 and an input of tag read/write control 134. Tag read/write control 134 includes:
It has an output connected to an input of tag RAM 102.104.106.108. Output control logic 122 further includes a cache memory output enable output C0ED-A# connected to a corresponding input of cache memory 42 and a cache memory write enable output CWED-A# connected to a corresponding input of cache memory 42. has.

Byte selection logic 120 has inputs connected to byte enable lines BE3-0# of local bus 62 and bus size lines MC816#, MC33 of expanded local bus 58.
It has an input connected to 2#. The byte selection logic 120 also has a cache memory selection output CC53-0# connected to a corresponding input of the cache memory 42;
Byte enable line EBE3-0 of extended local bus 58
Extended local bus byte enable output EB connected to #
E3-0#.

Control logic 132 is a CPU on local bus 62.
Bus-Op (ADS#, W/R#, D/C#,
and M/IO#), LOCK#, HLDASMEMR
#, and MEMW# lines, and the EHOLD and EREAD lines of the expansion local bus 58.
and an input connected to the YI# line. Control logic 132 includes PH0LD, R of local bus 62.
The outputs connected to EADYO# and WBS lines and the E-Bus Op (EAD
S#, EW/R#, ED/C#, and WM/IO#)
, EHLDA, and ERDYEN# lines. Control logic 132 also includes address multiplexing logic 100 and tag RAMs 102, 104 .
106.108 and tag comparators 110.112.
114.116, valid bit decoder 118, byte selection logic 120, output control logic 122, LRU RAMI 24, LRU logic 128, tag data generator 130, and tag read/write controller 134. It is connected to the.

(Left below) During normal reading and writing by the CPU 48, the address multiplexing logic 100 takes addresses A31-A15 and outputs them to the cache memory address CA1 as appropriate.
5-CAO and tag RAN102.104.106.1
08 (tag RAM0-3) and tag comparator 110
．． 112.114.116 and valid bit decoder 1
18, byte selection logic 120, and LRU RA
Distributed to MI24. Valid bit decoder 118 then receives tag comparator 110.112.1 as input.
14. decodes said address from address multiplexing logic 100 provided to 116; Tag comparator 110.
112.114.116 are address lines A31-A13 from address multiplexing logic 100, tag RAM 102
．． 104.106.108 output and valid bits...
The output of decoder 118 is taken to determine if a cache hit or cache miss has occurred.

This hit or miss determination is then sent to output control logic 122. Output control logic 122 then selects the appropriate cache memory output enable C0ED-
A# or cache memory write permission CWED-A#
and also outputs a hit status output to control logic 132 and tag read/write controller 134.

The tag data generator 130 uses the tag RAM 102
．． 104.106.108 when the tag RAM is to be updated. Tag comparators 110, 112, 114, 116 convert addresses from address multiplexing logic 100 to tag data generator 1 under control of control logic 132.
Send it to 30. The tag data number generator 130 uses this address data to update the tag RAMIO2,
Determine the data to be written to 104, 106, 108. In other words, tag comparators 110.112.114 . selected by control logic 132 .
116 from the address multiplexing logic 100 is updated to the real tag RAM 102.
．． 104.1406.108 and written to update the appropriate tag fields.

LRU-RAM 124 is a 256.times.6 bit RAM and is used to maintain a track of the last bank used by CPU 48 in cache memory 42 for each corresponding cache location. LRU-
RAMI 24 is initialized during a flush (1'1ush) sequence to a fixed sequence of three unique 2-bit bank IDs. In the direct LRU method for 4-way set associative caches, four unique 2-bit bank IDs are stored. The fourth bank ID is always derived from the other three bank IDs, so 3
Only one bank ID is stored.

LRU logic 128 performs the function of placing the most recently used bank ID at the top of a stack having a width of 2 bits and a depth of 3 bank IDs.

All other bank IDs below the most recently used ID are pushed down in the stack.

Since the depth of the stack is only 3 and the number of banks is 4, the bank ID of the oldest used bank is
However, when the cache controller 44 is in the 4-way set associative mode, the other 3 cache controllers on the stand
is logically derived from the bank ID. In the two-way set associative mode, the oldest used bank pair is indicated by the reverse most significant bits of the most recently used bank ID. In direct mapping mode, LRU
Output is ignored.

During normal operation, byte selection logic 120 outputs the appropriate cache memory chip select output (C83-0#) or the appropriate extended local bus byte enable output (EBE3-0#).
#) and make assumptions based on the byte grant lines (BH3-0#) of local bus 62. In a snoop operation, this changes in that in the case of a snoop hit, the appropriate byte in cache memory 42 to be updated must be determined. This corresponds to address line 5AI-8 of extended local bus 58 which is fed to byte selection logic 120 via address multiplexing logic 100.
Determined by AO. Next, byte selection logic 120
determines which bytes in cache memory 42 should be updated. MC from extended local bus 58
The 816# and MC832# inputs determine whether 8-bit, 16-bit or 32-bit operation is occurring.

If a copy pack has to be performed, the tag read/write controller determines the cache memory 42 storage location that has to be copy packed and the tag RAMIO2, 104, 106, 108 to be written.
Determine. For example, in the case of a write hit in copy pack mode, the tag RAMIO2, 104, 106, 108 that received the hit is determined and its dirty bit set is required.

FIGS. 8-10 are state diagrams of the processor state machine, cache operations state machine, and extended local bus state machine. Collectively, these represent the control functions performed by control logic 132 of FIG.

In the state diagrams of FIGS. 8-10, a transition occurs from one state to another when the result of the transition equation is a high logic level. For example, with respect to Figure 8, Pi and Pa
A transition between and occurs when the result of adding the oop signal to the yl- signal is a high logic level.

Here, the bar display (-) above the signal does not mean that the signal is false, but represents "no" of the signal. In the above example, a transition from Pi to Pa occurs when s noop is false (i.e., low as 5 noop is high) and ADS# is true (i.e., ADS# is high). occurs when the value is low (such that the value is low).

The processor bus state machine of FIG.
4 depicts a state diagram for the portion of the control logic of the cache controller 44 that controls the interlock between snob operations from and to the cache controller 44. FIG. The processor bus state machine enters the Pi (idle) state from the RESET state and remains in the Pi state until ADS# is asserted true (ADS# high). At the same time, 5noop is true (i.e.
If a snoop operation is in progress), the processor bus state machine transitions to the Pr state. In the Pr state,
The request on processor bus 62 is in a pending state, but has not been satisfied due to a snoop operation in progress. 5noo when ADS# becomes true (λDS# is high)
If p is false (snoop high), the bus state machine transitions to the Pa (processor bus active) state.

Once the processor bus state machine is in the Pr state, it remains there until 5noop goes false (snoop high) indicating that the snoop operation is complete. Then, it transitions to the Pa state.

In the Pa state, ready# is true (V lower ready
When # goes high), the processor bus state machine
Transition to i state. If ready# does not go true on the next clock cycle (i.e., ready# remains high), the processor bus state machine will run P2 until ready# becomes true (pready# is high). state and remain there, at which point the processor bus state machine transitions back to the Pi state. The P2 state is the processor bus 6
2, the state between the end of the first clock cycle and the state transition that occurs during the second clock cycle. (Processor bus 62 operations typically require two clock cycles.) If the processor bus state machine is in the Pa state, no snoop operation is initiated. Conversely, if a snoop operation is being performed, the Pa state is not entered. pre
The ady# signal is true (i.e., pr
cannot be low) as easy# is high.

The cache operational state machine of FIG.
This shows the state while M42 is empty or empty. The cache operation state machine enters the RESET state or the 0Pf (flush) state and
It remains in that state until the it done signal becomes true.

In1t d.

The ne times signal comes from the carry output of the 8-bit address counter of cache controller 44, which is used to sequence all the cache tags in cache controller 44. When the cache operation state machine enters the OPf state, a write operation is forced with all block valid and dirty bits in each tag being cleared. As a result, the cache controller 44 is initialized to an empty cache state. While in the OPf state, all processor bus 62 requests are processed by cache fill (cachef'1ll).
Treated as a miss unless b<never executed.

When the cache operation state machine is in the 0Pi (idle) state, lookups during tags are performed on processor bus 6.
2 request or a snoop request. The inputs to the cache operation state machine, rdmiss signal, dirty signal and block hit signal, are:
It is fixed only during the Pa state of the processor bus state machine of FIG. The cache activity state machine remains in the OPi state until a cacheable CPU 48 memory read operation occurs that causes a cache read miss. When a cache read miss occurs, the cache operating state machine determines the segment of cache memory 42 to which the requested main memory location is to be written before writing the requested main memory location into cache memory 42. A transition is made to either the OPr state or the OPw state, depending on whether it is necessary to "copy pack" into main memory 60.

If the block containing the requested main memory storage location is in cache memory 42, the Catch i operational state machine transitions to the OPr state. At this time, subblocks within this block other than the subblock containing the requested main memory 60 storage location are stored in the cache memory 42. The cache operation state machine also determines whether the block containing the selected main memory 60 is not in the memory location cache memory 42 provided that the block to which the selected main memory 60 memory location is to be written is not "dirty." The OPr
Transition to state.

If the block containing the requested main memory location is not in cache memory 42, then the LRU-
RAM is used to determine if the available tag for the memory location is the oldest used. Next, the dirty bits for that tag are checked. If the dirty bit is false (dirty is high), the cache operation state machine transitions to the OPr state. Conversely, if the dirty bit is true (high), the cache operation state machine transitions to the OPw state where a "copyback" occurs.

In the OPr state, new subblocks containing the requested main memory 60 storage locations are read from main memory 60 into cache memory 42 in such an order that the last word read satisfies the CPU 48 read request.

E_req is taken true and remains true until enough extended local bus 58 reads have occurred to satisfy the subblock counter in cache controller 44.

At that point, sb 1ast is set true (high) to transition the cache operational state machine to the OPi state.

In the case of the OPw state, the cache controller 4
4 performs a memory write to main memory 60 of all valid subblocks within the block of LRU tags. The valid bit of each subblock is cleared when the last word of each subblock is written. If all valid bits of the LRU block are cleared, blk val
id is set to false (low). If the subblock is being written, sb 1ast is true (high)
become. At this point, the cache operational state machine transitions to the OPr state. During this transition, sb
1ast is reset to false (low).

The enhanced local bus state machine of FIG. 10 is a state diagram for the portion of the control logic of the cache controller 44 that controls the interlock between the operation of the enhanced local bus 58 and the CPU 48. During the RESET state, the extended local bus state machine is placed in the Ei (idle) state. The state machine is
signal is true (high) or EHOLD is true (high) and cache controller 44
remains in the E2 state until other conditions exist that may cause the extended local bus 48 to be released. If EHOLD is true (high) in either the Ei state or the E2 state, then
LOCK# of CPU48 is false (fi is high) and WB
S is false (WBS high) to indicate that the after-write buffer is empty, and the cache operational state machine of FIG. 9 is not in the OPr state (i.e., a new subblock is currently Eh( has not been fetched from main memory 60 into cache memory 42 ).
hold) state. If all of these conditions are not met, EHOLD is ignored until they are met and the extended local bus state machine is in either the Ei or E2 state.

If the EHOLD conditions are not true in the Ei state, the extended local bus state machine holds the EHOLD condition until they are true or E_req is true (high).
Stay in i-state. E_req is true and the EH
If the OLD condition is not, the extended local bus state machine transitions to the E1 state. Said EHOL
Note that the D condition takes precedence over Ereq.

If in the E1 state, the extended local bus state machine:
It always transitions to E2 state by the next cycle. If in state E2, the extended local bus state machine
Stays in E2 state until READYI # is true (EREADYI # is high).

EREADYI# is true (E, REA
If DYI # is high), the extended local bus state machine transitions to the next state, either Ei, El, or Eh. If the EHOLD condition is true, the enhanced local bus state machine transitions to the Eh state regardless of other inputs.

If the EHOLD condition is not true, the enhanced local bus state machine returns to the E1 state if the E_req is true (high) or to the E1 state if the E_req is not true (E_req is high). transitions to the Ei state.

If the extended local bus state machine is in the Eh state, it remains there as long as EHOLD is true, regardless of other conditions. EHOLD becomes false (EHO
If LD goes high) and Ereq is false (E_req is high), the enhanced local bus state machine transitions to the Ei state. If EHOLD becomes false (EHOLD high) and E_req is true (high), then
The extended local bus state machine transitions to the E1 state.

The extended local bus state machine directly controls the EHLDA signal, which is the output of extended local bus 58, to indicate to remote bus mask devices that it is in control of the bus. The Eh state is the cache controller 4
4 (all extended local bus control signals other than EHLDA driven by EHLDA are disabled and undriven), and the EHLDA signal is made true (high). Depending on the E1 state,
The EADS# output is assumed to be true (low) for the duration of the state, indicating to devices on the expansion local bus 58 that expansion local bus 58 is beginning to operate. Said E2
Depending on the state, the CPU4 uses the EREADY1# signal.
The ready# signal to be the output of
It is only during certain operations that terminate with an external or system bus 56 operation that must be sent to the U 48 or the CPU 48 must not proceed until the external bus 56 operation is complete.

jsnoopJ signal, rpready#J signal, signal,
The rblock hitJ signal, the “E req” signal, and the [sb 1astJ signal are all internally generated signals of the cache controller 44.

Although the present invention has been described above in detail with reference to specific embodiments, the present invention can be implemented by adding various modifications and changes to the above-described embodiments within its technical scope.

(Margin below) Table ＾ Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating the cache structure for a directly mapped 32KB cache memory. FIG. 2 is a block diagram showing the cache structure for a 32 KB cache memory with two-way set associativity. FIG. 3 is a block diagram illustrating the cache structure for a 32 KB cache memory with 4-way set associativity. FIG. 4 is a block diagram illustrating a conventional microcomputer system having a cache memory using a prior art Intel 82385 cache controller. FIG. 5 is a block diagram of a microcomputer system having a cache memory using the cache controller of the present invention. FIG. 6 is a block diagram illustrating the hardware interfaces for various control inputs and outputs to the cache controller of FIG. 5. FIG. 7 is a block diagram consisting of FIG. 7a and FIG. 7b showing details of a cache controller constructed according to the present invention. 8 to 10 are state diagrams showing the operation of the cache controller of FIG. 7, respectively. 10...Microcomputer system, 12...
・Microprocessor, 14...cache memory,
18...32-bit transceiver, 20...chip set, 22...16-bit buffer, 24...
32-bit buffer, 26... Bus control output, 28... 8-bit e-latch, 30... Cache controller, 32... System bus, 34...
・Local bus, 36...DMA device, 38...
- Main memory, 40... Microcomputer Φ system, 42... Cache RAM, 44... Cache controller, 46... DMA device, 48...
・CPU.

Claims (3)

[Claims] (1) a processor having a processor address bus and a processor data bus and capable of executing locked write instruction sequences; and a plurality of locations for storing data and a cache connected to the processor data bus. a cache memory having a data bus; a system bus having a system address line and a system data line; and a system bus having a plurality of locations for storing data, and having a plurality of locations for storing data; a main memory connected to the system address line and the system data line; a peripheral device connected to the system address line and the system data line; A control for halting operation of the processor prior to initiation of a lock write instruction if the peripheral device is connected to a data bus, cache memory, system address line, and system data line, and the peripheral device is controlling the system bus. and means, when the processor initiates a lock instruction sequence,
A microcomputer system, wherein the control means disables the peripheral device from controlling the system bus. (2) said microprocessor initiates a full lock instruction sequence with a lock read instruction and communicates a lock instruction signal to said control means upon executing a lock instruction; a ready input line for receiving a ready signal indicating the presence of valid data, the peripheral device controlling the system bus when the processor initiates a read lock instruction; 2. The microcomputer system of claim 1, wherein said control means halts said processor by assuming said ready input line to be false until said controller ceases controlling said system bus. (3) the peripheral device has an EHOLD signal line connected to the control means for communicating a request signal to the control means; for enabling the control means to communicate EHLDA signals to said peripheral device;
an EHLDA signal line connected to the peripheral device, the peripheral device receiving the EHLDA signal allowing the peripheral device to control the system bus, and causing the processor to execute a lock instruction. 3. The microcomputer system of claim 2, wherein said control means prevents said EHLDA signal from becoming true at times.