JPH03185837A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PURPOSE:To reduce irregularity of element characteristics by introducing impurities from the surface side of a silicon substrate by ion implantation, forming a semiconductor region having a constant depth from the surface by heat treatment, and making a semiconductor layer having a constant thickness on said region an operating region of a bipolar transistor. CONSTITUTION:After N-type impurities like As is ion-implanted in the rear of an N-type silicon substrate 1, a high concentration semiconductor region 2 is formed by heat treatment. After a thermal oxide film 3 is formed, another silicon substrate 4 is bonded to the lower surface. Then the upper side silicon substrate 1 is polished from above, while the lower surface of the lower side substrate 4 is set as the reference, and the semiconductor layer 1' is left. After the surface polishing, an SOI substrate is put in an ion implanter, and subjected to two-step ion implantation of N-type impurities. Thereby an ion implanted region 5 overlapping with the high concentration semiconductor region 2 is formed. After that, implanted ions are activated by heat treatment, and a medium concentration semiconductor region 5' whose impurity concentration is higher than the substrate 1 and lower than the high concentration semiconductor region 2 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Fields of Application] The present invention relates to semiconductor devices and their manufacturing technology, as well as 5O
The present invention relates to a technique that is particularly effective when applied to a semiconductor device having an I (silicon-on-insulator) structure and its manufacturing process, and relates to a technique that is particularly effective when applied to, for example, an LSI having a vertical bipolar transistor and its manufacturing method.

[Prior art] In recent years, in bipolar integrated circuits, N is used as the collector region.
Vertical bipolar transistors using type 4 buried layers have become mainstream. In addition, in a bipolar transistor using such an N+ type buried layer, it is technically difficult to form one buried layer by high-energy, high-dose ion implantation and drilling methods from the surface of the semiconductor substrate. Since there are disadvantages such as crystal defects and dislocations, a high-concentration N+ region that will become a buried layer is selectively formed on the surface of the semiconductor substrate (silicon substrate) in advance, and then a low-concentration epitaxial layer is formed on the semiconductor substrate. The most common structure was one in which a base and an emitter region were formed on the surface of the substrate.

On the other hand, by using wafer bonding technology, a highly concentrated diffusion layer that will become the collector of the bipolar transistor is formed in advance on the back surface of the first semiconductor substrate on which the bipolar transistor is to be formed, and an insulating layer is formed on the surface. For example, a technique for manufacturing a bipolar transistor having an SOI structure by bonding a second semiconductor substrate on which is formed with the first semiconductor substrate is disclosed in Japanese Patent Laid-Open No. 63-349.
It is described in Publication No. 49. Bipolar transistors with such an SOI structure are suitable for high-speed operation because the highly doped diffused layer that serves as the collector is in direct contact with the insulating film, which reduces collector parasitic capacitance and reduces the PN junction area. , it is also resistant to soft errors caused by alpha rays.

[Problems to be Solved by the Invention] The inventor of the present invention has clarified the following problems as a result of studying how to increase the speed, high reliability, and reduce the process cost of a semiconductor integrated circuit device having a bipolar transistor.

In the bipolar transistor using the epitaxial layer described above, the controllability of the epitaxial layer thickness is relatively good (for example, ±0.05μ at the wafer level).
m), the thickness of the epitaxial layer of each semiconductor chip can be made uniform. This means that the thickness of the collector region of the bipolar transistors formed on each semiconductor chip can be made uniform, and the yield of bipolar transistors having predetermined electrical characteristics can be improved.

However, in bipolar transistors using the above epitaxial layer, impurities are randomly auto-doped into the epitaxial layer from the highly concentrated N4 type buried layer during growth of the epitaxial layer. Electrical characteristics of bipolar transistors, such as cutoff frequency fT, vary between chips or within one semiconductor chip.
There is a problem that the values vary. The autodoping depends on the impurity concentration of the N+ type embedded layer, and becomes more pronounced as the impurity concentration increases.
There is a restriction on increasing the impurity concentration of the + type buried layer. As a result, it becomes difficult to lower the resistance value of the collector region, so there is a problem that it is impossible to further increase the speed of the bipolar transistor.

In addition, the bipolar transistor using the above-mentioned epitaxial layer can reduce the process cost because the equipment used for epitaxial growth is expensive and the number of wafers that can be processed at one time by the equipment is small, for example, about 10. There is a problem that this cannot be adequately planned.

Furthermore, when obtaining an SOI substrate using the conventional wafer bonding method described above, it is not possible to bond very thin wafers to each other due to the strength of the silicon wafer, so after bonding wafers that are relatively thick,
A semiconductor layer (silicon wafer) having a desired thickness is formed by mechanically polishing the surface of a wafer on which semiconductor elements are to be formed.

Wafer polishing as described above can process several tens of wafers at a time, so it has the advantage of reducing process costs compared to forming a semiconductor layer by epitaxial growth.

However, with the technique of thinning the semiconductor layer by polishing, the variation in the thickness of the semiconductor layer is as large as ±0.5 μm, and it is difficult to keep the variation within the same level of variation (approximately ±0.05 μm) as that of a semiconductor layer formed by epitaxial growth. It was difficult.

Therefore, in a conventional bipolar transistor having an SOI structure, variations in the thickness of the semiconductor layer on the buried layer become large. Since the emitter and base regions of the bipolar transistor are formed on the surface of the semiconductor layer whose thickness varies widely, the distance between the emitter and base region and the buried layer (in other words, when the bipolar transistor operates) The distance from the emitter region to the buried layer) varies within one semiconductor chip or between each semiconductor chip (at the wafer level). As a result, the electrical characteristics of bipolar transistors (e.g. cutoff frequency fT, emitter
Collector breakdown voltage BVcEO, base-collector parasitic capacitance CTC, etc.) vary greatly within one semiconductor chip or between each semiconductor chip. This causes a problem in that the manufacturing yield of semiconductor integrated circuit devices having bipolar transistors having desired electrical characteristics is reduced.

In addition, if the electrical characteristics vary widely as described above, the system must be designed assuming, for example, a bipolar transistor with the slowest switching speed, which is not sufficient for high-speed systems. There's a problem.

To specifically explain the variations in the electrical characteristics, as shown in FIG. 8, when the thickness of the semiconductor layer becomes larger than the target value of 1.0 μm, for example, the emitter-collector breakdown voltage BVc EO becomes: Although the base-collector parasitic capacitance is reduced, the cutoff frequency fT is lowered. On the other hand, if the cutoff frequency fT becomes smaller than the target value, the cutoff frequency fT improves, but the emitter/collector 1iJi
The breakdown voltage BVcEO decreases and the base-collector parasitic capacitance also increases.

When a bipolar transistor is formed using semiconductor layers with varying thicknesses, for example, curve A in FIG.
As shown in Figure 2, the gate delay time varies depending on the thickness of the semiconductor layer, making it unsuitable for high-speed systems.

Incidentally, FIG. 7 above shows an example of a case where a bipolar ECL gate is assembled.

The present invention has been made to solve the various problems mentioned above, and its purpose is to reduce variations in the characteristics of elements in semiconductor integrated circuit devices using bonded SOI substrates. The purpose of this invention is to improve the performance and yield of LSI.

Another object of the present invention is to provide a bipolar transistor with an SOT structure that reduces the current dependence of device characteristics and has a good base-collector breakdown voltage.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] A typical overview of the inventions disclosed in this application is as follows. Namely, the first means of the present invention is to provide an SOI substrate using a wafer bonding method. When forming a semiconductor integrated circuit, after polishing the substrate, impurities are introduced from the surface side of the silicon substrate by ion implantation, and a semiconductor region or semi-insulating region is formed at a certain depth from the surface by heat treatment. A semiconductor layer having a certain thickness thereon is used as an operating region of a bipolar transistor or a MOS transistor.

Moreover, the second means is a wafer bonding method SOI
In the substrate, a low concentration semiconductor region is formed at a certain depth from the surface of the silicon substrate so as to overlap with the high concentration semiconductor region previously formed on the back surface of the silicon substrate before bonding. This paper proposes a vertical bipolar transistor having a structure in which a base and an emitter region are formed in a semiconductor layer above the semiconductor layer. In this case, it is desirable to set the impurity concentration of the high concentration semiconductor to 1X1×1016 cm.
Above, the impurity concentration of the low concentration semiconductor region is 1×101@c
m-4 or less, and the concentration distribution of the low concentration semiconductor region is preferably as flat as possible.

[Operation] According to the above-mentioned first means, when polishing a wafer bonding type SO substrate to obtain a semiconductor layer of a predetermined thickness, even if there is a large variation in polishing, it is possible to obtain a uniform layer from the surface by ion implantation. Since a semiconductor region or a semi-insulating region is formed at a depth of , variations in the thickness of the semiconductor layer that forms the device operation region above it are extremely small. This makes it possible to achieve the above-mentioned purpose of reducing variations in device characteristics and improving LSI performance and yield.

Further, according to the above-mentioned second means, the thickness of the semiconductor layer in which the base and emitter regions are formed is constant and the variation is small, so the variation in device characteristics is reduced, and
A low-concentration semiconductor region is formed on top of the high-concentration semiconductor region (buried layer) and is used as a collector region, which prevents the spread of the base due to the Kirk effect and prevents base-collector breakdown voltage. As a result, it is possible to obtain a bipolar transistor with an SOT structure in which the dependence of device characteristics on current is reduced and a good withstand voltage is achieved.

[Embodiment 1] An example of a process in which the present invention is applied to a base-emitter self-aligned bipolar transistor will be described below with reference to FIGS. 1(A) to 1()I).

First, an N-type impurity such as As (arsenic) is ion-implanted into the back surface of an N-type silicon substrate 1, and then heat treatment is performed to form a high concentration semiconductor region 2. As the silicon substrate 1, for example, a substrate with a thickness of about 500 μm and a sheet resistance of about 1 Ω·mark is used, and the ion implantation conditions are, for example, implantation energy of 100 KeV and implantation amount of 1.5XIO'″cm.
-", and the heat treatment conditions are set at a temperature of 1000°C and a treatment time of around 60 minutes. As a result, a depth of about 1.0 μm, which will later become a buried layer, is formed on the back surface of the silicon substrate l.
, a high concentration N1 type semiconductor region 2 having a carrier concentration of 1.5 X IO "cm-" can be formed. After that, a silicon oxide film (thermal oxidation [) 3
(Fig. 1(A)).

Note that the thickness of the thermal oxide film 3 is approximately 5,000 people. Further, in forming the N+ type semiconductor region 2 by the above-mentioned ion implantation, Sb (antimony), P (phosphorous), etc. may be used as an impurity in addition to As. However, among these, As
Since As has the highest solid solubility in silicon and has the slowest diffusion rate, it is preferable to use As to obtain the N+ type semiconductor region 2 with low resistance. In addition, the impurity may be introduced by a thermal diffusion method instead of the ion implantation method.

After forming the thermally oxidized film M3, another silicon substrate 4 having a thickness of about 500 μm is bonded to the back surface of the substrate l, that is, the lower surface of the thermally oxidized film 3. The two substrates 1 and 4 can be bonded by stacking the two boards with good flatness at room temperature and then annealing them at a high temperature (for example, 1100°C for 60 minutes), or by applying a voltage (100V to 500V)L, a method of bonding by electrostatic force and then annealing at a high temperature (1100° C., 30 minutes) is known.

After bonding the substrates, the upper silicon substrate 1 is polished from above using a single-sided polishing device with the lower surface of the lower substrate 4 as a reference, leaving a semiconductor layer 1'' with a thickness of about 2.5 μm (see Fig. 1 (B). )
). Note that the semiconductor layer 1' after polishing has a variation of about ±0.5 μm.

After surface polishing, the SOI substrate is placed in an ion implanter, and N-type impurity ions are implanted from the surface in two steps. Phosphorus ions are a good impurity, and the implantation conditions are a first implantation energy of 600KeV.

The dose was I
m-''. By this, as shown in FIG.
A heat treatment is performed at 00° C. for 30 minutes to activate the implanted ions and form a medium-concentration semiconductor region 5' having a higher impurity concentration than the substrate 1 and a lower concentration than the high-concentration semiconductor region 2.

In the above case, the implanted ions are p++ or p+
If it is in the form of +1, each of the above driving energies will be reduced by 1/
It can be reduced to 2 and 1/3.

Next, the thermal oxide film 3 is placed around a region where a bipolar transistor is to be formed (hereinafter referred to as an element region).
After forming a deep groove reaching 100 mm by anisotropic dry etching or the like, performing surface oxidation to form a silicon oxide film 6 inside the groove, polysilicon is deposited on the entire surface of the substrate and etched back. After filling the inside of the trench with polysilicon 7, the polysilicon on the surface is oxidized to form a silicon oxide film on the surface to form a trench isolation region 9. Furthermore, when forming the silicon oxide film on the surface of the polysilicon in the trench, it is preferable to form a relatively thick field oxide film 10 around the element region and on the surface of the boundary between the base region and the collector region. Thereafter, N-type impurities are selectively ion-implanted or diffused at a high concentration into the region that will become the collector pull-up region to form an N1-type collector pull-up region 11 that reaches the high-concentration semiconductor region 2, as shown in FIG. The state becomes D).

Next, a non-doped polysilicon layer 12 is deposited on the substrate surface, the surface is oxidized, and then a P-type impurity such as boron is implanted into the entire surface of the polysilicon layer 12 by ion implantation. Thereafter, a silicon oxide film 13 is formed on the surface by CVD or the like, and then a base lead electrode 12a is left at the periphery of the surface of the element region by selective etching (FIG. 1(E)).

Then, a heat treatment is performed to form a P-type external base region 14a on the substrate surface by diffusion from the polysilicon (base extraction electrode) 12a.

Thereafter, an insulator such as silicon oxide is deposited relatively thickly over the entire surface of the substrate, and then etched back to leave a sidewall 15 on the sidewall of the base extraction electrode 12a. Thereafter, the side of the collector extraction region (11) is covered with a resist, and using this resist and the sidewall 15 as an ion implantation mask, P-type impurities are implanted into the substrate surface inside the base extraction electrode 12a to form a relatively shallow intrinsic base region. When the sydist serving as a mask is removed after forming 14b, the state shown in FIG. 1(F) is obtained.

Next, a non-doped polysilicon layer 17 is deposited over the entire surface of the substrate, and an N-type impurity such as As is implanted into the polysilicon layer 17 by ion implantation, followed by heat treatment. by this,
An N-type emitter region 18 is formed on the base region 14b on the substrate surface by diffusion of impurity (As) from the polysilicon layer 17. After that, the polysilicon layer I7 is etched by selective etching.
The emitter electrode 17a is formed by etching and leaving the polysilicon only above the emitter region 18 (
Figure 1 (G)). At this time, the emitter electrode 17a and the base electrode 12a are insulated by a side wall (silicon oxide) 15.

After that, an insulating film 19 such as a silicon oxide film or a silicon nitride film is formed on the surface of the substrate, contact holes and through holes are formed in this insulating film 19, and then an aluminum layer 20 is deposited and patterned. Electrode 12a
and aluminum electrodes 20a and 20b that are in contact with the emitter electrode 17a and the collector pull-up region 11, respectively.
, 20c (Fig. 1(H)).

Next, S is deposited on the aluminum electrodes 20a to 20c by vapor deposition.
After depositing an interlayer insulating film such as iO, Si, N, or SOG (spin-on-glass) film, a second layer of aluminum wiring is formed, and then a second interlayer insulating film is formed on top of it. After the deposition, a third layer of aluminum wiring is formed, and a passivation film is deposited thereon to complete the process.

FIG. 2 shows a plan view of the bipolar transistor of the above embodiment.

In the figure, a region with hatching extending downward to the right is a rectangular bar-shaped trench isolation region 9 formed so as to surround the element region. Furthermore, in this embodiment, a field oxide film 10 is formed over the entire surface of the substrate.
A base, emitter and collector pulling region are formed in the opening. The symbols 10a and 10b in FIG.
This is an opening for an element region formed in the field oxide film 10.

Further, reference numerals 12a and 17a are a base extraction electrode and an emitter electrode made of polysilicon, respectively, and the hatched portion extending upward to the right is a sidewall 15 that insulates between the two electrodes. Further, 21a and 21b are aluminum'11 poles 20a, respectively.

20b as base extraction electrode 12a and emitter electrode 1
A contact hole 21c is a contact hole for connecting the aluminum electrode 20c to the collector pull-up region 11.

In order to understand the variations in the transistors of the above embodiments, the profile of impurity concentration in the depth direction of the base and emitter forming regions was investigated. The concentration profiles are shown at three locations indicated by symbols A-A', B-B', and c-c' in Figure 3, which exaggerates the thickness of each layer of the substrate at the stage of Figure 1 (C). The measurement results are shown in Figures 4 (A), (B), and (C). In other words, the same figure (A) is the semiconductor after polishing! The concentration profile of the thinnest part of 1' (C) is the concentration profile of the thickest part, (B) of the same figure
is the concentration profile at the intermediate thickness.

In addition, in FIG. 4, the symbol a indicates N of the emitter region 18.
Type impurity concentration west line, symbol P of the intrinsic base region 14a
type impurity concentration curve, symbol C indicates the medium concentration semiconductor region 5 resulting from the first ion implantation, and symbol d represents the medium concentration semiconductor region 5 resulting from the second ion implantation.
'' indicates an N-type impurity concentration curve, and symbol e indicates an impurity concentration curve of the high concentration semiconductor region 2 formed by ion implantation from the back surface of the substrate.

From the figure, even if the thickness of the semiconductor layer 1' varies from 2 to 3 .mu.m, the depth of the medium concentration semiconductor region 5' remains approximately constant at about 0.4 .mu.m. Furthermore, if the ion implantation is performed only once, it can be considered that there is no part marked d, so as it becomes thicker, the low concentration semiconductor region 5° and the high concentration semiconductor region 2 are separated, as is clear from FIG. Although the collector resistance increases due to the separation, it can be seen that the profile of the medium concentration semiconductor region 5'' can be flattened by two implantations.

Furthermore, the first ion implantation (energy 600KeV
), the maximum concentration of the medium concentration semiconductor region 5' is 3XlO''
The mark becomes “-”, and the second @ ion implantation (energy 1Me
It can be seen that the maximum concentration due to V) is 8×10 mark −°, and there is a concentration difference of about 10′ to 10° from the high concentration semiconductor region 2.

Generally, in a transistor in which the concentration of the semiconductor region between the base region 14a and the high concentration semiconductor region 2 as a buried layer is less than 1O"c+N', that is, in a transistor in which the concentration difference is 10'cm-" or more, the collector As the current increases, the base region 14a spreads downward, deteriorating the characteristics, and if the concentration of the medium concentration semiconductor region 5° increases to 1013 or more, the base-collector breakdown voltage decreases. However, in the transistor of the above embodiment, since there is a medium concentration semiconductor region 5'' of about 10~1013 am-'' between the base region 14a and the high concentration semiconductor region 3, the current dependence of the device characteristics is It has the advantage of being small in size and also having a high base-collector breakdown voltage.

In order to understand the difference in characteristics from conventional devices, an E-L gate was constructed using the bipolar transistor having the structure of the above embodiment, and its delay time was taken advantage of.

Figure 7 shows the results. Here, the horizontal axis shows the thickness of the semiconductor layer 1', and the vertical axis shows the delay time of the ECL gate. The curve A shows the variation in delay time when a conventional transistor having only a diffusion layer from the back side is used.

When an optimal design is performed with the center value of the thickness set to 167 μm, if the thickness varies by ±0.5 μm, the delay time will significantly increase (approximately 70 μm) due to the corresponding change in bipolar characteristics.
%) varies. On the other hand, the curve B indicates the case where an ECL gate is constructed using the transistor of this embodiment, and even if the thickness of the semiconductor layer 1' varies, the variation in delay time can be suppressed to 10% or less. That is, it can be seen that bipolar transistors can be formed at high speed and with little variation without using epitaxial growth, which has a high process cost.

In the above embodiment, the medium concentration semiconductor region 5'' was formed by two steps of ion implantation from the surface, but depending on the variation in thickness, only one step or three or more steps of ion implantation may be performed. It is also possible to do so.

Furthermore, in the above embodiment, relatively high-energy ion implantation is performed and defects caused by ion implantation are removed by heat treatment (1000°C), but defects can be removed by annealing, although it depends on the ion species. In the case of phosphorus, it is usually about 1×101 cm or less. Therefore, in the above embodiment, the implantation amount can be adjusted up to 1×10'cm-' as required. That is, the impurity concentration is within a practical range of 1x10'cm' or less.

Furthermore, instead of the highly doped semiconductor region (buried layer) 2 for lowering the collector resistance, W (tungsten), Ti,
A silicide layer of a high melting point metal such as Co or PC may also be used. In this case, in order to prevent the silicide layer from peeling off from the silicon substrate, it is preferable to form the silicide layer on the back surface of the silicon substrate with a buffer layer such as a polysilicon layer interposed therebetween.

Further, the insulating film 3 may be formed not on the back surface of the silicon substrate 1 but on the surface of the other silicon substrate 4 to be bonded, and the two substrates may be bonded together.

As explained above, the bipolar transistor of the above embodiment has the following characteristics:
A medium concentration semiconductor region is formed at a certain depth from the surface of the silicon substrate so as to overlap with a high concentration semiconductor region previously formed on the back surface of the silicon substrate before bonding, and a low concentration semiconductor region above this medium concentration semiconductor region is formed. Since the base and emitter regions are formed in the semiconductor layer, variations in the thickness of the lightly doped semiconductor layer in which the base and emitter regions are formed are small and constant, which reduces variations in device characteristics and also reduces the variation in the thickness of the lightly doped semiconductor layer where the base and emitter regions are formed. A medium-concentration semiconductor region is formed on top of the region (buried layer) and overlaps with this region, and this is used as the collector region, which prevents the spread of the base due to the Kirk effect and improves the breakdown voltage between the base and collector. As a result, the current dependence of the device characteristics becomes smaller.
Moreover, there is an effect that the withstand voltage is improved.

Another advantage of the SOI structure transistor is high α-ray intensity.

FIG. 5 shows an embodiment in which the present invention is applied to a B1-CMOS integrated circuit.

The difference between the semiconductor integrated circuit device of this embodiment and the device of the first embodiment is that the medium-concentration semiconductor region 5' formed by ion implantation from the surface is limited only to the lower part of the emitter region 18, rather than to the entire substrate. The second point is that a P-channel MO8FET and an N-channel MO3FET are formed together with a bipolar transistor on the same substrate.

Hereinafter, in the device structure of FIG. 5, the same parts as those of the transistor of the embodiment shown in FIG. 1 will be denoted by the same reference numerals, redundant explanation will be omitted, and differences will be explained.

In this embodiment, by ion implantation of N-type impurity (P) from the surface of the substrate only below the emitter region 18, a medium concentration semiconductor region 5'' overlapping with the high concentration semiconductor region 2 is selectively implanted by impurity implantation from the back surface. Since the collector current flows only below the emitter region 18, even if the medium concentration semiconductor region 5'' is limited below the emitter region, the transistor having the structure shown in FIG. The characteristics do not deteriorate in comparison.

Further, the formation of the above-mentioned local medium concentration semiconductor region 5'' is carried out by performing ion implantation using the resist mask 25 immediately after the emitter window opening inside the base extraction electrode 12a is processed, as shown in FIG. 6, for example. Then, the medium concentration semiconductor region 5'' can be selectively formed below the emitter without increasing the number of masks.

Furthermore, in this embodiment, P-type source and drain regions 33 are formed on the surface of the N-well region 3° surrounded by the trench isolation region 9 in a self-aligned manner on both sides using the gate electrode 31 and its sidewalls 15' as masks.
a, 33b are formed, and the N well region 3
A heavily doped semiconductor region 2' is formed at the bottom of the semiconductor layer 2' by implanting N-type impurities from the back surface. This heavily doped semiconductor region 2' serves to lower the substrate resistance of the P-channel MO3FET. In the above embodiment, when the initial concentration of the silicon substrate l is about 101 to 1013 cm-'', there is no need to introduce any impurity into the N-well region 30. When c+N' or less, the bipolar transistor side medium concentration semiconductor region 5
The N-well region 30 can be formed by ion implantation at the same time as or in a completely separate step from the formation of the N-well region 30.

On the other hand, in this embodiment, the trench isolation region 9
A gate electrode 4I is placed on the P well region 40 surrounded by
and source and drain regions 43a.

43b is formed, and a semi-insulating region 44 is formed at the bottom of the P well region 40. This semi-insulating region 44 can be formed by selectively implanting 01 ions using an ion implantation method so as to overlap with the silicon oxide film 3 before forming the gate electrode, and then performing heat treatment. With substrates other than SOI structures, it is difficult to form an insulating region in the form of a buried layer inside the substrate, but since the silicon oxide layer 3 originally exists inside the SOT substrate, O and ions from the surface are not absorbed. By implantation, it is possible to relatively easily form a semi-insulating region with a concentration sufficient to suppress the expansion of the depletion layer when a gate voltage is applied. Making the P-well shallower by forming a semi-insulating region 44 at the bottom of the P-well region 40 has the advantage of increasing the carrier mobility of the MOSFET and improving device characteristics.

As explained above, in the above embodiment, when a semiconductor integrated circuit is formed on an SOI substrate using a wafer bonding method, after polishing the substrate surface, impurities are introduced from the surface side of the silicon substrate by ion implantation and heat treatment is performed. By that,
A semiconductor region or a semi-insulating region is formed at a certain depth from the surface, and the semiconductor layer with a certain thickness above it is used as the operating region of bipolar transistors and MOS transistors, so even if there are large variations in polishing, Also, since a semiconductor region or a semi-insulating region is formed at a certain depth from the surface by ion implantation, variations in the thickness of the semiconductor layer which forms the device operation region thereon are extremely small. This has the effect of reducing variations in device characteristics and improving LSI performance and yield.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, a trench isolation structure is used as the element isolation region, but PN junction isolation or isolation using an insulating film may also be used.

In the above explanation, the invention made by the present inventor was mainly applied to silicon LSI, which is the background application field, but this invention is not limited thereto, and is applicable to GaAS and other compound semiconductor devices. can also be used.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, in a semiconductor device using a bonded type SOI substrate, even if there are large variations in polishing, a semiconductor region or a semi-insulating region is formed at a certain depth from the surface by ion implantation, so the device on it is Variations in the thickness of the semiconductor layer serving as the operating region become extremely small. This reduces variations in device characteristics and increases the
In addition to improving the performance and yield of I, the base,
Since the thickness of the semiconductor layer in which the emitter region is formed is constant and the variation is small, variations in device characteristics are reduced, and a medium-concentration semiconductor region is formed on and overlapping the high-concentration semiconductor region (buried layer). Since this is used as the collector region, it is possible to prevent the spread of the base due to the Kirk effect and improve the breakdown voltage between the base and collector. A bipolar transistor with an SOI structure can be obtained.

[Brief explanation of drawings]

1(A) to 1(H) are cross-sectional views showing one embodiment of the present invention in the order of steps when applied to a bipolar LSI; FIG. 2 is a plan view of a pibolar transistor to which the present invention is applied; The figure is a cross-sectional view showing the state of the wafer after polishing and ion implantation, and Figures 4 (A) to (C) are A-A', B-B', and C-C in Figure 3 after transistor formation. 5 is a graph showing the impurity concentration distribution along the line 'Bi-
0MO8LSI is a cross-sectional view showing an example of the method of forming a medium concentration semiconductor region (pedestal) in the middle of the process. FIG. 7 is a bipolar device to which the present invention is applied. A graph showing the relationship between the gate delay time of the ECL gate and the depth of the buried layer in LSI and conventional bipolar LSI. Figure 8 shows the thickness and cutoff of the epitaxial layer (or equivalent semiconductor layer) in a vertical bipolar transistor. 7 is a graph showing the relationship between frequency, base-collector breakdown voltage, and base-collector junction capacitance. 1.4...Silicon substrate, 1'...Semiconductor layer, 2...High concentration semiconductor region, 3...Thermal oxide film,
5...Ion implantation layer, 5'...Medium concentration semiconductor region, 6...Silicon oxide film, 7...Polysilicon, 9...Trench isolation region, l
O...Field oxide film, 12a...Base extraction electrode 1.14a...External base region, 14b...
...Intrinsic base area, 15...Side wall,
17a...Emitter electrode. Figure (A) A' Figure Figure

Claims (1)

[Claims] 1. S made by laminating a semiconductor single crystal substrate on an insulator
In a semiconductor device in which a bipolar transistor is formed on a substrate with an OI structure, a high concentration semiconductor region of a first conductivity type is formed on the back side of the semiconductor substrate in contact with the insulator, and overlaps with the high concentration semiconductor region. A semiconductor region of the same conductivity type as the high concentration semiconductor region but with a lower concentration than the high concentration semiconductor region is formed at a certain depth from the surface, and a semiconductor region of a second conductivity type is formed in the semiconductor layer above this relatively low concentration semiconductor region. A semiconductor device further comprising a semiconductor region of a first conductivity type formed thereon. 2. The impurity concentration of the high concentration semiconductor region is 1×10^
1^3cm^-^3 or more, and the impurity concentration of the relatively low concentration semiconductor region is 1x10^1^6cm^-^3 or more and 1x10^1^5cm^-^3 or less. 2. The semiconductor device according to claim 1. 3.S made by laminating a semiconductor single crystal substrate on an insulator
When forming a semiconductor element on a substrate with an OI structure, after polishing the surface of the substrate after bonding, impurities are introduced from the surface by ion implantation and heat treatment is performed to form a semiconductor region or semi-conductor at a certain depth from the surface. A method of manufacturing a semiconductor device, characterized in that an insulating region is formed. 4. After forming a high concentration semiconductor region on the back surface of the semiconductor single crystal substrate before bonding, bonding a substrate having at least an insulating layer on the surface to the back surface of the substrate, polishing the surface, and then polishing the surface of the SOI substrate. Introducing impurities by ion implantation and heat treatment forms a semiconductor region of the same conductivity type as the high concentration semiconductor region but with a lower concentration than the high concentration semiconductor region at a certain depth from the surface so as to overlap with the high concentration semiconductor region. 4. The method of manufacturing a semiconductor device according to claim 3, wherein: