JPH03201538A - Manufacture of thin film transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a thin film transistor, and particularly relates to a method for manufacturing a thin film transistor (TFT: Th1n F).
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[Prior Art] There is a simple matrix type of liquid crystal display devices used in liquid crystal televisions and the like. However, the simple matrix type has limitations in achieving high contrast and high time-division driving. Therefore, an active matrix type has been developed in which a switch element and, if necessary, a capacitor element are added and integrated for each pixel at the matrix intersection of the scanning 1i pole and the signal electrode to improve display performance such as contrast and response. It is starting to be used. In particular, among three-terminal switch elements, those using thin film transistors (hereinafter abbreviated as TPT) can operate at low voltages, have excellent compatibility with C-MOS ICs, and are easy to use in peripheral circuits. Because they can be integrated on the same substrate, they are thought to become mainstream in the future, surpassing two-terminal nonlinear elements such as varistors and MIMs. In addition, the semiconductor material for TPT was previously only CdSe, but amorphous silicon (a-3i), polysilicon (
Materials such as p-8i) are also being used.

The p-3i type T'FT not only provides fast response switching characteristics, but also allows peripheral circuits such as drive circuit elements to be
Although it is easy to integrally integrate such a peripheral circuit on the surface of a T matrix substrate, in the case of an a-3i type TPT, it is difficult to integrally integrate such peripheral circuits. However, a-3i type TPT
In the case of , the internal resistance when the switch is OFF is high and the dark current l0FF is relatively small, so there is an advantage that a capacitor for accumulating signal charge, which is generally required in the case of a p-3i TPT, is not required. .

Furthermore, four basic structures of TPT are known: a staggered type and an inverted staggered type in which the laminated structure is reversed, and a coplanar type and an inverted staggered type in which the laminated structure is reversed.

By the way, reduction of TOFF in thin film transistors,
There is a report that making the semiconductor layer ultra-thin is effective for stabilization (T) (E 21st Conference
ce on 5olid 5tate Dev
ices and MATERIALS, 1989
(See Proceedings A-6-2 (P97-100)).

Ion implantation is generally used as a method for forming the source and drain of such thin film transistors. However, ion implantation equipment is expensive and has a low throughput, making it unsuitable for mass production of devices on large substrates.

Therefore, as a conventional method for forming the source and drain of this type of coplanar thin film transistor, for example, as shown in FIG.
As shown in A) to (F), methods using a deposited layer doped with impurities are known.

In FIG. 2(A), 1 is a glass substrate, and on the glass substrate 1, first, a semiconductor layer 2 made of non-doped amorphous silicon (j-3i) which will become an active layer and has a thickness of, for example, 1500 Å is formed on the glass substrate 1 by a CVD method or the like. accumulate. Next, as shown in FIG. 2(B), the semiconductor layer 2 is doped with phosphorus (P) or arsenic (As) by sputtering or the like.
By forming a film of amorphous silicon (n+a-3i)3 and patterning it using photolithography,
N+ regions 4.5 for the source and drain are formed (see FIG. 2(C)).

Next, as shown in FIG. 2(D), amorphous silicon (a-S
The semiconductor layer 2 made of t) is made of polysilicon (p-3i). By using polysilicon, the field effect electron mobility μ can be increased and switching characteristics with fast response speed can be obtained.

Next, as shown in FIG. 2(E), for example, plasma C
A gate insulating layer 7 made of silicon nitride (SiNx) is patterned by a VD method.

Next, as shown in FIG. 2(F), by sputtering,
For example, conductor layers made of AQ are stacked L (1 layer) and patterned to form a source electrode 8, a drain electrode 9 and a gate electrode 1.
Complete by forming 0.

[Problems to be Solved by the Invention] However, in such a conventional thin film transistor, when forming the 09 region 4°5 of the source and drain, the processing selectivity with respect to the underlying i-31 semiconductor layer 2 is insufficient. This makes it virtually impossible to make the semiconductor layer 2 ultra-thin, and it is currently difficult to manufacture a Cobranar thin film transistor with an ultra-thin semiconductor layer without using ion implantation. be.

In other words, polysilicon that forms the semiconductor layer 2 generally has the characteristics of low bulk resistance and high conductivity, and although there is no problem when current is passed through it, leakage current flows even when it is not desired to flow current. It ends up. If such leakage current increases, when used in a liquid crystal display device, flicker will increase and power consumption will also increase. Therefore, it is necessary to make the semiconductor layer 2 as thin as possible in order to improve the characteristic of suppressing leakage current, but in the conventional structure, the semiconductor layer 2 and the n' regions 4 and 5 are impurity (
The only difference is whether or not they are doped with P, As, etc.), and the materials are almost the same. Therefore, during manufacturing, when patterning the n1 region 4°5 (
The semiconductor layer 2 is also removed to some extent (see FIG. 2(C)).
Oversex). In this case, n+ regions 4, 5
If the semiconductor layer 2 is not patterned reliably, leakage will occur immediately, so it is necessary to increase the thickness of the semiconductor layer 2 in advance.

From the above, the semiconductor layer 2 of coplanar TPT
It is difficult to realize ultra-thin films, and there is a need for thin-film transistors that can make semiconductor layers ultra-thin without using ion implantation.

An object of the present invention is to provide a method for manufacturing a thin film transistor in which a semiconductor layer is made ultra-thin without using ion implantation.

[Means for Solving the Problems] A method for manufacturing a thin film transistor according to the present invention includes the steps of: forming a semiconductor layer serving as an active layer on an insulating substrate; forming a source region and a drain region in the semiconductor layer by plasma doping and laser annealing;
The method includes the steps of removing the doping mask and then forming a gate insulating layer, source, drain, and gate electrodes.

[Function] According to the above-described means, since an etching process is not used when forming the source region and the drain region, the semiconductor layer is not over-etched, and the thin layer is thickened in advance in consideration of over-etching. There is no need to keep it. Also,
Since the source and drain regions are formed by plasma doping and laser annealing, it is possible to make the semiconductor layer ultra-thin without using ion implantation, which is expensive and has low throughput. Able to achieve purpose.

[Example] Hereinafter, the present invention will be explained based on the drawings.

FIG. 1 shows an embodiment of a method for manufacturing a coplanar thin film transistor according to the present invention.

In this embodiment, a film of 1-3i is formed on a glass substrate 11 by cVD or the like and has a thickness of, for example, 1.

Depositing an ultra-thin semiconductor layer 12 (FIG. 1(A))
reference). Next, as shown in FIG. 1(B), silicon nitride (S i Nx) is formed by, for example, plasma CVD.
An insulating layer consisting of is deposited and patterned to form a doping mask 13.

Next, as shown in FIG. 1(C), a doping mask 1 is formed.
Dopant plasma 1 is applied to the semiconductor layer 12 using 3 as a mask.
4. Plasma doping is performed.

Here, plasma doping includes, for example, H, diluted PH
, or BOH1, thereby implanting phosphorus (P) or boron (B) into the semiconductor layer 12 other than the masked areas.

Next, as shown in FIG. 1(D), by laser annealing using a laser beam 15 using an XeCQ excimer laser (λ=308 mm), the regions other than those masked become n+ regions 16° 17 of the source and drain.

Next, as shown in FIG. 1(E), a doping mask 1 is formed.
Thereafter, as shown in FIG. 1F, a gate insulating layer 18 made of silicon nitride (SiNx) is deposited and patterned by, for example, plasma CVD.

Next, as shown in FIG. 1(G), by sputtering,
For example, a conductor layer made of AQ is deposited and patterned to form a source 11 pole 19, a drain electrode 20, and a gate electrode 21, thereby completing the process.

Si in each step of FIG. 1 (B), (E) and (F) above
If patterning of Nx is performed using a hydrofluoric acid-based wet etchant, a sufficient selection ratio with respect to the underlying semiconductor 512 can be obtained.

As described above, in this embodiment, the semiconductor layer 12 is masked with the doping mask 13, impurities are implanted by plasma doping, and then laser annealing is performed to form n+ regions 16 and 17 in the areas other than the masked areas. Therefore, the semiconductor layer 17 is approximately 150 times thicker than the conventional one.
It is now possible to reduce the thickness by one order of magnitude from OA to about 100, and it is possible to manufacture a coplanar thin film transistor with an ultra-thin semiconductor layer without using ion implantation.

Note that the semiconductor layer 12 and the insulating layer 18 in the above embodiments,
Gate l! The material of the pole 21 and the like is merely an example, and it goes without saying that other materials having the same or similar properties can be used.

[Effects of the Invention] In this invention, the source and drain regions are formed by laser annealing after plasma doping, so there is no need to increase the film thickness in advance in preparation for overetching, and the semiconductor layer can be made ultra-thin. This has the effect of reducing and stabilizing Iorr and improving the characteristics of the coplanar thin film transistor. Also,
Since it can be realized without using ion implantation, it is possible to improve cost and throughput, and it is also advantageous for mass production of large substrates.

[Brief explanation of drawings]

FIGS. 1(A) to (G) are cross-sectional views showing an example of the method for manufacturing a coplanar thin film transistor according to the present invention in the order of steps, and FIGS. 2(A) to (F) are conventional manufacturing methods for a coplanar thin film transistor. FIG. 1 is a cross-sectional view showing an example of a method in the order of steps. 11... Glass substrate, ]2... Semiconductor layer, ]2
a...Channel part, J3...Doping mask, 14...Dopant plasma, 15...Laser beam, 16; 17...N+ region 18...
Gate insulating layer, 19...source electrode, 2o...
Drain electrode, 2I...gate electrode.

Claims (1)

[Claims] forming a semiconductor layer on an insulating substrate; forming a doping mask on a channel portion of the semiconductor layer; forming a source region and a drain region in the semiconductor layer by plasma doping and laser annealing; and the doping mask. 1. A method for manufacturing a thin film transistor, comprising the steps of: removing a gate insulating layer, and forming a source, drain, and gate electrode.