JPH03203089A - Pseudo static RAM reset circuit - Google Patents

Abstract

PURPOSE:To prevent the breakdown of storage contents even if the malfunction of a RAM occurs by fixing timing to execute actually resetting at time after the lapse of time equivalent to nearly one clock just after a refresh signal is turned ON, at whatever timing a reset signal turned ON. CONSTITUTION:A clock signal 2 delayed a little in its phase later than the clock signal 1 by a resistor R and a capacitor C is inputted to the tirgger terminal T of an SR flip flop 5 through a clock signal line 1a, and the refresh signal REF00 is inputted to a data terminal D through a refresh signal line 2a, and a result, a refresh acknowledge signal RAKO is outputted from an output terminal Q. This signal is turned OFF (low level) immediately after the signal REF00 is turned ON (low level) (after the lapse of the time equivalent to phase difference phi), and it is turned ON (high level) after the time equivalent to one clock of the signal 2 elapses from this moment.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a reset circuit for pseudo-static RAM in devices such as computers that require memory backup.

2. Description of the Related Art Generally, devices such as POS systems or computers are equipped with a pseudo-static RAM as a means for storing various data.

This pseudo-static RA, M needs to be refreshed at regular intervals if its storage contents are to be retained. For this reason, devices that require memory backup are provided with a refresh circuit and a reset circuit.

Pseudo-static RAM usually performs refreshing based on a refresh signal from a refresh circuit.

In addition, when the device is powered off, the pseudo-static RAM
The device shifts to self-refresh mode based on a reset signal from the reset circuit and continues refreshing.

An example of such conventional equipment will be explained based on FIGS. 3 and 4. This device, as shown in FIG.
The UI connects to the refresh circuit 2 via the clock signal line 1a.
It is also connected to one input terminal of the AND circuit 3 via the reset signal line ]b. However, the refresh circuit 2 divides the frequency of the clock signal from the CPUI to generate a refresh signal.

The refresh circuit 2 )111 is connected to the other input terminal of the AND circuit 3 via the refresh signal line 2a. Furthermore, the output terminal of the AND circuit 3 is connected to a pseudo-static RAM 4 via a reset/refresh signal line 3a.

In such a configuration, as shown in FIG.
The refresh circuit 2 is connected to the CP via the clock signal line 1a.
Clock signal 1 is input from the UI. The refresh circuit 2 divides the frequency of the input clock signal l to form a refresh signal REFOO, and outputs this to the AND circuit 3 via the refresh signal line 2a.

On the other hand, the CPU 1, which has received a reset command from the outside, outputs a reset signal RESO to the AND circuit 3 via the reset signal line 1b.

Furthermore, the AND circuit 3 receives the input refresh signal R.
Calculate the AND of EFOO and the reset signal RESO,
The reset/refresh signal REF that is the calculation result
O is output to the pseudo static RAM 4 via the reset/refresh signal line 3a.

Then, the pseudo static RAM 4 receives a reset signal R.
Refresh and self-refresh operations are performed based on ESO and refresh signal REFO. That is,
A refresh signal REF is generated when the refresh terminal of the PS-RAM, that is, the refresh signal line 2a of the refresh circuit 2 divides the frequency of the CPU clock.
If OO is at a low level for 180 μs or more, a refresh address is automatically generated internally in the RAM and refreshed. Also, when the refresh terminal of PS-RAM is in the Low state for 8 μs or more, R
AM's built-in refresh timer starts and refreshes internally at a fixed cycle.

Problems to be Solved by the Invention Since the timing at which the refresh signal REFOO turns on and the timing at which the reset signal RESO turns on are asynchronous, when the reset signal RESO turns on immediately after the refresh signal REFOO turns on, In other words, a reset may be executed immediately after the pseudo-static RAM 4 starts refreshing, and at this time, a pulse A is generated in the reset/refresh signal REFO, and this pulse A causes the pseudo-static RAM to malfunction, causing the stored contents to be changed. The problem is that it gets destroyed.

Means for Solving the Problems A CPtJ, a refresh circuit that forms a refresh signal from a clock signal from the CPtJ, and the CPtJ.
When the reset signal from U is turned on at an arbitrary timing, the reset signal is turned on after a time period corresponding to approximately 1 clock of the clock signal from the CPU has elapsed from immediately after the refresh signal from the refresh circuit turned on. a reset timing synchronization circuit that resets the timing of the reset timing synchronization circuit; and a reset timing synchronization circuit that performs writing and reading of information by the CPU, refreshes the memory contents based on a refresh signal from the refresh circuit, and performs a reset from the reset timing synchronization circuit. It consists of a pseudo-static RAM that performs reset based on signals.

Immediately after the refresh signal from the refresh circuit turns on and the pseudo-static RAM starts refreshing, the reset signal turns on and reset is executed after a period of time equivalent to about 1 clock of the CPU has elapsed. Even if the reset signal from the CPU is turned on immediately after the refresh signal from the circuit is turned on, a pulse will not be generated in the refresh signal, and as a result, pseudo-static R
There is no possibility that the AM malfunctions and the memory contents are destroyed.

Embodiment An embodiment of the present invention will be explained based on FIGS. 1 and 2. However, the same reference numerals are used for the same parts as those explained in FIGS. 3 and 4, and the explanation thereof will be omitted. This device, as shown in FIG.
A clock signal line 1a is connected to a capacitor C to which a voltage of 5V is applied and one end is grounded, and one end of the clock signal line 1a is connected to the clock signal line 1a.
The other end is connected to the trigger terminal T of the SR flip-flop 5. A refresh signal line 2a is connected to the data terminal of this SR flip-flop 5, and a voltage of +5V is applied to the set terminal S and reset terminal R. Further, the output terminal Q of this SR flip-flop 5 is connected to the trigger terminal T of the D latch IC 6 via the refresh ack signal line 5a,
A reset signal line 1b is connected to the data terminal of C6, and its output terminal Q is connected to one input terminal of the AND circuit 3 via a reset signal line 6a. The other input terminal of the AND circuit 3 is connected to a refresh signal line 2a drawn out from the refresh signal line 2a.

However, the reset timing synchronization circuit includes the resistor R, the capacitor C, and the SR flip-flops 5 and 011.
It is formed by the D latch IC6.

In such a configuration, as shown in FIG. 2, the trigger terminal T of the SR flip-flop 5 receives a signal whose phase is slightly delayed from the clock signal 1 due to the resistor R and the capacitor C.
(phase difference is ψ) Clock signal 2 is connected to clock signal line 1
The refresh signal REFOO is input to the data terminal via the refresh signal line 2a, and as a result, the refresh signal RAKO is output from the output terminal Q. This refresh ack signal RAKO is the refresh signal REFO.
Immediately after O turns on (low level) (after a time corresponding to the phase difference φ has elapsed), it turns off (low level),
After a time corresponding to one clock of clock signal 2 has elapsed from this moment, it becomes on (High level).

Then, the D latch I'C6 uses the refresh ack signal RAKO inputted to the trigger terminal T via the refresh ack signal line 5a as a trigger signal, and uses the reset signal line 1
Reset signal RE inputted to data terminal T via b
A reset signal RES that uses SOO as input data and resets the timing at which the reset signal RESOO from the output terminal Q turns on (Low level) to the timing at which the refresh ack signal RAKO turns on (High level).
Outputs O.

Furthermore, the AND circuit 3 receives a reset signal RESO manually inputted via the reset signal line 6a and a refresh signal RESO inputted via the refresh signal line 2a.
The reset signal RESOO is turned on at any timing, such as calculating the AND with OO and outputting the calculated result reset/refresh signal REFO to the pseudo static RAM 4 via the reset/refresh signal line 3a. Also, the timing at which the reset signal RESO turns on, that is, the timing at which the reset is actually executed, is fixed after a period of time equivalent to approximately one clock (1 clock signal) has elapsed from immediately after the refresh signal REFOO was turned on. . As a result, immediately after the refresh signal REFOO is turned on, the reset signal RE
There is no longer a pulse generated in the reset/refresh signal REFO when SOO is turned on.
As a result, there is no possibility that the pseudo-static RAM 4 malfunctions and the stored contents are destroyed.

Effects of the Invention As described above, the present invention includes a CPU, a refresh circuit that forms a refresh signal from a clock signal from the CPU, and a refresh circuit that generates a refresh signal from the refresh circuit when a reset signal from the CPU is turned on at an arbitrary timing. Immediately after the refresh signal of the CPU is turned on, the CPU
a reset timing synchronization circuit that resets the timing at which the reset signal is turned on after a time corresponding to approximately 1 clock of the clock signal from the CPU; Since the pseudo static RAM is configured to refresh its memory contents based on the refresh signal from the reset timing synchronization circuit and reset based on the reset signal from the reset timing synchronization circuit, the pseudo static RAM is refreshed when the refresh signal from the refresh circuit is turned on. The reset signal is turned on and the reset is executed after a period of time equivalent to approximately one CPtJ clock has elapsed since the start of the CPU. Even when the signal is turned on, no pulse is generated in the refresh signal, and as a result, the built-in refresh circuit of the pseudo-static RAM will not malfunction and the stored contents will not be destroyed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart of various signals during its operation, FIG. 3 is a block diagram showing an example of a conventional pseudo-static RAM reset circuit, and FIG. The figure is a timing chart of various signals during the operation. 1... CPIJ, 2... Refresh circuit, 4...
・Pseudo-static RAM 4. 1.

Claims (1)

[Claims] A CPU, a refresh circuit that forms a refresh signal from a clock signal from the CPU, and when a reset signal from the CPU turns on at an arbitrary timing, immediately after the refresh signal from the refresh circuit turns on, Approximately 1 of the clock signals from the CPU
A reset timing synchronization circuit resets the timing at which the reset signal is turned on after a time corresponding to the clock has elapsed, and the CPU writes and reads information, and the memory content is adjusted based on the refresh signal from the refresh circuit. 1. A reset circuit for a pseudo-static RAM, comprising a pseudo-static RAM that performs refresh and reset based on a reset signal from the reset timing synchronization circuit.