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JPH0321139A - signal processing device - Google Patents

signal processing device

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Publication number
JPH0321139A
JPH0321139A JP15603589A JP15603589A JPH0321139A JP H0321139 A JPH0321139 A JP H0321139A JP 15603589 A JP15603589 A JP 15603589A JP 15603589 A JP15603589 A JP 15603589A JP H0321139 A JPH0321139 A JP H0321139A
Authority
JP
Japan
Prior art keywords
section
signal
voltage
pulse
input section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15603589A
Other languages
Japanese (ja)
Inventor
Toshihiko Sasai
敏彦 笹井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Lighting and Technology Corp
Original Assignee
Toshiba Lighting and Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Lighting and Technology Corp filed Critical Toshiba Lighting and Technology Corp
Priority to JP15603589A priority Critical patent/JPH0321139A/en
Publication of JPH0321139A publication Critical patent/JPH0321139A/en
Pending legal-status Critical Current

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  • Remote Monitoring And Control Of Power-Distribution Networks (AREA)
  • Dc Digital Transmission (AREA)
  • Selective Calling Equipment (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、異なる電圧値の電圧信号を電源,制御信号と
して利用する信号処理装置に関ずる。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a signal processing device that utilizes voltage signals of different voltage values as power supply and control signals.

(従来の技術) 従来、この様な信号処理装置として、第12図に示すよ
うな回路構或のものもあった。このものは、時分割ざれ
た複極パルスを中央処理装置から2線伝送線を通じて、
パルス入力部1で受信し、このパルスをダイオートブリ
ツヂ3aで整流し、抵抗3c,3d.}−ランジ.スタ
3e,ツエナダイオード3fおよび平滑コンデンザ3g
からなる安定化電源回路3bによって高電圧部分をカツ
1〜して、一定の電圧を電源入力部信号入力部,制御信
号出力部を有する制御部に与えるとともに、パルス入力
部1とグランド間に過電流防止抵抗51,ツエナダイオ
ード52を直列接続し、抵抗51,ツエナダイオード5
2の中央を制御部8の信号入力部に接続して、ツエナダ
イオード52の設定電圧値を複極パルスのプラスの値程
度とすることで、複極パルスのプラス値のときのみ信号
入力部6に信号入力がないようにして、パルスの判別を
行い、これに基づき制御出力部7から負荷等を制御する
制御信号を出力するものであった。
(Prior Art) Conventionally, as such a signal processing device, there has been one having a circuit structure as shown in FIG. This device transmits time-divided bipolar pulses from the central processing unit through a two-wire transmission line.
The pulse is received by the pulse input section 1, rectified by the diode bridge 3a, and connected to the resistors 3c, 3d. }-Lunge. Star 3e, Zener diode 3f and smooth capacitor 3g
The stabilized power supply circuit 3b cuts off the high voltage part 1 and supplies a constant voltage to a control section having a power supply input section, a signal input section, and a control signal output section. A current prevention resistor 51 and a Zener diode 52 are connected in series, and a resistor 51 and a Zener diode 5 are connected in series.
By connecting the center of 2 to the signal input section of the control section 8 and setting the set voltage value of the Zener diode 52 to about the positive value of the bipolar pulse, the signal input section 6 is connected only when the positive value of the bipolar pulse is detected. The pulse is determined without receiving any signal input, and based on this, the control output section 7 outputs a control signal for controlling the load and the like.

(発明が解決しようとする課題) このような構造のものであると、判別部50にツエナダ
イオードが必須である。しかし、ツエナダイオードは、
品質的バラツキすなわち、ツエナ電圧のバラツキが多い
。つまり、受信電圧がバラックために、受信精度を高く
することが課題となっていた。
(Problems to be Solved by the Invention) With such a structure, a Zener diode is essential in the discrimination section 50. However, the zener diode
There are many variations in quality, that is, variations in Zener voltage. In other words, since the received voltage is variable, it has been a challenge to improve the reception accuracy.

また、近年、各種電気回路は、集積回路化がどこまで可
能かが技術課題となっているか、このものでは、せいぜ
い、制御部7の部分のみが集積化できる程度であり、集
積化の限界があった。
In addition, in recent years, the extent to which it is possible to integrate various electric circuits has become a technical issue, and in this case, at most, only the control section 7 can be integrated, and there is a limit to integration. Ta.

本発明は、以上の課題に鑑みてなされたものであり、そ
の目的は、簡単な構戒で、精度良くパルス信号の判別が
行え−、しかも、従来に比へてより集積回路化の可能な
信号処理装置を提供することにある。
The present invention has been made in view of the above-mentioned problems, and its purpose is to enable accurate discrimination of pulse signals with a simple structure, and also to enable more integrated circuits than before. An object of the present invention is to provide a signal processing device.

[発明の構戒] (課題を解決するための手段) 本発明の信号処理装置構戒を第1図を参照して説明する
。本発明の信号処理装置は、パルス送出側から伝送線等
パルス信号線2を通して送られて<るovと+χv,o
vと−χv.−χv.=十χV等の異なる電圧値が経時
的に変化するパルス信号が入力されるパルス入力部1,
このパルス入力部]の出力電圧を整流,平滑する定電圧
部3,電源入力部5と信号入力部6と制御信号出力部7
とを有する制御部8およびパルス入力部1の出力側と定
電圧部3の出力側との間に、パルス入力部1側4にカソ
ードを接続したダイオード12と定電圧部3の出力側9
に接続したプルアップ抵抗13とを有し、ダイオード1
2とプルアップ抵抗13との中点14を制御部8の信号
入力部6に接続した判別部11とからなり、制御部8の
電源入力部5には、定電3 圧部3の出力電圧を入力したことを特徴とするものであ
る。パルス送出側は、信号処理装置と伝送線で接続され
て遠隔地にあるものの他、信号処理装置と一体となって
いるものでもよい。パルス信号は、判別部11にて2値
の信号判別ができる信号であればよく、すなわち、検知
したい信号をそれ以外の信号との電圧差の中間値に定電
圧部3の出力電圧値がなるような、パルス信号であれば
よい。
[Structure of the Invention] (Means for Solving the Problems) The structure of the signal processing device of the present invention will be explained with reference to FIG. The signal processing device of the present invention is configured such that <ov and +χv, o are sent from the pulse sending side through a pulse signal line 2 such as a transmission line.
v and −χv. −χv. a pulse input section 1 into which a pulse signal in which different voltage values such as =10χV change over time is input;
A constant voltage section 3 that rectifies and smoothes the output voltage of this pulse input section], a power input section 5, a signal input section 6, and a control signal output section 7
A diode 12 having a cathode connected to the pulse input section 1 side 4 and an output side 9 of the constant voltage section 3 are connected between the output side of the control section 8 and the pulse input section 1 and the output side of the constant voltage section 3.
and a pull-up resistor 13 connected to the diode 1.
2 and a pull-up resistor 13 are connected to the signal input section 6 of the control section 8. It is characterized by inputting the following information. The pulse sending side may be connected to the signal processing device via a transmission line and located at a remote location, or may be integrated with the signal processing device. The pulse signal may be any signal that allows the discriminator 11 to discriminate between binary signals, that is, the output voltage value of the constant voltage section 3 will be the intermediate value of the voltage difference between the signal to be detected and other signals. Any pulse signal may be used.

(作用) 本発明の作用を説明する。(effect) The operation of the present invention will be explained.

バルス送出側からパルス入力部1に入力されたパルス信
号は、まず、定電圧部3によって整流,平滑され直流電
圧として出力される(この時の出力電圧値は、パルス入
力部に入力されるパルス信号の高い電圧値と低い(マイ
ナスも含む〉電圧値の中間値となる。)。この直流電源
は、電源入力部5に入力され制御部8の電源となる。ま
た、判別部11のプルアップ抵抗13のー@9にも常に
上記直流電圧が印加される。ここで、パルス入力部1側
4の電圧は、経時的に変化するため、直流電圧4 よりも高い時間と低い時間とが発生するが、高い時間に
は、ダイオード12があるためパルス入力部側は高電圧
にもかかわらずプルアップ抵抗13に電流は流れない。
A pulse signal input to the pulse input section 1 from the pulse sending side is first rectified and smoothed by the constant voltage section 3 and output as a DC voltage (the output voltage value at this time is equal to the pulse signal input to the pulse input section). This is the intermediate value between the high voltage value and the low (including negative) voltage value of the signal. This DC power is input to the power input section 5 and becomes the power source for the control section 8. Also, the pull-up of the discriminating section 11 The above DC voltage is always applied to -@9 of the resistor 13. Here, since the voltage on the pulse input section 1 side 4 changes over time, there are times when it is higher and times when it is lower than the DC voltage 4. However, at high times, no current flows through the pull-up resistor 13 despite the high voltage on the pulse input side because of the presence of the diode 12.

従って、中点14の電圧値は、上記直流電圧と同じ電位
となり、信号入力部6に直流電圧が印加される。
Therefore, the voltage value at the midpoint 14 is the same potential as the DC voltage, and the DC voltage is applied to the signal input section 6.

直流電圧よりも低い時間には、ダイオード12は電流方
向に対して順方向であるため、電流は9,13, 14
, 12, 4, 1 . 2 (第1図付号〉を通し
て流れ、従って信号入力部6には電圧は印加されない。
At times when the voltage is lower than the DC voltage, the diode 12 is in the forward direction with respect to the current direction, so the current is 9, 13, 14.
, 12, 4, 1. 2 (numbered in FIG. 1), and therefore no voltage is applied to the signal input section 6.

このように信号入力部6に対する電圧値の差によって、
制御部8では、パルス信号をデータ処理し、定電圧部3
出力を電源として、負荷側へ制御信号出力部から制御信
号を出力する。
In this way, due to the difference in voltage value for the signal input section 6,
The control section 8 processes the pulse signal as data, and the constant voltage section 3
Using the output as a power source, a control signal is output from the control signal output section to the load side.

(実施例) 本発明の第1の実施例を第2図ないし第9図を参照して
説明する。第3図は、従来技術第12図と比して、判別
部11が異なるだけであり、その他の部分は同様である
ため説明を省略する第1の実施例は、負荷制御装置であ
り、中央処理装置21,操作スイッチ23,端末器22
a〜22nが、2線の伝送線2で接続され、各端末器2
28〜22nにはそれぞれ照明などの負荷24a〜24
dが接続されている。各端末器22a〜22n,操作ス
イッチ23は、それぞれ固有のアトレスを持ち、中央処
理装置から伝送信号(第11図)のAのパルス群(スタ
ートC,モードD,アドレスE,データ「,チェックザ
ムG)を受信して(第4図(ア)〉,自己のアドレスで
あれば(第4図(イ)〉,データ[を判別し(第4図(
工)〉,負荷(例えばリレー)へ制御信号を出力する(
第4図(オ))。なお、モートDは4ビットのパルス信
号で、端末器を制御(する,しない)端末器から制御デ
ータを(送る,送らない)の組み合せ4モードがあり、
制御データを送るモードの場合は、指定された端末器は
、データを乗せて、中央処理装置へ返送する(以上制御
部8の動作〉 本実施例の要部具体横或を第10図に示す。第3図と共
通部分の説明は省略づ−る。
(Example) A first example of the present invention will be described with reference to FIGS. 2 to 9. The first embodiment shown in FIG. 3, which differs from the prior art shown in FIG. 12 only in the discriminating section 11 and other parts are the same and will not be described here, is a load control device, and the central Processing device 21, operation switch 23, terminal device 22
a to 22n are connected by a two-wire transmission line 2, and each terminal device 2
28 to 22n have loads 24a to 24 such as lighting, respectively.
d is connected. Each of the terminals 22a to 22n and the operation switch 23 have a unique address, and the pulse group A (start C, mode D, address E, data ", check sum") of the transmission signal (FIG. 11) from the central processing unit. G) is received (Fig. 4 (A)), if it is the own address (Fig. 4 (B)), then the data [ is determined (Fig. 4 (A)).
outputs a control signal to the load (e.g. relay)
Figure 4 (e)). In addition, mode D is a 4-bit pulse signal, and there are 4 combinations of modes for controlling the terminal (doing or not) and sending control data from the terminal (sending, not sending).
In the mode of sending control data, the designated terminal device carries the data and sends it back to the central processing unit (the above is the operation of the control unit 8). .Explanation of parts common to FIG. 3 will be omitted.

31は、上記端末器から中央処理装置へデータを返送す
る際に駆動させる返送信号回路であり、0,1信号を制
御部8の端子50の出力に応じて、ダイオードブリツヂ
3aの両端を短絡(する,しない)で表現し、電流値の
変化として、第11図のBに組入れ中央処理装置に識別
させる。
Reference numeral 31 denotes a return signal circuit that is driven when data is returned from the terminal device to the central processing unit, and sends 0 and 1 signals to both ends of the diode bridge 3a according to the output of the terminal 50 of the control section 8. This is expressed as a short circuit (on or off), and is incorporated into B in FIG. 11 as a change in current value to be identified by the central processing unit.

32, 33, 34., 35はそれぞれリセット回
路,発振回路,アドレス設定用デツプスイッチ,ドライ
ブトランジスタである。
32, 33, 34. , 35 are a reset circuit, an oscillation circuit, an address setting depth switch, and a drive transistor, respectively.

制御部8の制御信号出力は、図示にように、8ビット出
力で、内4ビットを前記ドライブトランジスタ35へ送
出し、内4ビットを制御部8に帰還させて返送データと
してあつかう。
As shown in the figure, the control signal output of the control section 8 is an 8-bit output, of which 4 bits are sent to the drive transistor 35 and the 4 bits are fed back to the control section 8 to be treated as return data.

42a〜42dおよび41 a 〜.41 dて、4個
のリレ回路を形或してあり、41a〜41dには、電源
36,ダイオードブリツヂ37,平滑コンデンサ38か
ら電源か供給され、42a〜42bには、電源43およ
び負荷24a〜24dか、それぞれ接続され、ドライブ
トランジスタ35からの4ビツ1への信号によって各負
荷24a〜24dか、所望にON,OFFされる。
42a-42d and 41a-. 41d has four relay circuits, 41a to 41d are supplied with power from a power supply 36, a diode bridge 37, and a smoothing capacitor 38, and 42a to 42b are supplied with power from a power supply 43 and a load. The loads 24a to 24d are connected to each other, and each load 24a to 24d is turned on or off as desired by a signal from the drive transistor 35 to 4 bits 1.

本実施例の判別部11の作用について第3図ないし第9
図を参照して説明する。
3 to 9 regarding the operation of the discriminator 11 of this embodiment.
This will be explained with reference to the figures.

第5図は、第3図の■,■間の電圧を■をOVとしてみ
た波形,第6図は、第3図の■,■間の電圧を■をOV
としてみた波形,第7図は、第3図の■,■間の電圧を
■をOVとしてみた波形,第8図は、第3図の■,■(
■)間の電圧を■をOVとしてみた波形,第9図は、第
3図の■,■間の電圧を■をOVとしてみた波形,すな
わち、信号入力部6への入力波形である。なお、全て横
軸は時間,縦軸は電圧,各図の時間割区間てaの部分は
同一時間帯を示す(bの部分も同様)。また、第5図な
いし第7図にあいて0.6〜1.○Vの差は、ダイオー
ドブリ.ツヂによる電圧降下であり、実際には第8図の
波形も24V(点線)よりも0.6〜1.0低い(VD
Dを除く)。
Figure 5 shows the waveform of the voltage between ■ and ■ in Figure 3 with ■ being OV, and Figure 6 shows the voltage between ■ and ■ in Figure 3 with ■ being OV.
Figure 7 shows the waveform when the voltage between ■ and ■ in Figure 3 is taken as OV, and Figure 8 shows the waveform when the voltage between ■ and ■ in Figure 3 is taken as OV.
FIG. 9 shows a waveform of the voltage between (1) and (2) in FIG. In all cases, the horizontal axis is time, the vertical axis is voltage, and in the timetable sections in each figure, the portion a indicates the same time zone (the same applies to the portion b). Also, in Figures 5 to 7, 0.6 to 1. ○The difference in V is due to the diode voltage. This is a voltage drop due to voltage drop, and the waveform in Figure 8 is actually 0.6 to 1.0 lower than 24V (dotted line) (VD
(excluding D).

ます、■,■に複極パルス±24が入力され(第5図)
,ダイオードブリツヂ3aによって直流電圧出力となる
(第8図)、この直流電圧出力のピーク分を安定化電源
回路3bでカットして安定化された定電圧を得る(第8
図VDD)。判別部11によって、V DD= 5 V
を基準値としているので、本実施例では、第6図から、
時間aのときに、第9図に示すように+5V発生するか
ら信号入力部6へ電圧か印加される。
Then, a bipolar pulse of ±24 is input to ■ and ■ (Figure 5).
, a DC voltage is output by the diode bridge 3a (Fig. 8), and the peak portion of this DC voltage output is cut by the stabilized power supply circuit 3b to obtain a stabilized constant voltage (Fig. 8).
Figure VDD). The determination unit 11 determines that V DD = 5 V
is used as the reference value, so in this example, from FIG. 6,
At time a, +5V is generated as shown in FIG. 9, so a voltage is applied to the signal input section 6.

なあ、夕゛イオード12のカソード側を1aて゛なく1
bに接続した場合には、第7図のように第6図と逆の波
形となるから時間bのときに1−5発生するようになる
。この場合は、例えば制御部8の信号入力部6にインバ
ータ回路を設【ブればよい。
Hey, put the cathode side of diode 12 at 1 instead of 1a.
When connected to b, the waveform as shown in FIG. 7 is opposite to that in FIG. 6, so that 1-5 is generated at time b. In this case, for example, an inverter circuit may be provided in the signal input section 6 of the control section 8.

本実施例では、第10図に示すように模式的にプルアッ
プ抵抗を制御部(LSI)8外部に出しているが、実際
には、LSI内部に組込んでいるものである。
In this embodiment, as shown in FIG. 10, the pull-up resistor is schematically placed outside the control section (LSI) 8, but it is actually built into the LSI.

[発明の効果] 本発明の信号処理装置は、パルス入力部に入力される電
圧値の異なるパルスの判別を前記パルスを整流化した定
電圧部の出力電圧との比較で行う。
[Effects of the Invention] The signal processing device of the present invention discriminates between pulses having different voltage values input to the pulse input section by comparing the pulses with the output voltage of the constant voltage section which rectifies the pulses.

定電圧部の出力電圧値(は、整流化ざれてあり、パルス
入力部に入力される中間となるため、パルス判別が確実
となる。また、判別部としては、定電圧部出力側にプル
アップ抵抗,電圧入力部側に力ソードを接続したダイオ
ードを設け、プルアップ抵抗とダイオードの中間を、電
圧の有・無に基づいて制御出力の有・無を決定する制御
部の信号入力部に接続する簡単な構或で足りるので、ダ
イオードに比べて高価なツエナダイオード等用いる必要
はなく安価な装置を提供できる。しかも、本発明は、ダ
イオードによって、パルス入力部からプルアップ抵抗に
直接電源か流れることがなく、制御部の電源電圧と同じ
定電圧部の電圧印加のみであるため、制御部を例えばI
C等の集積回路で構或する場合、プルアップ抵抗を集積
回路内に容易に取込めるので、装置に係わる製造,部品
コストの低減化を図ることができる。
The output voltage value of the constant voltage section (is rectified and becomes the intermediate input to the pulse input section, so pulse discrimination is reliable. Also, as a discrimination section, there is a pull-up on the constant voltage section output side. A diode with a power sword connected to the resistor and voltage input section is provided, and the intermediate point between the pull-up resistor and the diode is connected to the signal input section of the control section, which determines the presence/absence of the control output based on the presence/absence of voltage. Since a simple structure is sufficient, there is no need to use a Zener diode, etc., which is more expensive than a diode, and an inexpensive device can be provided. Since only the constant voltage section applies the same voltage as the power supply voltage of the control section, the control section can be
When the device is constructed using an integrated circuit such as C, the pull-up resistor can be easily incorporated into the integrated circuit, so manufacturing and component costs related to the device can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の基本構戊を一部ブロック化して示す図
,第2図は、本発明の一実施例の全体図,第3図は同上
の要部を示す回路図,第4図は同上の処理動作を示す流
れ図,第5ないし第9図はそれぞれ同上の信号波形を示
す図,第10図は、同上の要部を具体的に示す回路図,
第11図は同上に用いられるパルス信号波形を示す図,
第12図は従来装置の要部を示す回路図である。 1・・・パルス入力部, 3・・・定電圧部,5・・・
制御部, 6・・・信号入力部,7・・・制御信号出力
部, 8・・・制御部,11・・・判別部,12・・・
ダイオード,13・・・プルアップ抵抗。
Fig. 1 is a partial block diagram showing the basic structure of the present invention, Fig. 2 is an overall view of an embodiment of the present invention, Fig. 3 is a circuit diagram showing the main parts of the same, Fig. 4 is a flowchart showing the same processing operation as above, FIGS. 5 to 9 are diagrams showing signal waveforms as above, respectively, and FIG. 10 is a circuit diagram specifically showing the main parts of above,
Fig. 11 is a diagram showing the pulse signal waveform used in the above,
FIG. 12 is a circuit diagram showing the main parts of the conventional device. 1... Pulse input section, 3... Constant voltage section, 5...
Control unit, 6... Signal input unit, 7... Control signal output unit, 8... Control unit, 11... Discrimination unit, 12...
Diode, 13...Pull-up resistor.

Claims (1)

【特許請求の範囲】[Claims] (1)電圧値が経時的に異なるパルス信号が入力される
パルス入力部と; このパルス入力部からのパルス信号を整流、平滑する定
電圧部と; この定電圧部の出力を電源として入力される電源入力部
、信号入力部、および、信号入力部の入力電圧に基づい
て制御信号を出力する制御信号出力部を有した制御部と
; 上記パルス入力部および定電圧部の出力側間に介在し、
上記信号入力部へ上記パルス入力部に入力される電圧の
高低に応じて2値信号を出力する判別部と; を具備し、 上記判別部は、パルス入力部側がカソードとなるように
接続されたダイオードおよびこのダイオードよりも定電
圧部出力側に接続されたプルアップ抵抗からなり、上記
ダイオードおよびプルアップ抵抗の中点と上記信号入力
部とを接続したことを特徴とする信号処理装置。
(1) A pulse input section into which a pulse signal whose voltage value changes over time is input; A constant voltage section that rectifies and smoothes the pulse signal from this pulse input section; The output of this constant voltage section is input as a power source. a control section having a power input section, a signal input section, and a control signal output section that outputs a control signal based on the input voltage of the signal input section; interposed between the output side of the pulse input section and the constant voltage section; death,
a discriminator that outputs a binary signal to the signal input section according to the level of the voltage input to the pulse input section; and the discriminator is connected such that the pulse input section side becomes a cathode. 1. A signal processing device comprising a diode and a pull-up resistor connected to a constant voltage section output side of the diode, and a midpoint between the diode and the pull-up resistor connected to the signal input section.
JP15603589A 1989-06-19 1989-06-19 signal processing device Pending JPH0321139A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15603589A JPH0321139A (en) 1989-06-19 1989-06-19 signal processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15603589A JPH0321139A (en) 1989-06-19 1989-06-19 signal processing device

Publications (1)

Publication Number Publication Date
JPH0321139A true JPH0321139A (en) 1991-01-29

Family

ID=15618896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15603589A Pending JPH0321139A (en) 1989-06-19 1989-06-19 signal processing device

Country Status (1)

Country Link
JP (1) JPH0321139A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006157659A (en) * 2004-11-30 2006-06-15 Canon Inc Data carrier device and data communication method
JP2007172578A (en) * 2005-12-19 2007-07-05 Power Integrations Inc Method and apparatus to authenticate power supply

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006157659A (en) * 2004-11-30 2006-06-15 Canon Inc Data carrier device and data communication method
JP2007172578A (en) * 2005-12-19 2007-07-05 Power Integrations Inc Method and apparatus to authenticate power supply
US8499179B2 (en) 2005-12-19 2013-07-30 Power Integrations, Inc. Method and apparatus to authenticate a power supply

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