JPH03234125A - Error correction device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Industrial Application Field) The present invention relates to an error correction device for correcting errors in digital signals occurring in digital data communications, digital storage devices, and the like.

(Prior Art) In systems that handle digital data, error correction codes are widely used to improve the reliability of data that is degraded by noise or the like. Among several error correction codes, cyclic codes, especially BCH codes, have not only the commonly used random error correction ability but also a fairly powerful burst error correction ability, and are used in many systems. (Kinichi Tokiwa, Masao Kasahara, Toshihiko Namekawa; Burst error correction ability of r-cyclic codes 1. Journal of the Institute of Electrical Communication '83/10 Vol. J66-A No. 10) Selective random error correction and burst error correction A conventional error correction device that performs this function is configured as shown in FIG. 3, for example.

In the figure, a syndrome is calculated by a syndrome calculation circuit B1 into which a digital signal 101 is input, and this syndrome is applied to a random error estimation circuit 3 to estimate a random error pattern in the digital signal 101.

The syndrome is also given to the syndrome conversion circuit 5, and the remainder by the generating polynomial of the digital signal 101 is calculated. This remainder is output to the burst error estimation circuit 7, and the burst error pattern in the digital signal 101 is estimated.

On the other hand, the digital signal 101 delayed by the delay circuit 9 is
It is applied to EXOR (exclusive OR) gates 11.13, in which the error patterns estimated by each error estimation circuit 3.7 are corrected.

These error-corrected digital signals are input to delay circuits 15 and 17, respectively, and sent to switching circuit 19 after being delayed by one frame.

On the other hand, at the time when the final bit of the error-corrected digital signal is output from the EXOR gate 11.13,
Random error estimation circuit 3 or burst error estimation circuit 7
From there, a signal of the correction result is output to the output selection control circuit 21. Based on this correction result signal, the switching circuit 19
An output selection control signal 103 for controlling the output selection control circuit 21 is generated by the output selection control circuit 21 and output to one switching circuit.

According to this output selection control signal 103, one of the digital signals delayed by one frame is selected by the switching circuit 19.
selected and output.

In this way, the output selection control signal 103 is generated based on the correction result signal output from the random error estimation circuit 3 or the burst error estimation circuit 7. Furthermore, the signal resulting from this correction is output when the last bit of the digital signal whose error has been corrected is output from the EXOR gate 11.13.
This is the time when it is output from. Therefore, in order to select the output from the first bit to the last bit of the error-corrected digital signal in the switching circuit 19, delay circuits 15 and 17 are provided to delay the digital signal by one frame.

(Problem to be Solved by the Invention) As described above, in the conventional error correction device, it is necessary to provide a delay circuit that delays the digital signal in which the random error pattern and the burst error pattern have been corrected by one frame each. I had to. As a result, there are problems in that the error correction time becomes longer and the device becomes larger. A delay circuit is required to delay the signal by one frame (511 bits). If this delay circuit was constructed from static registers, about 7 gate delay circuits would be required.

Therefore, the present invention has been made in view of the above-mentioned conventional circumstances, and its purpose is to select the output before the first bit of the error-corrected digital signal is output from the EXOR gate. A control signal is generated to enable output selection without delaying the corrected digital signal. As a result, it is an object of the present invention to provide an error correction device that can shorten the error correction time and further reduce the size by eliminating the delay circuit.

[Structure of the Invention (Means for Solving the Problems)] In order to achieve the above object, the present invention corrects random errors in the input digital signal based on the syndrome of the input digital signal, and In an error correction device that corrects the burst error of this digital signal from the signal remainder and selectively outputs one of these corrected digital signals, one of the corrected digital signals to be output is corrected for the syndrome or the remainder. It is comprised of an output selection means for selecting based on the output.

(Operation) The present invention corrects random errors from the syndrome of an input digital signal. Also, burst errors are corrected from the remainder of the input digital signal. One of these corrected digital signals is selectively output based on the syndrome or remainder of the input digital signal.

(Example) Hereinafter, the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing one embodiment of an error correction device of the present invention.

As shown in the figure, the error correction apparatus of the present invention has a delay circuit 15.
17 has been deleted.

Also, components with the same reference numerals have the same functions.

The syndrome calculation circuit 1 receives a digital signal 101, calculates the syndrome of this digital signal 101,
This syndrome is output to the random error estimation circuit 3 and the syndrome conversion circuit 5. The syndrome calculation circuit 1 also outputs the calculated syndrome to the output selection control circuit 21.

The random error estimation circuit 3 estimates a random error pattern from the syndrome, and converts this random error pattern into E.
This is given to the XOR gate 11.

The syndrome conversion circuit 5 converts the syndrome calculated by the syndrome calculation circuit 1 into a remainder, and outputs this to the burst error estimation circuit 7.

The burst error estimation circuit 7 estimates a burst error pattern from the remainder and supplies this burst error pattern to the EXOR gate 13.

The delay circuit 9 receives the input digital signal 101, delays this signal 101, and then outputs it to the EXOR gates 11 and 13.

The EXOR gate 11 inputs the random error pattern and the delayed digital signal and corrects the random errors in the digital signal 101.

The EXOR gate 13 inputs the burst error pattern and the delayed digital signal, and corrects burst errors in the digital signal 101.

The switching circuit 19 receives the random error corrected digital signal and the burst error corrected digital signal, selects one of them based on the output selection control signal 103, and outputs the selected signal.

The output selection control circuit 21 receives the syndrome calculated by the syndrome calculation circuit 1 and generates the output selection control signal 103 based on this syndrome.
For example, when a (511,493) BCH code is used, the output selection control circuit 21 receives an 18-bit syndrome and generates a 1-bit output selection control signal 103. In this case, this output selection control circuit 21
is composed of a 256-bit ROM (not shown) and a single knob, and the ROM stores patterns corresponding to all 211' types of syndromes.

Further, the output selection control circuit 21 sends the generated output selection control signal 103 to the switching circuit 19.

One embodiment of the present invention is thus constructed, and the operation of this embodiment will now be described.

First, a digital signal 101 is input to the syndrome calculation circuit 1. At the same time, the digital signal 101 is also input to the delay circuit 9.

A syndrome is calculated from the digital signal 101 by the syndrome calculation circuit 1, and this syndrome is given to the random error estimation circuit 3.

The random error estimation circuit 3 given the syndrome estimates a random error pattern in the digital signal 101, and this error pattern is given to the EXOR gate 11.

Furthermore, the syndrome calculated by the syndrome calculation circuit 1 is also provided to the syndrome conversion circuit 5.

The syndrome conversion circuit 5 to which the syndrome is given converts the syndrome into a remainder, and this remainder is output to the burst error estimation circuit 7.

The burst error estimation circuit 7 estimates a burst error pattern in the digital signal 101 and applies this error pattern to the EXOR gate 13.

On the other hand, from the delay circuit 9 into which the digital signal 101 is input, a delayed digital signal is output to the EXOR gates 11 and 13.

EXOR gates 11 and 13 correct errors in the digital signal based on the error patterns estimated by the respective error estimation circuits 3 and 7 and the delayed digital signal. Furthermore, these error-corrected digital signals are sent to the switching circuit 19.

On the other hand, the syndrome calculated by the syndrome calculation circuit 1 is also output to the output selection control circuit 21. This syndrome is characterized by random error patterns and burst error patterns each time the error is estimated! The value has already been calculated before it is output from @3.7.

Output selection control circuit 2 with such a syndrome input
In step 1, this syndrome is associated with 218 patterns stored in the ROM. and,
A 1-bit output selection control signal 103 is generated based on a pattern corresponding to the syndrome.

This output selection control signal 103 is configured such that, for example, when its 1 bit is "0", a signal with a random error corrected is selected, and when it is 1'°, a signal with a burst error corrected is selected. It is given meaning.

Furthermore, the output selection control signal 103 generated in this way
is sent to the switching circuit 19.

In the switching circuit 19, one of the two error-corrected digital signals is selected and output according to the output selection control signal 103.

Next, the operation of the second embodiment of this invention will be explained.

FIG. 2 is a block diagram showing another embodiment of the error correction device of the present invention.

The error correction apparatus shown in FIG. 1 includes a remainder calculation circuit 23 and a remainder conversion circuit 25 in place of the syndrome calculation circuit 1 and the syndrome conversion circuit 5 in the configuration shown in FIG. Further, other components having the same reference numerals have the same functions.

The remainder calculation circuit 23 inputs the digital signal 101, calculates the remainder by the generator polynomial of this digital signal 101, and sends this remainder to the burst error estimation circuit 7 and the remainder conversion circuit 2.
5, and is output to the output selection control circuit 21.

The remainder conversion circuit 25 inputs the remainder calculated by the remainder calculation circuit 23, converts it into a syndrome, and outputs it to the random error estimation circuit 3.

The output selection control circuit 21 receives the remainder calculated by the remainder calculation circuit 23 and generates the output selection control signal 103 based on this remainder.

For example, when using the (511,493) BCH code,
The output selection control circuit 21 inputs the 18-bit remainder,
A 1-bit output selection control signal 103 is generated. In this case, this output selection control circuit 21 has a 256-bit ROM (not shown) 1 as in the first embodiment.
Consists of chips.

In the error correction device configured as described above, the digital signal 101 is first input to the remainder calculation circuit 23 and the delay circuit 9.

In the remainder calculation circuit 23, the remainder of the digital signal 101 is calculated, and this remainder is output to the burst error estimation circuit 7, the remainder conversion circuit 25, and the output selection control circuit 21.

The remainder is converted into a syndrome by the remainder conversion circuit 25 which inputs the remainder, and this syndrome is output to the random error estimation circuit 3.

The operations after the random error estimation circuit 3, the burst error estimation circuit 7, and the delay circuit 9 are performed in the same manner as in the first embodiment. As a result, respective digital signals with random and burst errors corrected are sent to the switching circuit 19.

On the other hand, the value of the remainder input to the output selection control circuit 21 has already been determined before the random error pattern and the burst error pattern are output from each error estimation circuit 3, 7.

In the output selection control circuit 21 which inputs such a remainder,
Similar to the first embodiment, this remainder is associated with the pattern stored in the ROM. Then, a 1-bit output selection control signal 103 is generated based on the pattern corresponding to the remainder.

Furthermore, the output selection control signal 103 generated in this way
is sent to the switching circuit 19 as in the first embodiment, and a digital signal selected according to this signal 103 is output from the switching circuit 19.

As described above, the output selection control circuit 21 generates the output selection control signal 103 that controls the switching circuit 19 directly from the syndrome or the remainder. Therefore, the switching circuit 19 can select the output from the first bit without delaying the error-corrected digital signal output from the EXOR gates 11.13.

[Effects of the Invention] As described above, with the error correction device according to the present invention, it is possible to select and output an error-corrected digital signal starting from the first bit without delay. This eliminates the need for a delay circuit for one frame, making it possible to downsize the device. Furthermore, it is possible to reduce the error correction time by about half.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the error correction device of the present invention, FIG. 2 is a block diagram showing another embodiment, and FIG. 3 is a block diagram showing an example of a conventional error correction device. It is. 1...Syndrome calculation circuit 23...Remainder calculation circuit 21...Output selection control circuit 19...Switching circuit 103...Output selection control signal

Claims (1)

[Scope of Claims] Random errors in the input digital signal are corrected from the syndrome of the input digital signal, and burst errors in the digital signal are corrected from the remainder of the input digital signal, and these corrected digital signals are corrected. An error correction device for selectively outputting one of the signals, further comprising an output selection means for selecting one of the corrected digital signals to be output based on the syndrome or the remainder.