JPH03230597A - Semiconductor device mounting structure - Google Patents
Semiconductor device mounting structureInfo
- Publication number
- JPH03230597A JPH03230597A JP2026590A JP2659090A JPH03230597A JP H03230597 A JPH03230597 A JP H03230597A JP 2026590 A JP2026590 A JP 2026590A JP 2659090 A JP2659090 A JP 2659090A JP H03230597 A JPH03230597 A JP H03230597A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- board
- mounting structure
- present
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Supply And Installment Of Electrical Components (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置の高密度実装構造に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-density packaging structure for semiconductor devices.
第４図は従来の半導体装置の実装状態を示す斜視図であ
る。図において、（１）は半導体装置、（２）は基板で
ある。基板（２）の表（８）および基板（２）の内部（
多層基板の場合）に導電物により配線および半導体付着
面を形成し、その基板（２）の表向に半導体装置（１）
を多数半田などにより装着し第５図のように多段に積層
して高密度実装していた。FIG. 4 is a perspective view showing the mounting state of a conventional semiconductor device. In the figure, (1) is a semiconductor device, and (2) is a substrate. The front (8) of the board (2) and the inside of the board (2) (
In the case of a multilayer board), wiring and a semiconductor attachment surface are formed using a conductive material, and a semiconductor device (1) is formed on the surface of the board (2).
A large number of them were attached by soldering, etc., and they were stacked in multiple stages as shown in Figure 5 for high-density mounting.
従来の半導体装置の実装構造は以上のように構成すれて
いたので、基板の面積に左右され実装密度を上げるには
基板面積の増大するという問題点があり、半導体装置の
集積度は日々向上しており、実装密度も向上させる必要
があった。Conventional packaging structures for semiconductor devices have been configured as described above, so there is a problem in that increasing the packaging density requires an increase in the board area as it depends on the area of the board, and the degree of integration of semiconductor devices is improving day by day. Therefore, it was necessary to improve the packaging density.
この発明は上記のような問題点を解消するためにな１れ
たもので、基板に穴を設けこの穴に半導体装置を埋めこ
むことによって実装密度の向上を図ることを目的とする
。The present invention was made to solve the above-mentioned problems, and an object of the present invention is to improve the packaging density by providing a hole in a substrate and burying a semiconductor device in the hole.
この発明に係る半導体装置の実装構造は、基板に穴を設
け、この穴に半導体装置を埋めこむように実装するよう
にしたものである。A mounting structure for a semiconductor device according to the present invention is such that a hole is provided in a substrate, and the semiconductor device is mounted so as to be buried in the hole.
この発明における半導体装置の実装構造は、基板に穴を
設けこの穴に半導体装置を埋めこむように実装したので
、実装密度を高密度化できる。In the semiconductor device mounting structure according to the present invention, since a hole is provided in the substrate and the semiconductor device is mounted so as to be buried in the hole, the mounting density can be increased.
以下、この発明の一実施例を図について説明する。第１
図において、（８）は追加される配線層、（４）は従来
基板の配線層である。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (8) is an added wiring layer, and (4) is a wiring layer of the conventional board.
半導体装置（１）を埋め込むことにより、基板配線層（
２）に配線層（８）が２層追加されるので、基板は多層
配線化し、基本単位表囲積に対し、基板配線密度が向上
する。従って、半導体装置（１）を密着して実装できる
ようになり、実装密度が向上する。By embedding the semiconductor device (1), the substrate wiring layer (
Since two wiring layers (8) are added to 2), the board has multilayer wiring, and the board wiring density is improved with respect to the basic unit surface area. Therefore, the semiconductor device (1) can be closely mounted, and the packaging density is improved.
さらにこの発明と従来実装状態、第２図と第５図を比較
すると理解しやすい。（７）の従来の厚さと（８）の本
実施例の厚さが等しいと仮定した場合、上記理由により
基板配線Ｉｉ１＋Ｓ＞が追加嘔れているので、基板の配
線密度が向上するので、従来のピッチ（５）に比較して
本実施例によるピッチ（６）は短くなっているため、基
板１枚当りの半導体装置（１）の付着個数が増加する。Furthermore, it is easier to understand by comparing the present invention and the conventional mounting state, FIGS. 2 and 5. Assuming that the conventional thickness (7) and the thickness of this embodiment (8) are equal, the board wiring Ii1+S> is added for the above reason, so the wiring density of the board improves, Since the pitch (6) according to this embodiment is shorter than the pitch (5) of , the number of semiconductor devices (1) attached per substrate increases.
従って、半導体装置の実装密度が向上する。Therefore, the packaging density of semiconductor devices is improved.
第３図はこの発明の他の実施例を示したもので基板端に
凹凸を設は嵌合することにより、安定した基板を実装で
きるようになる。FIG. 3 shows another embodiment of the present invention, in which a stable board can be mounted by providing and fitting irregularities on the edge of the board.
（従来技術では、半導体装置が引っかかって、基板端に
凹凸を設けても挿入できない。）〔発明の効果〕
以上のように、この発明によれば、基板に穴を設け、こ
の穴に半導体装置を埋めこむように実装したので実装密
度を高密度が出来る等の効果がある。(In the conventional technology, the semiconductor device gets caught and cannot be inserted even if unevenness is provided on the edge of the substrate.) [Effects of the Invention] As described above, according to the present invention, a hole is provided in the substrate, and the semiconductor device is inserted into the hole. Since it is mounted so as to embed it, it has the effect of increasing the packaging density.
第１図はこの発明の一実施例である半導体装置の実装構
造を示す断面図、第２図は第１図の半導体装置の多段実
装状態を示す断面図、第３図はこの発明の他の実施例を
示す斜視図、第４図は従来の半導体装置の実装状態を示
す斜視図、第５図は第４図の半導体装置の多段実装状態
を示す断面図である。図において、（１）は半導体装置
、（２）は基板（多ｍ ） 、 （８１は追加される配
線層、（４）は従来基板の配線層、（６）は発明の一実
施例のピッチ、（８）は発明の一実施例の厚さを示す。
尚、図中、同一符号は同一、または相当部分を示す。FIG. 1 is a cross-sectional view showing a mounting structure of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a multistage mounting state of the semiconductor device of FIG. 1, and FIG. FIG. 4 is a perspective view showing an embodiment of the present invention, FIG. 4 is a perspective view showing a conventional semiconductor device mounted, and FIG. 5 is a cross-sectional view showing the semiconductor device of FIG. 4 mounted in multiple stages. In the figure, (1) is a semiconductor device, (2) is a substrate (multiple m), (81 is an added wiring layer, (4) is a wiring layer of a conventional board, and (6) is a pitch of an embodiment of the invention. , (8) indicate the thickness of an embodiment of the invention. In the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
装することを特徴とする半導体装置の実装構造。A mounting structure for a semiconductor device, characterized in that a hole is provided in a substrate and a semiconductor device is mounted so as to be embedded in the hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2026590A JPH03230597A (en) | 1990-02-06 | 1990-02-06 | Semiconductor device mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2026590A JPH03230597A (en) | 1990-02-06 | 1990-02-06 | Semiconductor device mounting structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03230597A true JPH03230597A (en) | 1991-10-14 |
Family
ID=12197755
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2026590A Pending JPH03230597A (en) | 1990-02-06 | 1990-02-06 | Semiconductor device mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03230597A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5690891A (en) * | 1995-02-10 | 1997-11-25 | Ald Vacuum Technologies Gmbh | Process for the production of alloys in an inductively heated cold-walled crucible |
| EP0774888A3 (en) * | 1995-11-16 | 1998-10-07 | Matsushita Electric Industrial Co., Ltd | Printing wiring board and assembly of the same |
-
1990
- 1990-02-06 JP JP2026590A patent/JPH03230597A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5690891A (en) * | 1995-02-10 | 1997-11-25 | Ald Vacuum Technologies Gmbh | Process for the production of alloys in an inductively heated cold-walled crucible |
| EP0774888A3 (en) * | 1995-11-16 | 1998-10-07 | Matsushita Electric Industrial Co., Ltd | Printing wiring board and assembly of the same |
| US6324067B1 (en) | 1995-11-16 | 2001-11-27 | Matsushita Electric Industrial Co., Ltd. | Printed wiring board and assembly of the same |
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