JPH03266180A - Layout pattern verification device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a layout pattern verification device that verifies wiring widths and wiring spacings at or above layout pattern design reference values that are legal in circuit design.

[Conventional technology]

FIG. 4 is a block diagram showing the overall configuration of a conventional layout pattern verification device. In the figure, (1) is layout pattern data that is circuit layout information, (2) is circuit diagram data, and brush layout pattern data ( 1) is the design standards verification section that verifies whether the design standards are met, F31 is the circuit connection verification section that compares and verifies the circuit connections of both the layered pattern and the circuit diagram, and F31 is the verification result data of the design main office verification section CAl1. , (4) is the circuit connection verification section (
This is the verification result data of 3).

Next, the operation will be explained. Layout pattern data (1
) is verified by the design standard verification unit to see if it satisfies the design standard, and is added to the verification result data ρ. In addition, the circuit diagram data + 2) and layout pattern data (1) inputted by a circuit diagram editor etc. are compared and verified for each circuit connection in the circuit connection verification section (3), and the 14th verification result data is output. Ru.

[Problems that blindness attempts to solve]

Conventional layout pattern verification equipment was configured as described above, so if the wiring width and wiring spacing determined by the circuit design exceed the design standard values, the entire layout pattern must be visually inspected manually to verify it. There were problems in that things were sometimes overlooked because they were necessary, and checking took time.

This invention was made in order to solve the above-mentioned problems, and it is an object of the present invention to provide a layout pattern verification device that can automatically check the wiring width and wiring spacing determined by circuit design, and can shorten the time required for checking. With the goal.

[Means to solve the problem]

The layout pattern verification device according to the present invention utilizes the verification result data of the one-circuit connection verification section by giving information on the wiring name, wiring width, and spacing from other wiring to the necessary wiring in the circuit diagram. Extract the wiring and its information in the layout pattern corresponding to the wiring with the wiring name above, as well as the information on the wiring with the wiring name on the circuit diagram extracted in advance and the corresponding layered pattern. The above wiring information is compared and verified, and the wiring width and spacing from other wiring determined by the circuit design are verified.

[Effect]

In this invention, the wiring width determined by the circuit design and the spacing with other wiring can be checked by providing the necessary information to the circuit diagram in advance, so that the wiring corresponding to the circuit diagram and its information are extracted from the layout pattern. Compare and verify wiring information.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
FIG. 1 is a block diagram showing the overall configuration of a layered pattern verification apparatus which is an embodiment of the present invention. In the figure,
(1) is layout pattern data that is circuit layout information; (2) is circuit diagram data; (3) is a circuit connection verification unit for comparing and verifying layout pattern data (1) and circuit diagram data (2); (4) is the verification result data of the circuit connection verification section (3), (5) is the circuit diagram wiring information extraction means, (
6) is the circuit diagram wiring information extracted from the circuit diagram data (2) by the circuit diagram wiring information extraction means (5), and (7) is the verification result of the circuit diagram wiring information (6) and the circuit connection verification unit (3). Layout pattern wiring information extraction means (8) selects the wiring of layout pattern data (1) corresponding to the wiring of the circuit diagram extracted from data (4) and extracts necessary information; )
Layout pattern wiring information extracted by (9)
is a wiring information comparison and verification means that compares and verifies the wiring information from the layout pattern wiring information (8) and the circuit diagram wiring information (6), and QG is the verification result data of the wiring information comparison and verification means (9).

Next, the operation of the above embodiment will be explained with reference to FIGS. 2 and 3. FIG. 2 is a flowchart showing the operation of FIG. 1, and FIG. 3 is a circuit diagram showing an example of wiring extracted by the circuit diagram wiring information extraction means (5). In the figure, 翰 is the wiring name and wiring width, and (to) (2) is the wiring name and wiring spacing that should be spaced.

In step 11, wiring information such as wiring name, wiring width, and wiring spacing is extracted.

In step 12, the wiring of the layout pattern corresponding to the wiring expert %B extracted in step 11 is extracted from the layout pattern data (υ) using the verification result data (4) of the circuit connection verification section (3).Step 13
Now, for the wiring extracted in step 12, the wiring information of the minimum width of the wiring and the minimum spacing between the wiring and the wiring to be spaced is extracted, and in step 14, the extracted wiring information + 6) (81) are compared. By this comparison, the wiring information of the layout pattern (8
) is smaller, it is determined as an error, and a portion of the error is output as verification result data in step 16. On the other hand, if the layout pattern wiring information (8) is larger or the same, no error is output.

In addition, although the above example shows a case in which wiring information is given only to the necessary wiring, instead of wiring names, sequential numbers are given to all wiring, and the wiring width, the wiring number that should be spaced, and its A method may also be used in which the intervals are given to the circuit diagram.

[Effects of the Invention] As described above, according to the present invention, wiring information is given to the circuit diagram in advance, and the circuit diagram wiring information and layout pattern wiring information are compared and verified using the verification result data of circuit connection verification. Therefore, the reliability of the layout pattern is improved and the time for visual inspection of the layout pattern can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of a layout pattern verification device which is an embodiment of the present invention, FIG. 2 is a flowchart showing the operation of FIG. 1, and FIG. 3 is a circuit diagram wiring information extraction of FIG. 1. FIG. 4 is a block diagram showing the overall configuration of a conventional layout pattern verification device. In the figure, (1) is layout pattern data, +2
) is the circuit diagram data, (3) is the circuit connection verification section, [4] is the verification result data, (5) is the circuit diagram wiring information extraction means, (
6) is circuit diagram wiring information, (7) is a layered pattern wiring information extraction means, (8) is layout pattern wiring information, (9) is wiring information comparison verification means, and αO is verification result data. α9 represents the wiring name and wiring width, and (to) (1) represents the wiring interval and wiring name. In addition, the same symbols in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] In a circuit diagram in which the necessary wiring in the circuit diagram is given the wiring information such as the wiring name, the wiring width of the layout pattern, and the spacing in the layout pattern with other wiring, verify the circuit connection between this circuit diagram and the layout pattern. a layout pattern wiring information extraction means for extracting wiring of a layout pattern corresponding to a wiring having a wiring name on the circuit diagram and its wiring information using verification result data; and a layout pattern extracted by the extraction means. A layout pattern verification device comprising a wiring information comparison and verification means for comparing and verifying the wiring information of the circuit diagram with the wiring information of the circuit diagram.