JPH03263871A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] To provide a semiconductor device that can suppress reduction in effective channel length directly under a gate electrode due to element miniaturization and increase margin against short channel effect. A convex portion is formed on a substrate, a gate insulating film is formed on the substrate to cover the convex portion, and a gate electrode is formed to cover the convex portion via the gate insulating film. Configure it so that

[Industrial Application Field] The present invention relates to a semiconductor device, and can be applied to semiconductor devices such as MOS transistors, and in particular, a semiconductor device that can suppress reduction in effective channel length directly under a gate electrode due to element miniaturization. Regarding.

In recent years, with the miniaturization of elements, the gate electrode width has been narrowed to improve characteristics, especially in MOS transistors. However, there is a problem in that simply narrowing the gate electrode width on a flat substrate simultaneously reduces the effective channel length directly under the gate electrode, reducing the margin for the short channel effect.

Therefore, there is a need for a semiconductor device that can suppress reduction in the effective channel length directly under the gate electrode due to device miniaturization and increase the margin against short channel effects.

[Conventional technology]

3 and 4 are diagrams for explaining a conventional semiconductor device, FIG. 3 is a sectional view showing the structure of the conventional example, and FIG. 4(a)
-(f) are diagrams illustrating a conventional manufacturing method.

In these figures, 31 is a substrate made of Si or the like, 32
is S i O! 33 is Si
, a silicon nitride film made of N4, 34 an opening formed in the silicon nitride film 33, 35 a field oxide film made of Sing etc., 36 a gate insulating film made of 3i02 etc., 37 a polysilicon film for forming a gate electrode. Membrane, 37a
38 is a gate electrode made of poly-Si, etc.; 38 is a resist film;
39 is a source/drain diffusion layer, 40 is a glabellar insulating film made of PSG or the like, 41 is a contact hole, and 42 is a wiring layer made of AA or the like.

Next, the manufacturing method will be explained.

First, as shown in FIG. 4(a), after oxidizing the substrate 31 by, for example, thermal oxidation to form a silicon oxide film 32 as an initial oxide film on the substrate 31, a silicon oxide film 32 is formed on the silicon oxide film 32 by, for example, CVD method. A silicon nitride film 33 is formed by depositing Si and zN-.

Next, as shown in FIG. 4(b), the silicon nitride film 33 is selectively etched using, for example, iRI, so that it remains only in the element region, and an opening 3 for forming a field oxide film is formed.
form 4. At this time, the silicon oxide film 32 is exposed within the opening 34.

Next, as shown in FIG. 4C, a field oxide film 35 is formed by selectively oxidizing the substrate 31 through the opening 34 using the silicon nitride film 33 as a mask using LOCO3.

Next, as shown in FIG. 4(d), the silicon nitride film 33 and the silicon oxide film 3 are etched, for example, by wet etching.
2 is removed to expose the substrate 31. At this time, an element region is formed.

Next, as shown in FIG. 4(e), after oxidizing the substrate 31 by, for example, thermal oxidation to form a gate insulating film 36 on the substrate 31, a gate is formed so as to cover the gate insulating film 36 by, for example, a CVD method. A polysilicon film 37 for forming electrodes is formed. Next, after coating a resist on the polysilicon film 37 to form a resist film 38, the resist film 38 is exposed and developed to form a polysilicon film 3 corresponding to the gate electrode.
Patterning is performed so that only the area above 7 remains. next,
As shown in FIG. 4(f), the gate electrode 37a is formed by selectively etching the polysilicon film 37 using the resist film 38 as a mask, for example, by RIE, and after removing the resist film 38, by, for example, ion implantation. By introducing impurities into the substrate 31 using the gate electrode 37a as a mask and performing an annealing process, source/drain diffusion Fi 39 is formed.
form.

Then, after forming an interlayer insulating film 40 made of PSG on the entire surface and forming a contact hole 41 in the interlayer insulating film 40 and the gate insulating film 36, the source/drain diffusion layer 39 and the gate electrode 37a are connected via the contact hole 41. By forming the wiring layer 42 so as to make contact, a semiconductor device as shown in FIG. 3 can be obtained.

[Problem to be solved by the invention]

In the conventional semiconductor device described above, the width of the gate electrode 37a has been made narrower in order to improve the l transistor characteristics in response to the recent severe miniaturization of elements. However, the gate electrode 37a is simply formed on the flat substrate 31.
If the width is simply made narrower, the effective channel length directly under the gate electrode 37a (the LL portion shown in FIG. 3) will also become narrower, resulting in a reduction in the margin for the short channel effect. This tends to become more pronounced as the element becomes finer.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device that can suppress the reduction in the effective channel length directly under the gate electrode due to device miniaturization and increase the margin against the short channel effect.

[Means to solve the problem]

In order to achieve the above object, a semiconductor device according to the present invention includes a convex portion formed on a substrate, a gate insulating film formed on the substrate so as to cover the convex portion, and a gate insulating film covering the convex portion via the gate insulating film. It is characterized in that a gate electrode is formed so as to cover it.

[Effect]

In the present invention, as shown in FIG.
is formed, and a gate electrode 8a is formed so as to cover the convex portion 6 with the gate insulating film 7 interposed therebetween.

Therefore, the effective channel length directly under the gate electrode 8a can be made longer by approximately the diagonal length of about 1 of the convex portion 6, as shown in section L2 of FIG. become able to.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 and 2 are diagrams for explaining one embodiment of a semiconductor device according to the present invention, FIG. 1 is a sectional view showing the structure of one embodiment, and FIG. 2 is a diagram illustrating a manufacturing method of one embodiment. FIG.

In these figures, 1 is a substrate made of Si or the like, 2a,
2b is a silicon oxide film made of Sin, etc., 3a, 3b
is a silicon nitride film made of SssNa etc., 4a
is an opening formed in the silicon nitride film 3a, 4b is an opening formed in the silicon nitride film 3b, and 5a and 5b are openings 5i
A field oxide film made of n2 etc., 6 a convex portion formed on the substrate l, 7 a gate insulating film made of SiO□ etc., 8 a polysilicon film for forming a gate electrode, 8a a gate electrode made of poly 31 etc. , 9 is a resist film, 10a is SiO
2, IOb is a PSG film, 11 is an interlayer insulating film made of a 5in2 film 10a and a PSG film 10b, 12 is a source/drain diffusion layer, 13 is a contact hole, and 14 is a wiring layer made of A1 and the like.

Next, the manufacturing method will be explained.

First, as shown in FIG. 2(a), the substrate 1 is oxidized, for example, by thermal oxidation to form a silicon oxide film 2a having a film thickness of, for example, 100 to 300 layers. Depositing Si3N4 to a film thickness of, for example, 1
ooo~3000 silicon nitride films 3a are formed.

Next, as shown in FIG. 2(b), the silicon nitride film 3a is selectively etched by RIE, for example, so that it remains only in the region on the silicon oxide film 2a corresponding to the gate electrode, and a field oxide film is formed. An opening 4a is formed, and the silicon oxide film 2a is exposed within the opening 4a.

Next, as shown in FIG. 2C, the substrate 1 is selectively oxidized through the opening 4a using the silicon nitride film 3a as a mask by LOCO3, so that the film thickness is reduced to 50 mm, for example.
A field oxide film 5a having a thickness of 0.00 to 6000 is formed.

At this time, the silicon nitride film 3a between the field oxide films 5a
A convex portion 6 is formed on the lower substrate 1.

Next, as shown in FIG. 2(d), the silicon nitride film 3a and the silicon oxide film 2a are etched, for example, by wet etching.
Then, the field oxide film 5a is removed to expose the substrate 1 and the convex portions 6 formed on the substrate 1.

Next, as shown in FIG. 2(e), the substrate 1 is oxidized, for example, by thermal oxidation to form a silicon oxide film 2b having a film thickness of, for example, 100 to 300 layers. Si, N.

A silicon nitride film 3b having a thickness of, for example, 1,000 to 3,000 layers is formed by depositing.

Next, as shown in FIG. 2(f), the silicon nitride film 3b is selectively etched by, for example, RIE so that it remains only in the element region, and an opening 4 for forming a field oxide film is formed.
b is formed, and the silicon oxide film 2b is exposed within the opening 4b.

Next, as shown in FIG. 2(g), the substrate l is selectively oxidized by LOCO3 using the silicon nitride film 3b as a mask through the opening 4b, so that the film thickness is reduced to 50 mm, for example.
A field oxide film 5b having a thickness of 0.00 to 6000 is formed.

Next, as shown in FIG. 2(h), the silicon nitride film 3b and the silicon oxide film 2b are removed by wet etching, for example, to expose the substrate 1 and the convex portions 6 formed on the substrate 1. .

That is, at this time, an element region is formed.

Next, as shown in FIG. 2(i), the substrate 1 is oxidized, for example, by thermal oxidation, so that the film thickness is, for example, 10 mm, so as to cover the convex portions 6.
After forming the gate insulating film 7 of 0 to 200 layers, for example, C.
A polysilicon film 8 having a thickness of, for example, 3,000 to 4,000 thick for forming a gate electrode is formed to cover the gate insulating film 7 by the VD method. Next, a resist is applied onto the polysilicon film 8 to form a resist film 9, and then the resist film 9 is patterned by exposure and development so that it remains only in the region on the polysilicon film 8 corresponding to the gate electrode. At this time, the resist film 9 is formed on the convex portion 6 with the gate insulating film 7 interposed therebetween.

Next, as shown in FIG. 2(j), the polysilicon film 8 is selectively etched by, for example, RIE using the resist film 9 as a mask to form a gate electrode 8a. At this time,
The gate electrode 8a is formed on the protrusion 6 formed on the substrate 1 with the gate edge film 7 interposed therebetween. Next, after removing the resist film 9, As' is introduced into the substrate 1 by ion implantation of As, for example, using the gate electrode 8a as a mask to form a source/drain diffusion layer.

Next, for example, a CVD method is used to cover the polysilicon film 8 so that the film thickness is, for example, c*2ooo Si*2 film 10.
PSG film J with a and film thickness of, for example, 5000 to 7000
After forming the glabellar insulating film 11 made of ob, an annealing treatment is performed to diffuse As'' introduced in advance to form a source/drain diffusion layer 12.

After forming a contact hole 13 in the glabella insulating film 11 and the gate insulating film 7, a wiring layer 14 made of Af is formed so as to make contact with the gate electrode 8a and the source/drain diffusion layer 12 through the contact hole 13. By doing so, a semiconductor device as shown in FIG. 1 can be obtained.

That is, in the above embodiment, as shown in FIG. 1, the gate electrode 8a is formed so as to cover the convex portion 6 formed on the substrate 1 via the gate insulating film 7. Part L2 in Figure 1 shows the effective channel length directly under the gate electrode 8a, compared to the case where the gate electrode is formed on a substrate with the same width as in the conventional case (the width of the gate electrode and the width of the source/drain diffusion layer are the same). Thus, the length can be increased approximately by the slope of the convex portion 6. Therefore, reduction in the effective channel length directly under the gate electrode 8a due to device miniaturization can be suppressed, and a margin against the short channel effect can be increased. Note that the shape of the convex portion 6 that determines the effective channel length can be appropriately set by appropriately setting the conditions for Locos depending on the requirements of transistor characteristics or the degree of transistor miniaturization.

In addition, although the above-mentioned example explained the case where it applied to an NMOS transistor, the present invention is not limited to this, and the substrate 1 is made into N type, the source/drain diffusion layer 12 is made into P type, and it is applied to a PMOS transistor. In addition, the transistor structure may be DDD, which has been devised as a countermeasure against hot electrons.
It is also possible to apply an LDD structure or the like.

In the above embodiment, the convex portion 6 is formed on the substrate 1 using the LOCOS method, but the present invention is not limited to this. Convex portion 6 directly on substrate 1
may be formed.

〔Effect of the invention〕

According to the present invention, it is possible to suppress the reduction in the effective channel length directly under the gate electrode due to device miniaturization, and it is possible to increase the margin against the short channel effect.

[Brief explanation of drawings]

1 and 2 are diagrams explaining one embodiment of a semiconductor device according to the present invention, FIG. 1 is a cross-sectional view showing the structure of one embodiment, and FIG. 2 is a diagram illustrating a manufacturing method of one embodiment. Figures 3 and 4C are diagrams illustrating conventional semiconductor devices. Figure 3 is a sectional view showing the structure of the conventional example, and Figure 4 is a diagram illustrating the manufacturing method of the conventional example. It is. ...Substrate, ...Protrusion, ...Gate insulating film, a...Gate electrode. FIG. 2 is a cross-sectional view showing the structure of a conventional example. FIG. 3 is a diagram explaining the manufacturing method of an embodiment.

Claims (1)

[Claims] A protrusion (6) is formed on the substrate (1), a gate insulating film (7) is formed on the substrate (1) so as to cover the protrusion (6), and the gate A semiconductor device characterized in that a gate electrode (8a) is formed so as to cover the protrusion (6) with an insulating film (7) interposed therebetween.