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JPH03276627A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH03276627A
JPH03276627A JP7641390A JP7641390A JPH03276627A JP H03276627 A JPH03276627 A JP H03276627A JP 7641390 A JP7641390 A JP 7641390A JP 7641390 A JP7641390 A JP 7641390A JP H03276627 A JPH03276627 A JP H03276627A
Authority
JP
Japan
Prior art keywords
substrate
resist
thin film
pattern
intermediate layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7641390A
Other languages
Japanese (ja)
Inventor
Tsunenori Yamauchi
経則 山内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7641390A priority Critical patent/JPH03276627A/en
Publication of JPH03276627A publication Critical patent/JPH03276627A/en
Pending legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (概要〕 半導体基板または該基板上に形成した薄膜へのパターン
形成に関し、 パターン形成面上でのレジストの除去を完全に行うこと
を目的とし、 半導体基板または該基板上に形成した薄膜にレジストを
被覆し、写真蝕刻技術によりパターンを形成する工程が
、該基板または薄膜とレジストとの間に該基板または薄
膜よりも高い選択比をもってエツチング除去可能な中間
層を設ける工程と、前記レジストを選択露光した後に現
像し、レジストパターンを形成する工程と、該レジスト
パターンをマスクとして中間層と前記基板または薄膜を
選択エツチングする工程と、該マスクとして用いたレジ
ストと中間層とを除去する工程とを少なくとも含むこと
を特徴とする半導体装置の製造方法を構成する。
[Detailed Description of the Invention] (Summary) With regard to pattern formation on a semiconductor substrate or a thin film formed on the substrate, the purpose of this invention is to completely remove the resist on the pattern formation surface. The step of coating the thin film formed on the substrate with a resist and forming a pattern by photolithography is a step of providing an intermediate layer between the substrate or the thin film and the resist that can be removed by etching with a higher selectivity than the substrate or the thin film. a step of selectively exposing and developing the resist to form a resist pattern; a step of selectively etching the intermediate layer and the substrate or thin film using the resist pattern as a mask; and a step of selectively etching the intermediate layer and the substrate or thin film using the resist pattern as a mask; A method of manufacturing a semiconductor device is characterized in that it includes at least a step of removing.

(産業上の利用分野] 本発明はパターン形成に当たってレジストの残存を無く
した半導体装置の製造方法に関する。
(Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor device in which no resist remains during pattern formation.

大量の情報を高速に処理する必要から情報処理装置は小
形化と大容量化が行われているが、これに対応し、装置
の主体を構成する半導体装置は集積化が進んでLSIや
VLSIが実用化されている。
Due to the need to process large amounts of information at high speed, information processing equipment is becoming smaller and larger in capacity.In response to this, the semiconductor devices that make up the main body of the equipment are becoming more integrated, leading to LSI and VLSI. It has been put into practical use.

こ\で、これらの半導体装置を含め、総ての半導体素子
の製造に当たっては半導体基板上に薄膜形成技術、写真
蝕刻技術(フォトリソグラフィ或いは電子線リソグラフ
ィ)、不純物注入技術などが用いられている。
In the manufacture of all semiconductor elements, including these semiconductor devices, techniques such as thin film formation technology, photo-etching technology (photolithography or electron beam lithography), and impurity injection technology are used on semiconductor substrates.

次に、半導体にはシリコン(Si)で代表される単体半
導体とガリウム砒素(GaAs)やインジウム燐(In
P)で代表される化合物半導体とがあるが、LSIやV
LS Iなとの集積回路は殆どの場合Si基板を用いて
製造されている。
Next, semiconductors include simple semiconductors such as silicon (Si), gallium arsenide (GaAs), and indium phosphide (Indium phosphide).
There are compound semiconductors represented by P), but LSI and V
Integrated circuits such as LSI are manufactured using Si substrates in most cases.

そして、薄膜パターンの形成法として配線パターンの形
成にアルミニウムのような金属を用いる場合にはスパッ
タ法や真空蒸着法が、またポリSiを用いる場合は気相
成長法(略してCVD法)が、また、絶縁層の形成材料
としては二酸化シリコン(5i(h)や窒化硅素(5i
sN4)が用いられているが、これらは何れもCVD法
により作られている。
As a method for forming a thin film pattern, when a metal such as aluminum is used to form a wiring pattern, a sputtering method or a vacuum evaporation method is used, and when poly-Si is used, a vapor phase growth method (abbreviated as CVD method) is used. In addition, silicon dioxide (5i(h)) and silicon nitride (5i
sN4) is used, but these are all made by CVD method.

そして、このようにして基板上に嗅形成した薄膜あるい
は基板自体に対し、写真蝕刻技術を用いて選択エツチン
グを行い、微細な線幅の配線パターンや上下の配線層間
を結ぶピアホール(Via−hole)を形成しており
、また基板に対してはトレンチ(Trench)の形成
が行われている。
The thin film thus formed on the substrate or the substrate itself is then selectively etched using photolithographic technology to form wiring patterns with fine line widths and via-holes connecting upper and lower wiring layers. A trench is also formed in the substrate.

〔従来の技術〕[Conventional technology]

先に記したように、半導体装置の製造に当たっては半導
体基板(以下略して基板)或いはこの上に絶縁膜や導電
膜を形成し、これに写真蝕刻技術を用いてパターン形成
が行われている。
As described above, in manufacturing a semiconductor device, a semiconductor substrate (hereinafter simply referred to as a substrate) or an insulating film or a conductive film is formed thereon, and a pattern is formed on this using photolithography.

すなわち、基板または薄膜の上にレジストを被覆し、レ
ジストが“ネガタイプ”の場合には光照射部が現像液に
不溶となり、“ポジタイプ”の場合には可溶となるのを
利用してレジストパターンを作り、このレジストパター
ンをマスクとしてドライエツチング或いはウェットエン
チングを行って基板または基板上の薄膜をエツチングし
、次に、マスクとして用いたレジストを溶剤を用いて溶
解除去するか、或いはプラズマ処理することにより除去
している。
In other words, a resist is coated on a substrate or a thin film, and when the resist is a "negative type", the light irradiated area is insoluble in the developer, and when it is a "positive type", it is soluble, so a resist pattern is created. This resist pattern is used as a mask to perform dry etching or wet etching to etch the substrate or the thin film on the substrate, and then the resist used as the mask is removed by dissolving it using a solvent or is subjected to plasma treatment. It is removed by this.

こ\で、プラズマ処理は酸素(0□)プラズマを用いて
行われており、アッシング(沃化処理)と言われている
Here, the plasma treatment is performed using oxygen (0□) plasma and is called ashing (iodination treatment).

然し、このような除去法によっても充分除去できない場
合があり、か\る場合、レジスト中に含まれている不純
物イオン特にナトリウム(Na)イオンにより表面層が
汚染され漏洩電流を増加させるなど素子の電気的特性を
著しく低下させると云う問題がある。
However, even with such a removal method, there are cases where sufficient removal is not possible, and in such cases, impurity ions, particularly sodium (Na) ions, contained in the resist contaminate the surface layer and cause problems such as increased leakage current. There is a problem that electrical characteristics are significantly deteriorated.

そのため、パターン形成後はレジストを完全に除去する
ことが必要であるが、充分でない場合が多く、対策が必
要であった。
Therefore, it is necessary to completely remove the resist after pattern formation, but this is often not sufficient, and countermeasures are required.

〔発明が解決しようとする課題] 半導体装置の製造工程における微細パターンの形成法と
しては、予め設けたレジストパターンをマスクとして基
板或いは基板上に形成した薄膜に対してエツチングを行
い、微細パターンを形成した後はレジストパターンの除
去が行われている。
[Problems to be Solved by the Invention] As a method for forming fine patterns in the manufacturing process of semiconductor devices, etching is performed on a substrate or a thin film formed on a substrate using a resist pattern prepared in advance as a mask to form a fine pattern. After that, the resist pattern is removed.

然し、この除去が不充分の場合は所謂るNa汚染を住じ
、信頼性の著しい低下を招くことが問題で、この解決が
課題である。
However, if this removal is insufficient, so-called Na contamination occurs, resulting in a significant decrease in reliability, which is a problem to be solved.

(課題を解決するための手段〕 上記の課題は半導体基板または基板上に形成した薄膜に
レジストを被覆し、写真蝕刻技術によりパターンを形成
する工程が、この基板または薄膜とレジストとの間に基
板または薄膜よりも高い選択比をもってエツチング除去
可能な中間層を設ける工程と、レジストを選択露光した
後に現像し、レジストパターンを形成する工程と、この
レジストパターンをマスクとして中間層と基板または薄
膜を選択エツチングする工程と、マスクとして用いたレ
ジストと中間層とを除去する工程とを少なくとも含むこ
とを特徴として半導体装置の製造方法を構成することに
より解決することができる。
(Means for Solving the Problems) The above problem is that the process of coating a semiconductor substrate or a thin film formed on a substrate with a resist and forming a pattern by photolithography is a process in which a semiconductor substrate or a thin film formed on a substrate is coated with a pattern between the substrate or the thin film and the resist. Alternatively, there is a step of providing an intermediate layer that can be removed by etching with a higher selectivity than the thin film, a step of selectively exposing and developing the resist to form a resist pattern, and using this resist pattern as a mask, selecting the intermediate layer and the substrate or thin film. This problem can be solved by configuring a semiconductor device manufacturing method characterized by including at least the step of etching and the step of removing the resist used as a mask and the intermediate layer.

(作用〕 本発明は微細パターンの形成を行う基板または′FR膜
とレジストとの間に、この基板または薄膜と高い選択比
をもってエツチング可能な中間層を設けることによりレ
ジストの残留を皆無とするものである。
(Function) The present invention eliminates any residual resist by providing an intermediate layer that can be etched with a high selectivity to the substrate or thin film between the substrate or FR film on which a fine pattern is to be formed and the resist. It is.

すなわち、基板または薄膜よりも特定溶剤に溶は易い材
料を用いて中間層を設けておき、この上に形成したレジ
ストパターンをマスクとしてドライエツチングし、パタ
ーンを形成した後、中間層を溶剤で溶解すれば、この上
のレジストを完全に除くことができる。
In other words, an intermediate layer is prepared using a material that is more easily soluble in a specific solvent than the substrate or thin film, and a resist pattern formed thereon is used as a mask for dry etching.After the pattern is formed, the intermediate layer is dissolved with a solvent. This will allow you to completely remove the resist on top.

こ\で、中間層としては燐硅酸ガラス(略称PsG)、
硼硅酸ガラス(略称BSG) 、硼燐硅酸ガラス(BP
SG)などを挙げることができ、これらの材料からなる
中間層は5%弗酸(肝)水溶液や燐酸・硝酸(H2PO
4・HNO3)混合液(&Il成比100:2)などを
用いて容易に溶解除去することができる。
Here, the intermediate layer is phosphosilicate glass (abbreviated as PsG),
Borosilicate glass (BSG), borophosphosilicate glass (BP)
SG), etc., and the intermediate layer made of these materials is a 5% hydrofluoric acid (liver) aqueous solution, phosphoric acid/nitric acid (H2PO), etc.
It can be easily dissolved and removed using a mixed solution (&Il ratio: 100:2).

なお、薄膜の構成材としてはAfや金(Au)などの金
属やSiO□+ 513N4のような絶縁物が考えられ
るが、肝に溶けやすい5iOzの場合でも上記のガラス
材はエツチングレートは約10倍も大きく、そのためm
Wの溶解は極めて少なく抑えることができる。
Note that metals such as Af and gold (Au) and insulators such as SiO□+513N4 can be considered as constituent materials for the thin film, but even in the case of 5iOz, which easily dissolves in the liver, the etching rate of the above glass material is approximately 10. twice as large, so m
Dissolution of W can be suppressed to an extremely low level.

次に、このよう番こして中間層を除いた後は充分に水洗
して溶剤成分を除き、引き続いて窒素(N2)などの不
活性雰囲気中で加熱して吸着水を除いておくことが必要
である。
Next, after removing the intermediate layer by straining, it is necessary to thoroughly wash with water to remove the solvent component, and then heat in an inert atmosphere such as nitrogen (N2) to remove the adsorbed water. It is.

〔実施例〕〔Example〕

MOS ICの製造工程において、ソースおよびトレイ
ン電極の形成に本発明を実施した場合について説明する
と次のようになる。
A case in which the present invention is applied to the formation of source and train electrodes in the manufacturing process of a MOS IC will be explained as follows.

Si基板lの素子形成領域をSi:+N4膜で被覆した
後、1000°Cでウェット酸化し、厚さが約6000
人のフィールド酸化膜2を形成した後、熱HPO,+に
浸漬して5isNa膜を除去したSi基板1を1000
’Cでドライ酸化して素子形成領域に約300人の厚さ
のゲート酸化膜3を形成した。(以上第1図A)次に、
Si基板1を気相成長装置にセットし、Si基板1を臭
化燐(PBr+)のガス雰囲気中で920″Cに加熱し
、この基板上に約300人の厚さのPSG膜4を膜形成
した。(以上同図B) 次に、この基板上にレジスト5を被覆した後、状態で三
弗化メタン(CHF3)をエッチャントとしてRIEを
行い、PSG膜4とゲート酸化膜3を工・7チングした
。(以上同図C) 次に、Si基板を煮沸)12SO,中に浸漬してレジス
ト5を溶解除去した後、2%のHF水溶液に40秒間浸
漬してPSG膜4を除去し、純水を用いて充分に洗浄処
理をした後、乾燥した窒素(N2)雰囲気中で600°
Cで加熱して水分を除去した。
After covering the element forming area of the Si substrate l with a Si:+N4 film, wet oxidation was performed at 1000°C to a thickness of approximately 6000°C.
After forming the field oxide film 2, the Si substrate 1 was immersed in hot HPO,+ to remove the 5isNa film.
A gate oxide film 3 having a thickness of approximately 300 mm was formed in the element formation region by dry oxidation using carbon. (Above Figure 1 A) Next,
The Si substrate 1 is set in a vapor phase growth apparatus, heated to 920''C in a phosphorus bromide (PBr+) gas atmosphere, and a PSG film 4 with a thickness of approximately 300 mm is deposited on the substrate. (See Figure B) Next, after coating the resist 5 on this substrate, RIE was performed using methane trifluoride (CHF3) as an etchant to form the PSG film 4 and gate oxide film 3. (See C in the same figure) Next, the Si substrate was immersed in boiling 12 SO to dissolve and remove the resist 5, and then immersed in a 2% HF aqueous solution for 40 seconds to remove the PSG film 4. , After thorough cleaning treatment with pure water, it was heated at 600° in a dry nitrogen (N2) atmosphere.
The water was removed by heating at C.

(以上同図D) このような工程をとることによりNa汚染の恐れのない
ゲート酸化膜3を得ることができた。
(The above is D in the same figure) By taking such a step, it was possible to obtain a gate oxide film 3 free from Na contamination.

〔発明の効果〕〔Effect of the invention〕

本発明の実施により半導体装置の製造工程において、被
処理基板上へのレジストの残留を無くすることができ、
これにより半導体装置の信頼性を向上することができる
By implementing the present invention, it is possible to eliminate residual resist on the substrate to be processed in the manufacturing process of semiconductor devices,
Thereby, the reliability of the semiconductor device can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明を適用したMOS IC製造工程の断面
図である。 図において、 1はSi基板、      2はフィールド酸化膜、3
はゲート酸化膜、    4はPSG腰、5はレジスト
、 6.6′は電極形成領域、 である。
FIG. 1 is a cross-sectional view of a MOS IC manufacturing process to which the present invention is applied. In the figure, 1 is a Si substrate, 2 is a field oxide film, and 3 is a Si substrate.
4 is the gate oxide film, 4 is the PSG layer, 5 is the resist, and 6.6' is the electrode formation area.

Claims (1)

【特許請求の範囲】  半導体基板または該基板上に形成した薄膜にレジスト
を被覆し、写真蝕刻技術によりパターンを形成する工程
が、 該基板または薄膜とレジストとの間に該基板または薄膜
よりも高い選択比をもってエッチング除去可能な中間層
を設ける工程と、 前記レジストを選択露光した後に現像し、レジストパタ
ーンを形成する工程と、 該レジストパターンをマスクとして中間層と前記基板ま
たは薄膜を選択エッチングする工程と、該マスクとして
用いたレジストと中間層とを除去する工程と、 を少なくとも含むことを特徴とする半導体装置の製造方
法。
[Claims] A step of coating a semiconductor substrate or a thin film formed on the substrate with a resist and forming a pattern by photolithography includes a step of forming a pattern between the substrate or the thin film and the resist at a higher temperature than the substrate or the thin film. a step of providing an intermediate layer that can be removed by etching with a selectivity; a step of selectively exposing the resist to light and then developing it to form a resist pattern; and a step of selectively etching the intermediate layer and the substrate or thin film using the resist pattern as a mask. A method for manufacturing a semiconductor device, comprising at least the following steps: and a step of removing the resist used as the mask and the intermediate layer.
JP7641390A 1990-03-26 1990-03-26 Manufacture of semiconductor device Pending JPH03276627A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7641390A JPH03276627A (en) 1990-03-26 1990-03-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7641390A JPH03276627A (en) 1990-03-26 1990-03-26 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03276627A true JPH03276627A (en) 1991-12-06

Family

ID=13604539

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7641390A Pending JPH03276627A (en) 1990-03-26 1990-03-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03276627A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0601723A3 (en) * 1992-11-24 1995-05-17 American Telephone & Telegraph Integrated circuit fabrication.
US6583037B2 (en) 2001-08-07 2003-06-24 Hynix Semiconductor Inc. Method for fabricating gate of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0601723A3 (en) * 1992-11-24 1995-05-17 American Telephone & Telegraph Integrated circuit fabrication.
US6583037B2 (en) 2001-08-07 2003-06-24 Hynix Semiconductor Inc. Method for fabricating gate of semiconductor device

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