JPH03278392A - Control method for semiconductor memory device - Google Patents

Abstract

PURPOSE:To perform fast signal amplification with high quality by cutting off a pair of transfer gates simultaneously with or after the activation of a sense amplifier driving signal after transferring information in a memory cell to a pair of bit lines and a pair of input/output terminals. CONSTITUTION:After the information in the memory cell of a semiconductor memory device is transferred to the pair of bit lines 3A, 3B and the pair of input/output terminals 4A, 4B of a sense amplifier SNS2, a pair of transfer gates Q16A, Q16B connecting the pair of bit lines 3A, 3B to the pair of input/ output terminals 4A, 4B of a sense amplifier SNS2, are cut off simultaneously with or after the activation of the sense amplifier driving signal SE1. By cutting off the transfer gates Q16a, Q16b in such way, the capacity of the input/output terminals 4A, 4B of the sense amplifier SNS2 can be prevented from being decreased remarkable when signal amplification is started, therefore, it is pos sible to prevent the sense amplifier SNS2 receiving the disturbance of a noise, or to prevent sensing capability deteriorating due to the unbalance of capacity. In such a way, the fast signal amplification with high quality can be realized.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a bit line pair to which a plurality of memory cells are connected, and a pair of transfer transistors that respectively connect the bit line pair to a pair of input/output terminals of a sense amplifier. The present invention relates to a method of controlling a semiconductor memory device having a gate.

[Prior Art] FIG. 3 is a circuit diagram showing a conventional example of this type of semiconductor memory device, and FIG. 4 is a time chart showing a conventional control method for the semiconductor memory device of FIG.

The sense amplifier SNS 1 includes transistors Q10 . Ql 1. formed by Ql2゜Ql3, and the input/output nodes 4A and 4B of the sense amplifier
is transfer gate Q16. They are connected to bit lines 3A and 3B via Q1.6B, respectively. bit line 3
A, 3B has an l transistor type memory cell C21A,
C21B are connected via transistors Q17A and Q17B, respectively. Memory cells C21A, C21B
are also connected to word lines LA and IB, respectively. Memory cells 21 are connected to the bit lines 3A and 3B of the memory cell array.
In addition to A21B and a plurality of memory cells (not shown), two dummy word capacitors C20AC20B are also connected. That is, dummy word capacitor C20A is connected to bit line 3A and dummy word line 2A, and dummy word capacitor C2OB is connected to bit line 3B and dummy word line 2B. These dummy word capacitors C2OA and C2OB are used to set a reference level when the sense amplifier SNS1 operates. The precharge signal PDL is an N-channel transistor Q18.
．． Supplied to the gates of Q18A and Q18B and used to precharge and balance the bit lines. The transfer gate control signal TG is supplied to the gates of N-channel transistors Q16A and Q16B. The drive signal SEI of the sense amplifier SNS 1 is connected to the gate of the N-channel transistor Q15 and the inverter circuit IN.
It is supplied to the gate of transistor Q14 via VI. The circuits for generating these signals PDL, TG and SEI are well known and are therefore not shown in FIG.

Next, a conventional control method for the semiconductor device shown in FIG. 3 will be explained with reference to FIG. 4.

(1) Period ■ (Bit line precharge period) The bit line charge signal PDL and control signal TG are set to high level (hereinafter referred to as "H"), and the precharge transistors Q18AQ18B, Q18 and the transistor gate Q16. Turn on Q16B. In this way, a bit line precharge cycle is started. As a result,
Terminal HVC is transistor Q18A.

It is connected to bit lines 3A and 3B via Ql 8B, and maintains the level of bit lines 3A and 3B. Also, the bit line 3A is connected to the bit line 3A by the transistor Q18.

The level balance of 3B is maintained.

(2) Period ■ (memory cell information read period) In the following explanation, word line IA is selected, and charge is stored in memory cell (2) A of IA, that is, logic 1
(hereinafter referred to as "1").

When the potential of the word line IA connected to the memory cell C2]A rises, the charge stored in the memory cell C21A flows out to the bit line 3A.

That is, the potentials of the bit line 3A and the node 4A rise slightly. At this time, the potential of the dummy word line 2B is lowered to the side opposite to the selected word line across the sense amplifier. For this reason, bit line 3B and node 4B are slightly lowered, and a necessary reference potential for sense amplifier SNS 1 is provided.

As described above, a difference signal is generated at the sense amplifier input/output nodes 4A and 4B.

(3) Period■ The control signal TG is lowered, and the transistors Q16A and Q1
Cut off 6B. Therefore, the capacitance at the input/output node of the sense amplifier becomes only its own capacitance, which becomes extremely small.

(4) Period ■ (signal amplification period) Drive signal SEI is activated, and transistor Q14. Q1
By turning on 5, the sense amplifier SNS
1 to input/output nodes 4A and 4B of the sense amplifier.
amplify the difference signal occurring in the

(5) Period ■ (memory cell rewriting period) By raising the control signal TG, the transistors Q16A and Q
16B is turned on, and sense amplifier SNS 1 is connected to bit lines 3A and 3B. Then, the signal amplified in the previous period O is written into the memory cell C21A again. That is, charges flow into the memory cell C2LA via the transistors Q16A and Q7A.

FIG. 5 is a circuit diagram showing an improved version of the semiconductor memory device shown in FIG. 3, and FIG. 6 is a time chart showing a conventional control method for the semiconductor memory device shown in FIG.

The semiconductor memory device of FIG. 5 uses a sense amplifier 5NS2 in place of the sense amplifier SNS1 of FIG. 3. Sense amplifier 5NS2 is sense amplifier SNS
1, transistor 14'Q15', inverter I'N
This is the one with V2 added.

Transistor Q14. Q15 is transfer gate Q
The sense amplifier is driven when Q16A and Q16B are turned on, but depending on the dimension, the amplification speed that cuts off the transfer gate and amplifies the potential at the sense amplifier input/output node and the speed when the transfer gate is turned on are determined. There may be cases where it is not possible to achieve both the charging and discharging speed for charging and discharging the bit line. Therefore, transistors Q1 of different sizes are used to drive the sense amplifier.
4. Q14' and transistor Q15°Q15', and a small-sized transistor Q15. Two-stage amplification is performed by driving transistors Q14 and large-sized transistors Q15' and Q14' with sense amplifier drive signal SE2 and its inverted signal.

[Problems to be Solved by the Invention] In the conventional control method described above, signal amplification is started after separating the sense amplifier from the bit line, so when signal amplification starts, the capacitance at the sense amplifier input/output node is only its own capacitance. becomes extremely small. Therefore, the conventional sense amplifier becomes sensitive to noise and unbalance within the sense amplifier, resulting in a disadvantage that the sense sensitivity deteriorates.

For example, if a coupling capacitance exists between the transfer gate and the sense amplifier input/output node, the capacitance at the sense amplifier input/output node is small, causing a relatively large fluctuation in the sense amplifier input potential when the gate potential of the transfer gate falls. That is, if there is an unbalance of stray capacitance within the sense amplifier due to layout considerations, this will result in a significant reduction in the difference signal. This is particularly a serious drawback if there is an unbalanced layout in the coupling capacitance between the sense amplifier input/output node and the transfer gate.

An object of the present invention is to provide a method for controlling a semiconductor memory device that does not have the above drawbacks.

[Means for Solving the Problems] A method for controlling a semiconductor memory device of the present invention includes transferring information of a memory cell of a semiconductor memory device to a bit line pair and a pair of input/output terminals of a sense amplifier, and then driving the sense amplifier. At the same time as or after activation of the signal, a pair of transfer gates connecting the bit line pair and a pair of input/output terminals of the sense amplifier are cut off.

[Operation] The transfer gate is not cut off until at least the activation of the sense amplifier starts.

[Example 1] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a time chart showing a first embodiment of the method for controlling a semiconductor memory device of the present invention.

This embodiment is a control method for controlling the semiconductor memory device shown in FIG.

(1) Periods ■, ■ Since they are the same as those shown in FIG. 4, their explanation will be omitted.

(2) Period ■ Before the transistors Q16A and Q16B are completely cut off, the drive signal SEL of the sense amplifier SNS1 is activated to start signal amplification. That is, at the start of signal amplification, sense amplifier SNS 1 is not separated from bit lines 3A and 3B, so sense amplifier input/output node 4A
, 4B's capacity includes not only its own capacity but also the bit line capacity, and is not as light as the conventional one. Therefore,
According to this embodiment, the sensing sensitivity is improved because it is less susceptible to noise at the start of signal amplification and unbalance within the sense amplifier.

(3) Period ■ Completely cut off transistors Q16A and Q16B, completely separate sense amplifier SNS 1 from bit lines 3A and 3B, and input/output node 4 of sense amplifier SNS 1.
Signal amplification is continued with the capacitances of A and 4B being extremely small.

(4) Period■ Since it is the same as that shown in FIG. 4, the explanation will be omitted.

FIG. 2 is a time chart showing a second embodiment of the present invention.

This embodiment is a control method for controlling the semiconductor memory device shown in FIG.

(1) Periods ■, ■ Since they are the same as those shown in FIG. 4, their explanation will be omitted.

(2) Period■ Since this is the same as the embodiment shown in FIG. 1, the explanation will be omitted.

(3) Period ■ After signal amplification has been performed to some extent in period ■, the drive signal SE2 of the sense amplifier 5NS2 is activated to accelerate signal amplification.

(4) Period ■ Since it is the same as that shown in FIG. 4, the explanation will be omitted.

〔Effect of the invention〕

As explained above, the present invention is as follows. By cutting off the transfer gate after starting the activation of the sense amplifier, the capacitance of the input/output terminals of the sense amplifier will not become extremely small when signal amplification starts, thereby preventing the sense amplifier from being interfered with by noise. This eliminates deterioration of sense sensitivity due to sense amplifier capacitance imbalance. This has the effect of enabling high-speed signal amplification with good quality.

[Brief explanation of drawings]

FIG. 1 is a time chart showing a first embodiment of a method for controlling a semiconductor memory device according to the present invention, FIG. 2 is a time chart showing a second embodiment of the present invention, and FIG. 3 is a time chart showing a conventional semiconductor memory device. A circuit diagram showing an example, FIG. 4 is a time chart showing a conventional control method of the semiconductor memory device of FIG. 3, and FIG.
Circuit diagram illustrating an improved semiconductor memory device shown in Fig. 6.
This figure is a time chart showing a conventional control method for the semiconductor memory device shown in FIG. ■、■、〜■・・・period

Claims (1)

[Claims] 1. Control of a semiconductor memory device having a bit line pair to which a plurality of memory cells are connected and a pair of transfer gates respectively connecting the bit line pair to a pair of input/output terminals of a sense amplifier. In the method, after the information of the memory cell is transferred to the bit line pair and the pair of input/output terminals, the pair of transfer gates is cut off at the same time as or after activation of the sense amplifier drive signal. A method for controlling a semiconductor memory device.