JPH03282375A - Waveform display circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is applied to digital signal processing and measuring instruments. In particular, it relates to the waveform display means of this measuring instrument.

〔overview〕

The present invention converts the total number of pieces of time-series data to be processed in the same way into a displayable number in the waveform display means of a digital signal processing measuring instrument. This enables simultaneous waveform display.

[Conventional technology]

In this type of conventional circuit, when displaying a time axis waveform or a frequency spectrum on a display device, the measurement data display area is fixed, and the number of displayed data is 400 to 800 points.
set to a point. Now, the number of data required to obtain a frequency spectrum is usually selected as 1,024 points or 2,048 points due to limitations imposed by the fast Fourier transform algorithm. For example, the effective number of spectral data obtained from fast Fourier transform of 1,024 points is 400 points in the case of baseband measurement (measurement mode including DC), and in this case, the number of display data should be set to 400 points. This will not cause any problems. The configuration of a conventional circuit is shown in FIG.

[Problem to be solved by the invention]

However, such a conventional circuit has a drawback that all of the 1.024 points of time-axis data cannot be simultaneously displayed and observed within the 400-point display area.

The present invention aims to eliminate such drawbacks and to provide a waveform display device that can simultaneously display all data of one frame.

[Means to solve the problem]

The present invention provides a waveform display device including a display circuit that reads out waveform information stored in a digital storage circuit and displays it on the display device, in which the number of data that can be displayed on the horizontal axis of the display device is n, and the number of data that can be displayed on the horizontal axis of the display device is n. When the number of data to be displayed on the horizontal axis of the circuit is m (where m>n), the data stored in the digital storage circuit is read out so that the number corresponding to the horizontal axis becomes the least common multiple of m and n. an interpolation circuit that interpolates data, a low-pass filter through which the output of this interpolation circuit passes, and a decimation circuit that thins out data such that the number corresponding to the horizontal axis of the output of this low-pass filter is n. It is characterized by having the following.

Further, in the present invention, the low-pass filter includes a first low-pass filter that removes unnecessary spectral components generated in the interpolation circuit, and a second low-pass filter that prevents generation of aliasing error components in the thinning circuit. A cascade circuit with a low pass filter may be included.

[For production]

For one frame of spectrum data whose number (multiple powers of 2) is larger than the number of data pieces that can be displayed on the display device (an integral multiple of multiple powers of 2), first, calculate the least common multiple between these two data numbers. The second low-pass filter is used to remove unnecessary spectral components derived from this interpolation calculation using the first low-pass filter, and to prevent the generation of aliasing error components in the interpolation calculation. Perform a thinning operation to reduce the number of data that can be displayed from the processed results. Using this calculation result, all data of one frame can be displayed simultaneously on a CRT display device.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings.

First, the configuration of this embodiment will be explained based on FIGS. 1 and 2. This embodiment, as shown in FIG. ) input data RA that accumulates
M2, a processor 3 that performs fast Fourier transform processing on the data stored in the manual data RAM 2, and a processor 3.
An output data RAM 4 in which waveform information for one frame of data generated in is stored, a frame length conversion circuit 5 for changing the frame length of this waveform information, and an output of this frame length conversion circuit 5 (not shown). The frame length conversion circuit 5 includes an interpolation circuit 5I that interpolates the waveform information stored in the output data RAM 4, and an unnecessary spectral component from the output of the interpolation circuit 51. a first low-pass filter 52 that removes the
The second low-pass filter 53 prevents the generation of aliasing error components, and the thinning circuit 54 thins out the output of the second low-pass filter 53 to a predetermined number.

Next, the operation of this embodiment will be explained based on FIGS. 1 to 9.

The analog human input signal is converted into a digital signal by an AD converter 1, and the output of the AD converter 1 is stored in the human input data RAM 2. The data stored in the input data RAM 2 is processed by the processor 3, and the waveform information of one frame of data generated by the processor 3 is stored in the output data RAM 4. The waveform information stored in the output data RAM 4 is interpolated by an interpolation circuit 51, unnecessary spectral components are removed from the output of the interpolation circuit 51 by a first low-pass filter 52, and aliasing error components are removed by a thinning circuit 54. After passing through a second low-pass filter 53 that prevents such occurrence, the signal is decimated by a decimation circuit 54 and displayed on a CRT display device via a display circuit 6.

Here, the operation of the frame length conversion circuit 5 will be explained using a case where data of L024 points is converted to data of 640 points.

1.024=2”, 640=5 The relationship of X27 is
Since it can be expressed as 640 = 2" x 5 ÷ 23, the frame length conversion circuit 5 only needs to perform an operation to interpolate the data of 1.024 points by a factor of 5 and then thin it out to 1/8. To realize this operation, A signal sampled at the sampling frequency fil (the spectrum of this signal is shown in Fig. 3) is input to the interpolation circuit 51, and the data is interpolated five times in this interpolation circuit 51 (the spectrum of the interpolated signal is (shown in Figure 4).At this time, the sampling frequency fs
2 is five times the sampling frequency fiI, and an unnecessary spectrum appears in the result of interpolation with appropriate data (for example, zero) (the shaded area in FIG. 4 indicates an unnecessary spectrum). When the output of this interpolation circuit 51 passes through a first low-pass filter 52 having the characteristics shown in FIG.
The signal will be as shown in the figure. When the output of the first low-pass filter 52 passes through the second low-pass filter 53 having the characteristics shown in FIG. 7, it becomes a signal shown in FIG. 8. This second low-pass filter 53
The output of is decimated to 1/8 to become a signal with the spectrum shown in Fig. 9, and the resulting sampling frequency fs
3 is one-eighth of five times the sampling frequency Ll.

The spectra indicated by dotted lines in FIGS. 3 to 9 represent aliasing spectra generated by sampling.

In addition, in this example, the case where data of 1.024 points is converted to data of 640 points was explained, but 1.024 points data is converted to data of 640 points.
When converting point data to 400 point data, 4
The present invention can be carried out by interpolating by a factor of 25 using the relationship 00=2''×52÷26 and then thinning out to 1/64.

〔Effect of the invention〕

As explained above, the present invention provides two
By converting the total number of time-series data for one frame into the number of pieces that can be displayed in the measurement data display area of the display device and displaying them simultaneously, the effect of making it easier to comprehensively understand the measurement data on the time axis. There is.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a block configuration diagram showing the configuration of the frame length conversion circuit of FIG. 1. FIG. 3 is a spectrum diagram of the human input signal of the interpolation circuit shown in FIG. FIG. 4 is a spectrum diagram of the output signal of the interpolation circuit of FIG. 2. FIG. 5 is a characteristic diagram showing the characteristics of the first low-pass filter of FIG. 2. FIG. 6 is an output vector diagram of the first low-pass filter in FIG. 2. FIG. 7 is an explanatory diagram showing the characteristics of the second low-pass filter shown in FIG. 2. FIG. 8 is an output vector diagram of the second low-pass filter in FIG. 2. FIG. 9 is an output vector diagram of the thinning circuit shown in FIG. FIG. 10 is a block configuration diagram showing the configuration of a conventional example. ■...AD converter, 2...Input data RAM, 3...
... Processor, 4... Output data RAM, 5... Frame length conversion circuit, 6... Display circuit, 51... Interpolation circuit, 52... First low-pass filter, 53... Second low-pass filter, 54...interbow circuit.

Claims (1)

[Scope of Claims] 1. A waveform display device comprising a display circuit (6) that reads out waveform information stored in a digital storage circuit (4) and displays it on a display device, comprising: data that can be displayed on the horizontal axis of the display device; When the number of data to be displayed on the horizontal axis of the digital storage circuit is n and the number of data to be displayed on the horizontal axis of the digital storage circuit is m (where m>n), read the data stored in the digital storage circuit and display the number corresponding to the horizontal axis. An interpolation circuit that interpolates data so that is the least common multiple of m and n, a low-pass filter through which the output of this interpolation circuit passes, and a number corresponding to the output of this low-pass filter on the horizontal axis is n. 1. A waveform display circuit comprising: a thinning circuit that thins out data so that the data is thinned out. 2. The low-pass filter includes: a first low-pass filter that removes unnecessary spectral components generated in the interpolation circuit, and a second low-pass filter that prevents generation of aliasing error components in the thinning circuit. 2. The waveform display circuit according to claim 1, further comprising a cascade connection circuit.