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JPH0330419U - - Google Patents

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Publication number
JPH0330419U
JPH0330419U JP7692589U JP7692589U JPH0330419U JP H0330419 U JPH0330419 U JP H0330419U JP 7692589 U JP7692589 U JP 7692589U JP 7692589 U JP7692589 U JP 7692589U JP H0330419 U JPH0330419 U JP H0330419U
Authority
JP
Japan
Prior art keywords
layer
pulse transformer
secondary winding
primary winding
winding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7692589U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7692589U priority Critical patent/JPH0330419U/ja
Publication of JPH0330419U publication Critical patent/JPH0330419U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Coils Or Transformers For Communication (AREA)
  • Power Conversion In General (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例の基本的な構成を
示す断面図、第2図は第1図および第3図にそれ
ぞれ示されたパルストランスを第7図図示のイン
バータ回路に適用した場合における第7図のトラ
ンジスタQ1のゲート電流波形を示す波形図、第
3図はこの考案の他の実施例の基本的な構成を示
す断面図、第4図はこの考案のさらに他の実施例
の斜視図、第5図は第4図図示のパルストランス
に用いられるプリント基板の平面図、第6図はそ
の積層態様を示す説明図、第7図はインバータ回
路の基本的な構成を示す電気回路図、第8図およ
び第9図は従来技術をそれぞれ示す断面図、第1
0図は第8図および第9図にそれぞれ示されたパ
ルストランスを第7図のインバータ回路に適用し
た場合におけるトランジスタQ1のゲート電流波
形を示す波形図である。 30,40……コイルボビン(磁心)、31,
41……一次側巻線、32,42……二次側巻線
、33,43……絶縁テープ(絶縁層)。
Figure 1 is a sectional view showing the basic configuration of an embodiment of this invention, and Figure 2 is a case in which the pulse transformers shown in Figures 1 and 3 are applied to the inverter circuit shown in Figure 7. 7 is a waveform diagram showing the gate current waveform of transistor Q1 in FIG. 7, FIG. 3 is a sectional view showing the basic configuration of another embodiment of this invention, and FIG. A perspective view, FIG. 5 is a plan view of a printed circuit board used in the pulse transformer shown in FIG. 4, FIG. 6 is an explanatory diagram showing its laminated form, and FIG. 7 is an electric circuit showing the basic configuration of an inverter circuit. 8 and 9 are cross-sectional views showing the prior art, respectively.
FIG. 0 is a waveform diagram showing the gate current waveform of transistor Q1 when the pulse transformers shown in FIGS. 8 and 9 are applied to the inverter circuit of FIG. 7. 30, 40... Coil bobbin (magnetic core), 31,
41... Primary winding, 32, 42... Secondary winding, 33, 43... Insulating tape (insulating layer).

Claims (1)

【実用新案登録請求の範囲】 (1) 高周波駆動信号をパワーMOSFETのゲ
ートに伝達させるパルストランスにおいて、 磁心に絶縁層を介在させて1層ずつ交互に積層
した一次側巻線および二次側巻線を備え、 1層おきに積層された各一次側巻線および各二
次側巻線をそれぞれ直列に接続したことを特徴と
するパルストランス。 (2) 高周波駆動信号をパワーMOSFETのゲ
ートに伝達させるパルストランスにおいて、 磁心に絶縁層を介在させて1層ずつ交互に積層
した一次側巻線および二次側巻線を備え、 1層おきに積層された各一次側巻線および各二
次側巻線をそれぞれ並列に接続したことを特徴と
するパルストランス。
[Scope of Claim for Utility Model Registration] (1) In a pulse transformer that transmits a high-frequency drive signal to the gate of a power MOSFET, a primary winding and a secondary winding that are alternately laminated layer by layer with insulating layers interposed in the magnetic core. 1. A pulse transformer characterized in that each primary winding and each secondary winding, which are laminated every other layer, are connected in series. (2) A pulse transformer that transmits a high-frequency drive signal to the gate of a power MOSFET is equipped with a primary winding and a secondary winding that are alternately laminated one layer at a time with an insulating layer interposed between the magnetic core, and every other layer is A pulse transformer characterized in that each stacked primary winding and each secondary winding are connected in parallel.
JP7692589U 1989-06-27 1989-06-27 Pending JPH0330419U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7692589U JPH0330419U (en) 1989-06-27 1989-06-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7692589U JPH0330419U (en) 1989-06-27 1989-06-27

Publications (1)

Publication Number Publication Date
JPH0330419U true JPH0330419U (en) 1991-03-26

Family

ID=31618833

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7692589U Pending JPH0330419U (en) 1989-06-27 1989-06-27

Country Status (1)

Country Link
JP (1) JPH0330419U (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001525607A (en) * 1997-11-28 2001-12-11 エービービー エービー Transformer
JP2003086428A (en) * 2001-09-07 2003-03-20 Sumida Corporation Pulse transformer
JP2010534947A (en) * 2007-08-01 2010-11-11 エプコス アクチエンゲゼルシャフト Current compensation choke and circuit device having current compensation choke
JP2012227331A (en) * 2011-04-19 2012-11-15 Mitsubishi Electric Corp Power supply device and lighting fixture having the same
JP2017017062A (en) * 2015-06-26 2017-01-19 Tdk株式会社 Pulse transformer
WO2024176532A1 (en) * 2023-02-24 2024-08-29 パナソニックIpマネジメント株式会社 Inductor

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001525607A (en) * 1997-11-28 2001-12-11 エービービー エービー Transformer
JP2003086428A (en) * 2001-09-07 2003-03-20 Sumida Corporation Pulse transformer
JP2010534947A (en) * 2007-08-01 2010-11-11 エプコス アクチエンゲゼルシャフト Current compensation choke and circuit device having current compensation choke
US9305695B2 (en) 2007-08-01 2016-04-05 Epcos Ag Current-compensated choke and circuit arrangement with a current-compensated choke
JP2012227331A (en) * 2011-04-19 2012-11-15 Mitsubishi Electric Corp Power supply device and lighting fixture having the same
JP2017017062A (en) * 2015-06-26 2017-01-19 Tdk株式会社 Pulse transformer
WO2024176532A1 (en) * 2023-02-24 2024-08-29 パナソニックIpマネジメント株式会社 Inductor

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