JPH0352189A - Dynamic random access memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention relates to semiconductor memory, and particularly to word line/dummy word line driving in dynamic random access memory (hereinafter abbreviated as DRAM). system and dummy cell precharge means.

(Prior Art) Fig. 3 shows a part of a word line/dummy word line drive system in a conventional DRAM, in which BL1 and BL2 are bit line pairs in each column in a DRAM memory cell array, and SA is a bit line pair in each column in a DRAM memory cell array. Bit line sense amplifier, MCi (
i-os+...n) is connected to each bit line (BL, ,B
A plurality of regular dynamic memory cells are connected to each of the bit lines BL and BL, respectively, but only the bit line BL side is shown for the sake of simplification of explanation. These regular memory cells MCj are insulated gate field effect transistors (
A charge transfer transistor T consisting of a MOS transistor
M and a capacitor Cs are connected in series. WLf
(f-ost, . . . n) is a word line connected to the gate of the charge transfer transistor TM of the memory cell MCi, and RD is a row decoder that selectively drives the word line WLi.

DC is a dummy cell connected to each bit line (BL1, BL2), but only the bit line BL2 side is shown to simplify the explanation. These dummy cells DC include a charge transfer transistor TM and a capacitor Cd connected in series. DWL is dummy cell D
A dummy word line 30 is connected to the gate of the charge transfer transistor TM of C, and a dummy word line drive circuit 30 selectively drives the dummy word line DWL. 31 is a row system drive circuit to which the row address and row address strobe signal RAS are input; 32 is a row decoder R that applies a boosted voltage of the vCC power supply voltage to the output of the row system drive circuit 31;
This is a booster circuit that is supplied as a drive input for D and dummy word line moving circuits 30. This booster circuit 32 controls the gate threshold voltage Vt of the fU1 load transfer transistor TM during writing to the memory cell MCi and the dummy cell DC.
Since a voltage drop of n occurs, it is provided to compensate for this, and is configured to output a voltage boosted to Vcc+Vtn or higher.

These memory cells MCi and D. When writing to the memory cell DC, the capacitance of the capacitor Cd of the dummy cell DC is equal to the memory cell MC so that the amount of charge written to the dummy cell DC is 1/2 of the amount of charge written to the memory cell MCi.
It is set to 1/2 of the capacitance of capacitor Cs of i.

As a result, when reading from memory cell MCi and dummy cell DC, the potential of one bit line on the memory cell MCi side is set to "H2" according to the data of memory cell MCi.
level or "L2 level", and the potential of the other bit line on the dummy cell side becomes an intermediate potential between the "H" level and "L" level, so that the sense amplifier SA can perform the sensing operation.

Note that a bit line precharge/equalization circuit (not shown) is used to precharge and equalize each bit line pair (BL+, BL2) to 1/2 of the power supply voltage VCC after the rewriting is completed using the sense output of the sense amplifier SA. is provided.

Next, a potential of OV ("L2 level") is written to a certain memory cell MCo connected to one of the bit line pair (BL, BL2) of the DRAM, for example, the first bit line BL side. The read/rewrite operations in the case where the

In this DRAM, the power supply potential VCC is, for example, 5V,
Since a method is adopted in which the bit line pair is precharged to a voltage of Vcc/2, each bit line (BL1BL2) is maintained at the same voltage (Vec/2) until a word line is selected. Row address and column address are input sequentially as address input, and R
The AS signal is activated, the row address is decoded by the row-related drive circuit 31, a boosted voltage is applied to the selected word gland WLo on the side of the first bit IIBL, and the charge transfer transistor TM of the selected memory cell MCO is turned on. , the "L" level is read from the capacitor Cs of this memory cell MCo, and the potential of the first bit line BL is Vcc/2.
decreases slightly from

On the other hand, at the same time as the word line WLo on the first bit line BLI side is selected, a boosted voltage is applied to the dummy word line DWL on the second bit line BL2 side, and the charge transfer transistor TM of the dummy cell DC is turned on. . Here, since the potential Vcc/2 is written in advance in the dummy cell DC, even if the charge transfer transistor TM is turned on and the capacitor Cd of the dummy cell DC and the second bit line BL2 are short-circuited, both are at the same potential, so the potential of the second bit line BL2 remains unchanged at Vcc/2.

After this, after a slight potential difference occurs between the potential of the first bit line BL1 and the potential of the second bit line BL2, the sense amplifier SA is activated and the slight potential difference between the bit line pair is sense-amplified. .

Thereafter, when the column address strobe signal is activated and the column address is decoded, and the column selection transistor pair (not shown) is turned on by the column decode signal, the output potential of the sense amplifier SA is passed through the data line to the data buffer ( (not shown) and output to the data path.

Furthermore, the selected memory cell MC. Then, rewriting is performed to the dummy cell DC. After this, word line WL. and dummy word line DWL
returns to unselected state. After this rewrite operation is finished,
The bit line pair (BL, BL2) is precharged.

However, in the above DRAM, the boosting circuit 32 needs to supply a boosted voltage to the row decoder RD and the dummy word line drive circuit 30, which increases its burden. Therefore, if the booster circuit 32 is not provided with a strong boosting ability, the boosting time will be increased and the operating speed of the DRAM will be slowed down, and in the worst case, the voltage will not be able to be boosted completely. If so, the circuit area will increase.

(Problems to be Solved by the Invention) As described above, in conventional large-capacity DRAMs, the load on the booster circuits for boosting word lines and dummy word lines is heavy, and the boosting time is increased, which reduces the operating speed of the DRAM. There are problems in that the speed becomes slow or the circuit area of the booster circuit becomes large.

The present invention has been made to solve the above problems, and its purpose is to reduce the burden on the booster circuit of the word line drive system,
The object of this invention is to provide a dynamic random access memory that can reduce the circuit area of a booster circuit and increase the operating speed. [Structure of the Invention] (Means for Solving the Problem) The dynamic random access memory of the present invention supplies the boosted voltage output of the booster circuit to the word line drive circuit, but not to the dummy word line drive circuit. When a regular memory cell is selected, the word line drive circuit outputs a boosted word line signal, but when a dummy cell is selected, the dummy word line drive circuit outputs a dummy word line signal that is not boosted, thereby precharging the dummy cell. The present invention is characterized in that it includes a dummy cell precharge circuit that precharges the capacitor of the dummy cell via the dummy cell precharge transistor without driving the dummy word line.

(Function) Since a dummy cell precharge circuit is provided that precharges the capacitor of the dummy cell without driving the dummy word line, there is no need to output a boosted dummy word line signal from the dummy word line drive circuit. , there is no need to supply a boosted voltage from the booster circuit to the dummy word line drive circuit. Therefore, it is possible to reduce the burden on the booster circuit of the word line drive system, suppress the circuit area of the booster circuit, and increase the operating speed of the DRAM.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of the DRAM of the present invention,
Compared to the conventional DRAM as described above with reference to FIG. The output of the row-related drive circuit 12 is input to the word line drive circuit 11 without passing through the booster circuit 10;
b) The capacitance value of the capacitor Cd of the dummy cell DC is equivalent to the capacitance value of the capacitor Cs of the regular memory cell MCi. The difference is that a dummy cell precharge circuit 13 for precharging to a potential of 1/2 of the power supply voltage is added, and other parts are the same and are designated by the same reference numerals as in FIG. 3.

That is, BL and BL2 are the bit line pairs of each column in the DRAM memory cell array, SA is the bit line sense amplifier, and M C i is the bit line pair tm (BL,
, BL2), each of which has a charge transfer transistor TM and a capacitor Cs connected in series. WLi is the charge transfer transistor T of the memory cell MCi
The word line RD connected to the gate M is a row decoder (word line drive circuit) that selectively drives the word line WLi. DC is a dummy cell connected to each bit line (BLl, BL2), and each has a charge transfer transistor TM and a capacitor Cd connected in series.

DWL is a dummy word line connected to the gate of the charge transfer transistor TM of the dummy cell DC, and 11 is a dummy word line drive circuit that selectively drives the dummy word line DWL. 12 is a row system drive circuit which manually generates a row address and a row address strobe signal RAS; 10 is a Vec electric field Fi. This booster circuit supplies a voltage obtained by boosting the 'rjX voltage to Vcc+Vtn or more as a drive input to the row decoder RD based on the output of the row system drive circuit 12.

Further, in the dummy cell precharge circuit 13, a dummy cell precharge power supply Vdc is connected to a connection point between the charge transfer transistor TM and the capacitor Cd of the dummy cell DC via a dummy cell precharge MOS transistor DP, A bit line precharge/equalization signal EQ is applied to the gate of transistor DP (MOS). Here, the dummy cell precharge power supply Vdc is the power supply voltage Vec
However, as mentioned above, the capacitance value of the capacitor Cd of the dummy cell DC is equal to the capacitance value of the capacitor Cs of the regular memory cell MCi, so the dummy cell precharge transistor DP is When turned on, the capacitor Cd of the dummy cell DC becomes Vec/2.
It becomes possible to precharge to the potential of Note that the capacitance value of the capacitor Cd of the dummy cell DC is equal to the capacitance value of the capacitor Cs of the regular memory cell MCi, which is advantageous in terms of the process.

Next, the operation of the DRAM will be explained with reference to the waveforms shown in FIG. The operation of this DRAM is basically the same as that of the conventional DRAM as described above with reference to FIG. 3, so a detailed description thereof will be omitted, but the following points are different.

That is, in the above DRAM, when the bit line precharge/equalize signal EQ is activated after the read/rewrite operation or the write operation, the bit line precharge/equalize circuit (not shown) activates the bit line pair (BL1,
At the same time, the dummy cell precharge circuit 13 precharges the dummy cell DC
The capacitor Cd of is precharged to a potential of Vcc/2. Therefore, in the operation of the next cycle, the boosted word line signal output from the row decoder RD selects the transistor TM of the selected memory cell on one bit line BL, and the boosted word line signal output from the dummy word line drive circuit 11 is selected. The transistor TM of the selected dummy cell on the other bit line BL2 side is selected by the dummy word line signal that is not boosted.

Note that since the capacitor Cd of the dummy cell DC is precharged to the potential of Vcc/2, the memory cell MCi
When data is read from the dummy cell DC, the potential of the other bit line BL2 from which the data of the dummy cell DC is read is an intermediate potential with respect to the potential of the one bit line BL from which the data of the memory cell MCi is read.

Note that in the above embodiment, the dummy cell precharge circuit 1
3, the capacitor Cd of the dummy cell DC is set to Vcc/2.
The pair of bit lines (BL, BL2) are precharged to the potential of Vcc/ by the bit line precharge circuit.
Although the example in which the bit line precharge circuit 13 precharges the capacitor Cd of the dummy cell DC to the potential Vcc/2 is shown, the present invention is not limited to this. The bit lines (BL, BL2) may be precharged to the power supply voltage Vec or the ground potential VSS.

Further, in the present invention, when the sense amplifier SA operates, the bit line pair (B
The sense amplifier SA
and the bit line pair (BLI BL2), or between the N channel sense amplifier and P that constitute the sense amplifier SA.
It is also applicable to a DRAM in which a charge transfer transistor is inserted between a channel sense amplifier.

[Effects of the Invention] As described above, according to the DRAM of the present invention, the dummy cell precharge circuit that precharges the capacitor of the dummy cell without driving the dummy word line is provided, so there is no need to boost the voltage of the dummy word line. This eliminates the burden on the bamboo pressure circuit of the word line drive system, and reduces the circuit area of the boosted voltage. In addition, when selecting a regular word line, the dummy word line is selected without going through the booster circuit, so the dummy word line is selected earlier than the regular word line, and the dummy word line is selected faster than the regular word line. By selection, the circuit operation is no longer time-limited, and the operation speed is substantially increased.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a part of a DRAM according to an embodiment of the present invention, and FIG. 2 is a diagram showing waveform examples of a boosted word line signal and a non-boosted dummy word line signal in the DRAM of FIG. 1. , FIG. 3 is a circuit diagram showing a part of a conventional DRAM. BL,,BL2...bit line, MCi...memory cell, WLi...word line, DC...dummy cell, D
WL... dummy word line, SA... bit line sense amplifier, RD... row decoder, 1o... booster circuit, 11... dummy word line drive circuit, 12... row system drive circuit, 13...Dummy cell precharge circuit.

Claims (3)

[Claims] (1) In a dynamic random access memory, by supplying the boosted voltage output from the booster circuit to the word line drive circuit but not to the dummy word line drive circuit, the output from the word line drive circuit is removed when a regular memory cell is selected. outputs a boosted word line signal, but when a dummy cell is selected, the dummy word line drive circuit outputs a dummy word line signal that is not boosted, and when precharging a dummy cell, the dummy cell precharge is performed without driving the dummy word line. A dynamic random access memory comprising a dummy cell precharge circuit that precharges a capacitor of a dummy cell via a transistor. (2) The dynamic random access memory according to claim 1, wherein the capacitance value of the capacitor of the dummy cell is equal to the capacitance value of the capacitor of the regular memory cell. (3) The dummy cell precharge circuit precharges the capacitor of the dummy cell to a potential of 1/2 of the power supply voltage, and the bit line precharge circuit further connects a complementary pair to the regular memory cell and the dummy cell. 3. The dynamic random access memory according to claim 1, wherein the bit line of the dynamic random access memory is precharged to a potential half of the power supply voltage.