JPH0358149A - Storage device - Google Patents

Abstract

PURPOSE:To practically shorten the access cycle time by providing a high-speed memory part and an extended memory part and performing the same control as a cache memory with an address array by the former. CONSTITUTION:Contents of an address array 10 are retrieved by a request address 100 from a central processing unit or the like; and when an address corresponding to the request address 100 exists in the address array 10, data is read out from a high-speed memory part 20. When it does not exist there, data is read out from an extended memory part 30 and is not only sent to the central processing unit or the like as read data 300 but also written in the high-speed memory part 20 through a data selector 40, and the corresponding address is registered in the address array 10. Thus, the access cycle time is practically shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a storage device, and particularly to a storage device that is divided into a high-speed memory section and an extended memory section.

[Conventional technology]

As shown in FIG. 2, a conventional storage device stores a memory section 50 composed of a RAM element, a request address 100 from a central processing unit, write data 200, and read data 3.
00.

The memory unit 50 is generally composed of several thousand RAM elements in a large computer system.

The access time and cycle time of a storage device are factors that determine the performance of a computer system, and the smaller the better, but the access time and cycle time of this storage device are determined by the sum of the access time and cycle time of the RAM element itself and the signal propagation time. It can be determined by

The propagation time of the above signal has become large in large computer systems due to the need to distribute addresses to thousands of RAM elements, and is now equivalent to the access time of a RAM element, or They tend to become larger.

For example, while the access time of a RAM element is 100 ns, the signal propagation time is 120 ns, and the access time of a storage device ends up being 220 ns.

[Problem to be solved by the invention]

In the conventional storage device described above, the proportion of the signal propagation time in the access time of the storage device is increasing. On the other hand, the execution time per instruction in computer systems is becoming smaller; for example, even in microprocessors, it is 50 ns, and the signal propagation time is decreasing.
It has the disadvantage that it affects the instruction execution time of the processor, increasing the instruction execution time and reducing the performance of the computer system.

[Means to solve the problem]

The storage device of the present invention has an address array that is a set of addresses indicating whether or not there is data corresponding to a request address from the central processing unit, etc. in the storage device where data is continuously transferred and written between the central processing unit and the like. a comparator that compares the contents of the address array and the request address to see if they are the same; a high-speed memory section in which data is written and read if the outputs of the comparator match; When the outputs do not match and the target data does not exist in the high-speed memory section, data is written and read in the extended memory section, which is made up of the same RAM elements as the high-speed memory section, and at the same time data is written to and read from the high-speed memory section. The address array has means for transferring the data and updating the address array. [Example] Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which a high-speed memory section 20 composed of the same RAM element, an expansion memory section 30, and functions equivalent to a cache control section used in a cache memory, etc. In order to write data from the extended memory section 30 to the high speed memory section when there is no target data in the address array 10 and the high speed memory section 20,
It consists of a data selector 40 for selecting data from a central processing unit or the like.

Next, the operation of the present invention will be explained.

The contents of the address array 10 are searched based on the request address 100 from the central processing unit or the like, and if the address corresponding to the request address 100 is contained in the address array 10, data is successively outputted from the high speed memory section 20.

If the address corresponding to the request address 100 is not included in the address array 10, the data is read from the extended memory unit 30 and read as read data 300.
By sending the data to the central processing unit, etc., writing it to the high-speed memory unit 20 through the data selector 40, and registering the corresponding address in the address array 10, data from the high-speed memory unit 20 is sent to the next request address 100. Reading can be performed at high speed. A write operation is performed in the same way.

The high-speed memory section 20 and the extended memory section 30 are composed of the same RAM element, the high-speed memory section 20 is composed of a small number of RAM elements, and the extended memory section 30 is composed of a large number of RAM elements (the memory section 50 in FIG. same degree).

By taking the above-mentioned precautions, the high-speed memory unit 20
The access time is several + ns shorter than that of the memory unit 50 in the figure, and the access time of the storage device of FIG. 1 is several +ns shorter than the access time of the storage device of FIG. 2.

〔Effect of the invention〕

As explained above, the present invention has a high-speed section and an extension section in the storage device, and the high-speed section is controlled in the same way as cache memory by an address array, thereby substantially reducing access time and cycle time. It is possible to configure a storage device with high performance. Furthermore, by configuring the high-speed section and the expansion section with the same RAM element, a large-capacity, high-speed storage device can be produced at a lower cost than using an expensive, low-capacity RAM element such as that used in a cache memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional example. 10... address array, 20... high speed memory section,
30... Expansion memory section, 40... Data selector,
50...Memory section, 100...Request address, 200...Write data, 300...Read data.

Claims (1)

[Claims] In a storage device that reads and writes data between a central processing unit and the like, an address array that is a set of addresses indicating whether there is data corresponding to a request address from the central processing unit, etc., and the contents of the address array. a comparator that compares whether the request addresses are the same; a high-speed memory section that writes and reads data when the outputs of the comparator match; and a high-speed memory section that writes and reads data automatically when the outputs of the comparator do not match. means for writing and reading data in an extended memory section constituted by the same RAM element as the high speed memory section when there is no data, and at the same time transferring the data to the high speed memory section and updating the address array. A storage device comprising: