JPH0359522A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To prevent the leakage of light through a spacer material by providing the spacer material for making the thickness between substrates constant and constituting the spacer material of a material for forming color filter. CONSTITUTION:The device is constituted of a transparent glass substrate(color filter substrate) SUB2 where the color filter is formed, a light shielding film BM for preventing light from being made incident on a thin film transistor (TFT), the color filter FIL1 for a 1st color, the color filter FIL2 for a 2nd color, the color filter FIL3 for a 3rd color and the spacer SP consisting of the color filters for the 2nd color and the 3rd color. Therefore, thickness of liquid crystal LC is regulated by thickness obtained by adding the thickness (d) of the color filters FIL2 and 3 to the thickness of the gate line of a lower transparent glass substrate SUB1 or the projecting part of a drain line GDL. Thus, the leakage of the light caused by the spacer material does not occur and a point defect and the lowering of contrast ratio are prevented.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a liquid crystal display device, and particularly to a spacer material for an active matrix type liquid crystal display device using thin film transistors and the like. [Prior Art] An active matrix type liquid crystal display device is one in which a nonlinear element (switching element) is provided corresponding to each of a plurality of pixel electrodes arranged in a matrix. Since the liquid crystal in each pixel is theoretically always open (duty ratio 1.0), a time-division opening method is adopted. The active method has better contrast than the so-called simple matrix method, and is becoming an indispensable technology, especially in color. A typical switching element is a thin film transistor (TPT). As shown in FIG. 11, in order to keep the thickness of the liquid crystal layer LC sealed between the upper and lower transparent glass substrates SUB1.5UB2 constituting the liquid crystal display section of the liquid crystal display device constant, a spacer material SP is provided between the two substrates. However, conventionally, the upper transparent glass substrate 5UB on which the color filter FIL is formed
Small spherical or cylindrical spacer materials SP were dispersed over the entire display screen of either 2 or the lower transparent glass substrate 5UBI on which thin film transistors (not shown) were formed. The active matrix liquid crystal display device using TPT is described in, for example, "L2.5-type active matrix color liquid crystal display employing redundant configuration", Nikkei Electronics, pp. 193-210, 1986.
It is known for being published by Nikkei McGraw-Hill on February 15th. [Problems to be Solved by the Invention] Since transparent small spherical or cylindrical spacer materials made of plastic or glass are dispersed over the entire display screen of a transparent glass substrate, the spacer materials cannot be provided at desired positions. Furthermore, since the spacer material is transparent, light leaks through the spacer material, and if the spacer material has a high dispersion density or is densely packed, there are problems in that point defects occur and the contrast ratio decreases. An object of the present invention is to provide a liquid crystal display device that can prevent light leakage through a spacer material. [Means for Solving the Problems] In order to solve the above problems, the liquid crystal display device of the present invention includes a first transparent substrate on which a color filter is formed, and a second transparent substrate.
a transparent substrate, a liquid crystal sealed between the first transparent substrate and the second transparent substrate, and a spacer material for making the thickness between the two substrates constant, and the spacer material is characterized in that it is made of the color filter forming material described above. FIGS. 1A and 1B schematically show an example of a cross-sectional structure of a liquid crystal display device of the present invention. In FIG. 1(A), 5UB2 is an upper transparent glass substrate (color filter substrate) on which a color filter is formed;
BM is a light-shielding film that prevents light from entering the TPT, and FILL is the first color filter. FIL2 is the second color filter, FIL3 is the third color filter
The color filter SP is a spacer composed of a second color filter and a third color filter. Figure 1 (B) is a diagram of the combination of the upper and lower boards, with 5UB
I is a lower transparent glass substrate (TFT substrate) on which TPT (not shown) is formed, and GDL is a gate line or a drain line. The thickness of the liquid crystal LC is the sum of the thickness d of the second color filter FIL2 and the third color filter FIL3 and the thickness of the convex portion of the gate line or drain line GDL of the lower transparent glass substrate SUB1. is specified. [Function] In the liquid crystal display device of the present invention, since the spacer material is composed of a color filter, the spacer material can be provided at a desired position, and can be placed on a portion that does not affect the display, for example, on a light shielding film on a color filter substrate, Alternatively, it can be formed on the color filter substrate corresponding to the gate line or drain line on the TPT substrate, so there is no light leakage due to the spacer material.
There is no possibility that the spacer material has a high dispersion density or that the spacer material is crowded together, so that no point defects occur or the contrast ratio decreases. Other objects and features of the invention will become apparent from the following description with reference to the drawings. [Example] Below, the configuration of the present invention will be described together with an example in which the present invention is applied to an active matrix color liquid crystal display device. In addition, in an attempt to explain the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof will be omitted. FIG. 2A is a plan view showing one pixel and its surroundings of an active matrix color liquid crystal display device to which the present invention is applied, and FIG. 2B is a cross section taken along the nB-nB cutting line in FIG. 2A and a plan view of the display panel. 2C is a cross-sectional view taken along the uc-nc line in FIG. 2A; FIG. Moreover, FIG. 3 (main part plan view) shows a plan view when a plurality of pixels shown in FIG. 2A are arranged. (Pixel Arrangement) As shown in Figure 2A, each pixel is connected to two adjacent scanning signal lines (gate signal line or horizontal signal line) GL and two adjacent video signal lines (drain signal line or vertical signal line). Signal AI
X) D It is arranged within the intersection area with L (inside the area surrounded by four signal lines). Each pixel is a thin film transistor T
Including PT, pixel electrode TO1 and additional capacitance Cadd,
The scanning signal lines OL extend in the column direction, and a plurality of scanning signal lines OL are arranged in the row direction. The video signal lines DL extend in the row direction, and a plurality of video signal lines DL are arranged in the column direction. (Overall panel cross-sectional structure) As shown in FIG. 2B, a thin film transistor TPT and a transparent pixel electrode ITOI are formed on the lower transparent glass substrate 5UBI side with respect to the liquid crystal layer LC, and the upper transparent glass substrate 5
On the UB2 side, a color filter FIL and a light shielding black matrix pattern BM are formed. The lower transparent glass substrate 5UBl side has a thickness of, for example, about 1.1 [mm]. The central part of Figure 2B shows a cross section of one pixel,
The left side shows a cross section of the left edge portion of the transparent glass substrates 5UBI and 5UB2 where external lead wiring is present. The right side shows a cross section of the right edge portion of the transparent glass substrates 5UBI and 5UB2 where no external output wiring is present. The sealing material SL shown on the left and right sides of FIG. 2B is configured to seal the liquid crystal LC, and the liquid crystal sealing opening (
Transparent glass substrates 5UBI and 5 excluding (not shown)
It is formed along the entire circumference of UB2. The sealing material SL is made of, for example, epoxy resin. The common transparent pixel electrode ITO2 on the side of the upper transparent glass substrate 5UB2 is connected to an external lead wiring formed on the side of the lower transparent glass substrate 5UBI with a silver paste material SIL at at least one place. This external lead wiring is formed in the same manufacturing process as each of the gate electrode GT, source electrode SDI, and drain electrode SD2 described above. Alignment films 0RII and 0RI2, transparent pixel electrode ITo, common transparent pixel electrode ITO1 protective films PSVI and PSV2,
Each layer of the insulating film GI is formed inside the sealing material SL. The polarizing plate POL has a lower transparent glass substrate 5UBI,
It is formed on each outer surface of the upper transparent glass substrate 5UB2. Liquid crystal LC has a lower alignment film ○R that sets the direction of liquid crystal molecules.
II and the upper alignment film 0RI2, and sealed by a sealing portion SL. The lower alignment film 0RII is the lower transparent glass substrate 5tJBl.
The protective film PSVI is formed on the side protective film PSVI. On the inner surface (liquid crystal side) of the upper transparent glass substrate 5UB2, a light shielding film BM, a color filter FIL, and a protective film PSV are provided.
2. A common transparent pixel electrode (COM) IrO2 and an upper alignment film 0RI2 are sequentially laminated. In this liquid crystal display device, the lower transparent glass substrate 5UBl, the side and two upper transparent glass substrates 5UB are formed separately, and then the upper and lower transparent glass substrates 5UBI and 5UB are formed separately.
2 are stacked on top of each other and a liquid crystal LC is sealed between the two. (Light-shielding film BM> A shielding film BM is provided on the upper substrate 5UBZ side to prevent external light (light from above in FIG. 2B) from entering the i-type semiconductor layer AS used as a channel formation region, The pattern is as shown by the hatching in Fig. 6. Note that Fig. 6 shows the ITO film IWd3 in Fig. 2A.
, is a plan view depicting only the filter layer FIL and the light shielding film BM. The light-shielding film BM is formed of, for example, an aluminum film or a chromium film that has a high light-shielding property, and in this embodiment, the chromium film is formed by sputtering to a thickness of approximately 1300 mm. Therefore, the common semiconductor NAs of the TPTs 1 to 3 is sandwiched between the upper and lower light shielding films BM and the thick gate electrode GT, and that portion is not exposed to external natural light or backlight light. The light shielding 11BM is shown by the hatched part in FIG. The light shielding film BM is formed around the JNJ of the pixel, that is, the light shielding film BM is formed in a lattice shape (black matrix), and the effective display area of one pixel is partitioned by this lattice. Therefore, the outline of each pixel becomes clear due to the light shielding film BM, and the contrast is improved. In other words, the light shielding film BM has two functions: shielding the semiconductor layer As from light and serving as a black matrix. In addition, the backlight is installed on the 5UBZ side, and the 5UBI
can also be set as the observation side (externally exposed side). (Spacer) As shown in Figure 2B, the spacer material SP is the second color (
In other words, it is a part that does not affect the display, and is composed of a green color filter FIL (G) (formed second) and a blue color filter FIL (B) (formed third). , upper transparent glass substrate 5UB
On the light shielding film BM on Z and on the lower transparent glass substrate 5UBI
It is formed on the upper transparent glass substrate 5UBZ corresponding to the drain line (or gate g) of. Therefore, there is no light leakage caused by the spacer material as in the past, there is no high dispersion density of the spacer material, there is no possibility that the spacer material is densely packed, and there is no point defect or decrease in contrast ratio. A liquid crystal display device with high display quality can be provided. The method for forming the spacer material SP will be described in the following section (Color filter FIL). (Color filter FIL) Color filter FIL is made by adding dye to a dyed base material made of a resin material such as acrylic resin. The color filter FIL is formed in a dot shape for each pixel at a position facing the pixel (FIG. 7), and is colored differently (FIG. 7 is the third conductive film in FIG. 3, l1d3). (The R, G, and B filters are hatched at 45°, 135', and a cross, respectively), and the color filter FIL is connected to the pixel electrode as shown in Figure 6. The light shielding film BM is formed to be thick so as to cover all of the ITOI (El-R3), and the light shielding film BM is formed inside the peripheral part of the pixel electrode ITOI so as to overlap with the color filter FIL and the edge part of the pixel electrode ITOI. The color filter FIL can be formed as follows: First, a dyed base material is formed on the surface of the upper transparent glass substrate 5UB2, and the dyed base material other than the red filter formation area is removed by photolithography technology. Thereafter, the dyed base material is dyed with red dye and subjected to a fixation treatment to form a red filter R. Next, a similar process is performed to sequentially form a green filter G and a blue filter B. Spacer material SP (Figure 2B) shows the upper transparent glass substrate 5.
When forming a red filter R1, a green filter G, and a blue filter G on the UBZ, after forming the red filter R of the first layer, the green filter G of the second layer is formed on a part thereof.
A third layer of blue filter B is formed in an overlapping manner. The positions where the green filter G and blue filter B are formed as spacers SP are as follows. The position corresponds to the gate line GL or drain line DL on the light shielding film BM of the upper transparent glass substrate 5UB2 or on the lower transparent glass substrate 5UBI. Thickness of green filter G and blue filter B and lower transparent glass substrate 5U
The thickness of the liquid crystal LC is defined by the total thickness of the convex portion of the gate line or drain line of the BI. The protective film PSV2 is provided to prevent the dyes used to dye the color filter FIL into different colors from leaking into the liquid crystal LC. The protective film PSV2 is made of, for example, a transparent resin material such as acrylic resin or epoxy resin. (Thin film transistor TPT> The thin film transistor TPT operates in such a way that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and drain becomes small, and when the bias is reduced to zero, the channel resistance becomes large.Thin film transistor of each pixel TPT is 3 within a pixel.
It is divided into two (plurality) of thin film transistors (divided thin film transistors) TFT1, TFT2, and TFT3. Thin film transistor TPTI~TFT3
Each of the channels is of substantially the same size (same channel length and width). Each of the divided thin film transistors TPTI to TFT3 mainly includes a gate electrode GT, a gate electrode G1 to an insulating film GI,
It is composed of an i-type (intrinsic, not doped with conductivity type determining impurities) amorphous Si semiconductor layer AS, a pair of source electrode SDI and drain electrode SD2. Note that the source and drain are originally determined by the bias polarity between them, and in the circuit of this display device, the polarity is reversed during operation, so it should be understood that the source and drain are interchanged during operation. However, in the following description, for convenience, one side will be fixedly expressed as a source and the other side as a drain. (Gate electrode GT> As shown in detail in FIG. 4 (a plan view depicting only the layers g1, g2, and AS in FIG. 2A), the gate electrode GT is connected vertically from the scanning signal line GL (FIG. 2A and The gate electrode GT is configured with a shape that protrudes upward (in FIG. 4) (branched into a T-shape).The gate electrode GT is formed by W so as to protrude to the formation regions of each of the thin film transistors TPTI to TFT3. .Thin film transistor TPTI~TF
The respective gate electrodes GT of T3 are integrally formed (as a common gate electrode) and are formed continuously to the scanning signal line GL. The gate electrode GT is formed of a single-layer first conductive film GL so as not to form a large step in the formation region of the thin film transistor TPT. The first conductive film g1 is formed using, for example, a chromium (Cr) film formed by sputtering, and has a film thickness of approximately 1000 nm. As shown in FIGS. 2A, 2B, and 4, this gate electrode GT is formed to be thicker than the semiconductor RAS so as to completely cover it (as viewed from below). Therefore, when a backlight BL such as a fluorescent lamp is attached below the substrate 5UBI, the opaque Cr gate electrode GT casts a shadow, and the backlight light does not shine on the semiconductor IAs.
A conductive phenomenon, that is, deterioration of the off-characteristics of TPT due to light irradiation becomes less likely to occur. The original size of the gate electrode GT is the minimum width required to span between the source/drain electrodes SDI and SD2 (including the alignment margin between the gate electrode and the source/drain electrodes), and the channel width. W
The depth length that determines the ratio to the distance (channel length) L between the source and drain electrodes, that is, the factor W/L that determines the mutual conductance gm, is determined. Of course, the size of the gate electrode in this example is important. It is made larger than the original size mentioned above. Considering only the gate and light shielding functions of the gate electrode GT, the gate electrode and its wiring OL may be integrally formed in a single layer, and in this case, Si is used as the opaque conductive material.
A1 containing A1. A1 containing pure AI and Pd
etc. can be selected. (Scanning Signal Line GL> The scanning signal line GL is composed of a composite film consisting of a first conductive film g1 and a second conductive film g2 provided on top of the first conductive film g1. is formed in the same manufacturing process as the first conductive film g1 of the gate electrode GT, and is configured integrally with the first conductive film g1.The second conductive film g2 is made of, for example, an aluminum (AQ) film formed by sputtering. The second conductive film g2 is formed to have a film thickness of about 2000 to 4000 [people].The second conductive film g2 reduces the resistance value of the scanning signal line GL and increases the signal transmission speed (improves the writing characteristics of pixel information).
It is structured so that it can be achieved. Furthermore, in the scanning signal line OL, the width of the second conductive film g2 is smaller than the width of the first conductive film g1. That is, the scanning signal line GL has a gradual step shape on its side wall. (Gate Insulating Film GI> The insulating film GI is used as a gate insulating film for each of the thin film transistors TPTI to TFT3. #! The edge film GI is formed on the gate electrode GT and the scanning signal BGL. Insulating film Gl is, for example, made of a silicon nitride film formed by plasma CVD, and has a temperature of 3000 [λ
] Formed with a film thickness of approximately . (Semiconductor layer AS> As shown in FIG. 4, the i-type semiconductor layer AS is used as a channel formation region for each of the thin film transistors TPTI to TFT3 divided into a plurality of parts. The i-type semiconductor layer AS is made of amorphous silicon. The i-type semiconductor layer AS is formed of a polycrystalline silicon film or a polycrystalline silicon film with a thickness of approximately 1800 [A].
, N4 gate insulating film GI, and is formed in the same plasma CVD apparatus without being exposed to the outside from the apparatus. Also, P for ohmic contact
Similarly, N''1dO doped with N''1dO (Fig. 2B) is continuously formed to a thickness of about 400[lambda].The lower substrate 5UBI is then taken out from the CVD apparatus and photoprocessed using a photoprocessing technique. N”ldO and i-layer AS are shown in Figure 2A, °2
It is patterned into independent islands as shown in Figures B and 4. The i-type semiconductor layer AS is located at the intersection of the scanning signal line OL and the video signal line DL (as shown in detail in FIGS. 2A and 4).
The cross-over section) is also provided between the two. This intersection i-type semiconductor layer As is connected to the scanning signal line O at the intersection.
It is configured to reduce short circuits between L and the video signal line DL. (Source/drain electrodes SDI, SD2>The source electrodes SDI and drain electrodes SD2 of the thin film transistors TPTI to TFT3 divided into a plurality of parts are shown in FIG. 2A, FIG. 2B, and FIG. 5 (layer di- As shown in detail in the plan view (plan view depicting only d3), they are provided separately on the semiconductor layer AS.
From the lower layer side in contact with the type semiconductor/ldo, the first conductive film d
1, a second conductive film d2, and a third conductive film d3 are sequentially stacked. First conductive film d1 of source electrode SDI
, the second conductive film d2 and the third conductive film d3 are formed in the same manufacturing process as the drain electrode SD2. The first conductive film d1 is a chromium film formed by sputtering, and is formed with a thickness of 500 to 1000 [A] (in this example, a film thickness of about 600 [A]). The thicker the chromium film is, the greater the stress will be, so
The film should be formed within a range that does not exceed a film thickness of approximately 0 [person]. The chromium film has good contact with the N+ type semiconductor layer do. The chromium film prevents aluminum of the second conductive film d2, which will be described later, from diffusing into the N+ type semiconductor layer dO. It constitutes a so-called barrier layer. The first conductive film d1 is formed of a high melting point metal (Mo, Ti, Ta, W) film and a high melting point metal silicide (M. Si, TiSi, TaSi, WSi,) film in addition to the chromium film. You may. After patterning the first conductive film di by photoprocessing, the N+ layer do is removed using the same photoprocessing mask or using the first conductive film d1 as a mask. In other words, the N''J'ldO remaining on the i-layer AS is removed by self-line except for the first conductive film d1. At this time, the N+ layer do is etched to remove its entire thickness. As a result, the surface portion of i l AS is also slightly etched, but the extent can be controlled by the etching time.Then, the second conductive film d2 is formed by sputtering aluminum to form a film with a thickness of 3000 to 4000 [A]. The aluminum film is formed to a thickness of about 3000 [A] in this example.The aluminum film has less stress than the chromium film and can be formed to a thick film thickness. It is configured to reduce the resistance values of the electrode SD2 and the video signal line DL.The second conductive film d2 is made of silicon (Si) or copper (Cj) in addition to the aluminum film.
It may be formed of an aluminum film containing as an additive. After patterning the second conductive film d2 using a photoprocessing technique, a third conductive film d3 is formed. This third conductive film d3 is a transparent conductive film (Induim-T) formed by sputtering.
in-Oxide ITO: consists of 1
000 to 2000 [A] film thickness (in this example, 120 [A]
0 [film thickness of approximately A]. This third conductive film d3 is connected to the source electrode SD1. In addition to forming the drain electrode SD2 and the video signal line DL, the transparent pixel electrode IT
It is designed to constitute OI. First conductive film di of source electrode SD1, drain electrode SD
Each of the first conductive films di of No. 2 extends more inward (into the channel region) than the upper second conductive film d2 and the third conductive film d3. In other words, the first conductive film d1 in these parts is the layer d
2. The configuration is such that the gate length of the thin film transistor TPT can be defined independently of d3. As described above, the source electrode SD1 is the transparent pixel electrode IT.
Connected to OI. The source electrode SDI has a step shape of the i-type semiconductor layer AS (the thickness of the first conductive film g1, the thickness of the N+ layer d
It is configured along a step corresponding to the sum of the film thickness of the i-type semiconductor layer AS and the film thickness of the i-type semiconductor layer AS. Specifically, the source electrode SDI includes a first conductive film di formed along the step shape of the i-type semiconductor layer AS, and a first conductive film d.
1, a second conductive film d2 is formed on the side connected to the transparent pixel electrode IT○1 in a smaller size than that of the second conductive film d2, and a third conductive film d2 is connected to the first conductive film d1 exposed from the second conductive film. It is composed of a conductive film d3. Source electrode SDI
The second conductive film d2 of the first conductive film di cannot be formed thickly due to increased stress, and cannot overcome the stepped shape of the i-type semiconductor MAS.
It is designed to overcome. In other words, the step coverage is improved by forming the second conductive film d2 thickly. Since the second conductive film d2 can be formed thickly,
This greatly contributes to reducing the resistance value of the source electrode SDI (the same applies to the drain electrode SD2 and the video signal line DL). Since the third conductive film d3 cannot overcome the step shape caused by the i-type semiconductor layer AS of the second conductive film d2, by reducing the size of the second conductive film d2, the exposed first conductive film di configured to connect. The first conductive film di and the third conductive film d3 not only have good adhesion but also have a small step shape at the connection between them.
Can be connected reliably. (Pixel electrode ITOI) The transparent pixel electrode ITOI is provided for each pixel and constitutes one of the pixel electrodes of the liquid crystal display section. It is divided into three transparent pixel electrodes (divided transparent pixel electrodes) El, E2, and E3 corresponding to each of the TFTs 3. The transparent pixel electrodes E1 to E3 are each connected to the source electrode SDI of the thin film transistor TPT. Each of the transparent pixel electrodes E1 to E3 is patterned to have substantially the same area.In this way, the thin film transistor TPT of one pixel is divided into a plurality of thin film transistors TPTI to TFT3. By connecting each of the transparent pixel electrodes El-E3 divided into a plurality of parts to each of the thin film transistors TPTI to TFT3, a divided part (for example, TF
Even if Tl) becomes a point defect, it is no longer a point defect when looking at the two pixels as a whole (TFT2 and TFT3 are not defective), so
The probability of point defects can be reduced, and defects can be made difficult to see. Furthermore, the divided transparent pixel electrodes Ei- to E3 of the pixel
By configuring each of them to have substantially the same area, each of the transparent pixel electrodes El-E3 and the common transparent pixel electrode ITO2
It is possible to make each liquid crystal volume 1 (CPiX) uniform. (Protective film PSV1) A protective film PSVI is provided over the thin film transistor TPT and the transparent pixel electrode IrO2. The protective film PSVI is mainly formed to protect the thin film transistor TPT from moisture and the like. Use a material that is highly transparent and has good moisture resistance. The protective film PSVI is formed of, for example, a silicon oxide film or a silicon nitride film formed by plasma CVD, and has a film thickness of 8000 [
Formed with a film thickness of approximately (Common electrode IT○2) The common transparent pixel electrode ITO2 is connected to the lower transparent glass substrate 5U.
Opposing the transparent pixel electrode ITOI provided for each pixel on the BI side, the optical state of the liquid crystal changes in response to the potential difference (electric field) between each pixel electrode IT○1 and the common electrode IrO2. This common transparent pixel electrode ITO2 has a common voltage Vco
m is applied. Common voltage Vc
om is a video signal! Low level driving voltage V d win and high level driving voltage V d m applied to DL
This is the intermediate potential between ax and ax. (Pixel Arrangement) As shown in FIGS. 3 and 7, a plurality of pixels of the liquid crystal display section are arranged in the same column direction as the direction in which the scanning signal 1% GL extends, and pixel columns Xi, X2° X3. X4. ...
constitutes each of the following. Each pixel column X1, X2. X3. X
4. Each pixel of... is a thin film transistor TFTI
~The arrangement positions of the TFT 3 and the transparent pixel electrodes E1 to E3 are configured to be the same. That is, odd numbered pixel columns Xi, X3 .・
Each pixel of . . . is a thin film transistor TPTI to TF.
The arrangement position of T3 is arranged on the left side, and the arrangement position of transparent pixel electrodes E1 to E3 is arranged on the right side. Odd pixel columns Xi, X3.・
. . , adjacent even-numbered pixel columns in the row direction X2. X4.・
The pixels of each of the odd-numbered pixel columns Xi, X3 . . . . each pixel is made up of pixels that are symmetrically turned upside down with respect to the extending direction of the video signal line DL. That is, pixel row X2. X4. In each pixel, thin film transistors TPTI to TFT3 are arranged on the right side, and transparent pixel electrodes E1 to E3 are arranged on the left side. Then, pixel row X2. X4. Each pixel of...
Pixel rows Xi, X3. . . are moved (shifted) by half a pixel interval in the column direction. In other words, if each pixel interval of pixel row X is 1.0 (1,0 pitch), then the next stage pixel row
and is shifted by 0.5 pixel interval (0.5 pitch) in the column direction with respect to the previous pixel column X. The video signal line DL extending in the row direction between each pixel is configured to extend in the column direction by a half pixel interval (0.5 pitch) between each pixel column X. As a result, as shown in FIG. 7, the pixels in the previous pixel row The pixels on which color filters are formed (for example, the pixels on which red filter R is formed in pixel row It will be arranged. Color filter F
The RGB triangular arrangement structure of the IL can improve the mixing of each color, and therefore can improve the resolution of a color image. Moreover, since the video signal line DL extends in the column direction by only half a pixel interval between each pixel column X, it does not intersect with the adjacent video signal line DL. Therefore, video signal line D
It is possible to eliminate the routing of L and reduce its occupied area, and it is also possible to eliminate the detour of the video signal line DL and eliminate the multilayer wiring structure. (Equivalent circuit of the entire display panel) An equivalent circuit of this liquid crystal display device is shown in FIG. XiG, Xi+IG, . . . are video signal lines DL connected to pixels in which the green filter G is formed. X x B t X x + I B y . . . is a video signal line DL connected to a pixel in which a blue filter B is formed. Xi+IR, Xi+2R, . . . are video signal lines DL connected to pixels in which the red filter R is formed. These video signal lines DL are selected by a video signal drive circuit. Yi is a scanning signal line GL that selects the pixel column Xi shown in FIGS. 3 and 7. Similarly, Yi+1. Yi+2. Each of the pixel rows X2 . X3. . . . is a scanning signal line GL that selects each of the following. These scanning signal lines GL are connected to a vertical scanning circuit. (Structure of additional capacitance Cadd) Each of the transparent pixel electrodes E1 to E3 is a thin film transistor T.
It is bent into an L-shape so as to overlap the adjacent scanning signal line GL at the end opposite to the end connected to PT. As is clear from FIG. 2C, this superposition is such that each of the transparent pixel electrodes E1 to E3 is connected to one electrode PL.
2, and configures a storage capacitor element (electrostatic capacitor element) Cadd in which the adjacent scanning signal line OL is the other electrode PLI. The dielectric film of this storage capacitor element Cadd is an insulating film GI used as a gate insulating film of the thin film transistor TPT.
It is composed of the same layer. As is clear from FIG. 4, the storage capacitor Cadd is formed in the widened portion of the first layer g1 of the gate line OL. Note that the Mg1 in the portion intersecting with the drain line DL is made thin in order to reduce the probability of short circuit with the drain line. Similar to the source electrode SDI, a portion between the capacitor electrode line (gl) and each of the transparent pixel electrodes E1 to E3 that are overlapped to form the storage capacitor element Cadd is provided with a An island region made up of the first conductive film d1 and the second conductive film d2 is provided so that the transparent pixel electrode IT○1 is not disconnected. This island region is configured to be as small as possible so as not to reduce the area (aperture ratio) of the transparent pixel electrode ITO1. (Equivalent circuit of additional capacitance Cadd and its operation) An equivalent circuit of the pixel shown in FIG. 2A is shown in FIG. 9. In FIG. 9, Cgs is the gate electrode GT of the thin film transistor TPT.
and a parasitic capacitance formed between the source electrode SDI. The dielectric film of the parasitic capacitance Cgs is an insulating film GI. Cpi
x is a liquid crystal capacitance formed between the transparent pixel electrode ITOI (PIX) and the common transparent pixel electrode IT○2 (COM). The dielectric film of the liquid crystal capacitor Cpix is the liquid crystal LC1 protective film ps
v1, alignment film 0RII, and ○Rr2. Vlc is a midpoint potential. The storage capacitance element Cadd works to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Via when the TFT switches. This situation can be expressed by the formula ΔV lc= ((Cgs/ (Cgs+Cadd+C
pix)) XΔVg. Here, ΔVlc is ΔVg
represents the change in midpoint potential due to This change ΔVlc
causes a DC component applied to the liquid crystal, but the retention capacity Ca
The larger dd is, the smaller its value can be. In addition, the holding capacitor Cadd also has the effect of lengthening the discharge time, so that video information is stored for a long time after the TPT is turned off. Reducing the DC component applied to the liquid crystal LC can improve the life of the liquid crystal LC and reduce so-called burn-in, in which the previous image remains when switching liquid crystal display screens. As mentioned above, since the gate electrode GT is enlarged to completely cover the semiconductor layer AS, the overlapping area with the source/drain electrodes SD1 and SD2 increases, and therefore the parasitic capacitance JiCgs increases, and the midpoint potential Vlc increases. Gate(
This has the opposite effect of becoming more susceptible to the influence of the scanning signal Vg. However, by providing the holding capacitor Cadd, this disadvantage can also be eliminated. The storage capacitance of the storage capacitor element Cadd is 4 to 8 times the liquid crystal capacitance Cpix (4・Cp
ix<Cadd<8・Cpix), superposition capacitance Cgs
8 to 32 times (8・Cgs<Cadd<32
・Set to a value of about Cgs). (Connection method of additional capacitance Cadd electrode line) As shown in FIG. ) Connect to IrO2. The common transparent pixel electrode ITO2 is. As shown in FIG. 2B, the peripheral portion of the liquid crystal display device is connected to an external lead wire by a silver paste material SL. Moreover, a part of the conductive line M (gl and g2) of this external lead wiring is formed in the same manufacturing process as the scanning signal line GL. As a result, the final stage capacitor electrode! GL can be easily connected to the common transparent pixel electrode ITO2. Alternatively, as shown by the dotted line in FIG. 8, the capacitor electrode line OL at the final stage (first stage) may be connected to the scanning signal line GL at the first stage (last stage). Note that this connection can be made by internal wiring within the liquid crystal display section or external wiring. (DC cancellation by additional capacitance Cadd scanning signal) This liquid crystal display device is based on the DC cancellation method (DC cancellation method) described in Japanese Patent Application No. 62-95125 previously filed by the applicant of the present invention. Diagram (time chart)
As shown in FIG. 2, by controlling the drive voltage of the scanning signal line DL, the DC component applied to the liquid crystal LC can be further reduced. In FIG. 1O, Vi is the drive voltage of an arbitrary scanning signal line GL, and Vi+1 is the drive voltage of the scanning signal line GL at the next stage. Vee is a low-level driving voltage Vdm1n applied to the scanning signal mGL, and Vdd is a high-level driving voltage Vdma applied to the scanning signal line GL.
It is x. Midpoint potential Vl at each time t=11 to t
The voltage change ΔV~Δv4 of c (see FIG. 9) is as follows. 1=11:ΔV,=-(Cgs/C)・V21=12:
ΔV, = + (Cgs/C) (V1 + v2) - (Cadd
/C)・V 2 1 = 1. : ΔVa = (Cgs/C)・V 1
+ (Cadd/C)・(V1+V2) 1=14:ΔV4= (Cadd/C)・Vl However, the total capacitance of pixels: C= Cgs+ Cpix + ad
d Here, if the drive voltage applied to the scanning signal line GL is sufficient (see below)

[Note]), the DC voltage applied to the liquid crystal LC is ΔV, 1ΔV4= (Cadd-V 2- Cgs-V
l )/C, so Cadd-V 2 =
If Cgs-Vi, the DC voltage applied to the liquid crystal LC is O
become. [Note] Time 1. ．． 1. The change in scan tIAvi affects the midpoint potential Vlc, but during the period from t2 to t, the midpoint potential V1c is made the same potential as the video signal potential through the signal mXi (sufficient writing of the video signal). The potential applied to the liquid crystal is almost determined by the potential immediately after the TPT is turned off (the TPT off period is overwhelmingly longer than the on period). Therefore, when calculating the DC component applied to the liquid crystal, the period t to t can be almost ignored, and it is sufficient to consider the potential immediately after the TPT is turned off, that is, the influence of the transient at times t3 and t4. Note that the polarity of the video signal Vi is inverted for each frame or line, and the DC component due to the video signal itself is zero. In other words, the DC cancellation method uses the drive voltage applied to the storage capacitance element Cadd and the next stage scanning signal line GL (capacitance electrode line) to push up the drop caused by the pull-in of the midpoint potential Vlc by the superimposed capacitance Cgs. The DC component added to the LC can be made extremely small. As a result, the life of the liquid crystal LC of the liquid crystal display device can be improved. Of course, if the gate GT is increased in size to improve the light shielding effect, the value of the storage capacitor Cadd may be increased accordingly. As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course. For example, the spacer material made of a color filter is not limited to the configuration of the above embodiment, and various configurations such as the number of layers can be applied. Furthermore, although the example shows an inverted staggered structure in which gate electrode formation → gate TPI film formation → semiconductor layer formation → source/drain electrode formation, the present invention is also effective in a staggered structure in which the vertical relationship or the order of formation is reversed. be. [Effects of the Invention] As described above, according to the present invention, light leakage due to the spacer material does not occur, point defects and a decrease in contrast ratio can be prevented, and the display quality of a liquid crystal display device can be improved.

[Brief explanation of drawings]

1(A) and 1(B) are schematic cross-sectional views of examples of the cross-sectional structure of a liquid crystal display device of the present invention, and FIG. 2A is a schematic cross-sectional view of an example of a cross-sectional structure of a liquid crystal display device of the present invention. FIG. 2B is a plan view of a main part showing one pixel of the liquid crystal display section of the display device. FIG. 2B is a cross-sectional view of the portion taken along the HB-nB cutting line in FIG. 2A is a cross-sectional view taken along the NC-NC cutting line; FIG. 3 is a plan view of a main part of a liquid crystal display section in which a plurality of pixels shown in FIG. 2A are arranged; FIGS. 4 to 6 are a cross-sectional view of FIG. 7 is a plan view depicting only a predetermined layer of the pixel shown in FIG.・An equivalent circuit diagram showing the liquid crystal display section of a matrix type color liquid crystal display device, FIG.
Figure A is an equivalent circuit diagram of the pixel shown in Figure A. Figure 10 is a time chart showing the opening voltage of the scanning signal line using the DC cancellation method. Figure 11 is a schematic cross-sectional view of a liquid crystal display section showing a conventional spacer material. It is. In the figure, sp...spacer material, SUB...transparent glass substrate, GL...scanning signal line, DL...video signal line,
G■...Insulating film, GT...Gate electrode, AS...
i-type semiconductor layer, SD... source electrode or drain electrode, PSV... protective film, LS... light shielding film, LC...
Liquid crystal, TPT...thin film transistor, ITO...transparent electrode, g+ d...conductive film, Cadd...holding capacitor element, Cgs...superimposed capacitance, Cpix...
This is the liquid crystal capacity (numerical subscripts after alphabetic characters are suffixes).

Claims (1)

[Claims] 1. A first transparent substrate on which a color filter is formed, a second transparent substrate, a liquid crystal sealed between the first transparent substrate and the second transparent substrate, and a liquid crystal sealed between the two substrates. A liquid crystal display device comprising a spacer material for making the thickness constant, and the spacer material is made of the color filter forming material.