JPH0367345B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a multi-chip package in which wiring between mounted chip components and I/O leads can be easily changed.

[Technical background of the invention and its problems] As electronic devices become smaller and lighter, there is an increasing demand for high-density packaging of electronic components.

Against this background, hybrid ICs
Its application fields are rapidly expanding because it is suitable for high-power/high-voltage fields that are difficult to achieve with monolithic ICs, high-mix, low-volume production, and multifunctionality.

FIG. 2 is a perspective view of an example of a hybrid IC, in which a group of bonding pads 3a to 3f that are electrically connected to the embedded wiring 1 are formed on a ceramic multilayer substrate 2 in which a large number of embedded wiring 1 are buried. . Therefore, it was mounted and arranged on the ceramic multilayer substrate 2.
The terminals of the IC chips and other chip components 4a to 4c are respectively connected to predetermined (corresponding) bonding pads 3a to 3f via bond lines 5a to 5f.

Hybrid ICs like this are developed and designed according to customer needs, and after evaluating the prototype and making any necessary modifications to confirm that the desired functionality is achieved, production begins. However, these days, there is often less time available from development design to production, so it is rarely necessary to proceed with prototype evaluation and product production in parallel, especially for small-volume products. do not have.

In such a case, when it became necessary to add or delete the embedded wiring 1 between the IC chips 4a to 4c or between the IC chip and the input/output circuit, conventionally the ceramic multilayer board 2 itself was remade. In order to reduce the man-hours and time required for this, as well as development costs for pattern masks, molds, etc., a method of modifying the hybrid IC shown in FIG. 3 has been considered.

That is, as a result of evaluating the hybrid IC having the configuration shown in FIG.
If it is found that it is necessary to break the continuity between the IC chips 4a and 4b and instead establish continuity between the terminals of the IC chips 4a and 4b, as shown in FIG. Attach the additional pad 6 to the position near the terminal 4a, and connect the bond wire 5b.
After removing one end from the bonding pad 3b and connecting it onto the additional pad 6, an additional wiring 7 is wired between the additional pad 6 and the bonding pad 3d.

In this way, it is possible to easily change the connections between IC chips while using the originally designed ceramic multilayer board, and the ceramic multilayer board and the IC chips attached to it can be used as they are, reducing losses. It becomes possible to significantly reduce the time.

Further, since the bond line and the additional wiring are connected via the additional pad, bonding is performed reliably and reliability does not deteriorate.

However, the method of changing the hybrid IC described above has the following problems.

In other words, if the embedded wiring is a wiring that is connected to many locations, such as the address bus or data bus of a CPU module, and you try to change the connections using the method described above, you will have to change a large number of locations. This makes the work complicated.

In addition, in multi-chip packages, normally a metal cap is fixed onto a ceramic multilayer board to seal the chip component area internally and hermetically, but a seal ring pattern is provided on the board for mounting this metal cap. Because it is
It is difficult to provide the additional wiring between the I/O pad for attaching an I/O lead that exists outside the seal ring pattern and the conductor pad such as a bonding pad that exists inside.

Furthermore, since the area of the board surface on which additional wiring can be provided is limited, there is also a limit to the amount of additional wiring, and the reality is that it is virtually impossible to cope with an increase in the number of chip components to be mounted.

[Object of the Invention] The present invention was made to solve the above-mentioned problems in the background art, and an object of the present invention is to provide a multi-chip package that makes it easier to change the wiring of a hybrid IC. It is something.

[Summary of the Invention] The multi-chip package of the present invention includes a substrate on which embedded wiring is arranged, a plurality of chip components mounted on the substrate, and a multi-chip package formed on the substrate surface near each of the chip components. A first bonding pad group electrically connected to the embedded wiring, a seal ring pattern formed on the board surface surrounding the first bonding pad group and the chip component group, the chip component and the corresponding chip component. In the multi-chip package, the multi-chip package includes a bond line connecting between first bonding pads, and a cap having an open end surface sealed on the seal ring pattern, wherein the embedded wiring is inside the seal ring pattern. forming a non-conducting portion between the bonding pad group and the first bonding pad group at the position and near the sealing pattern;
The non-conducting portion is connected to a second group of bonding pads formed on the substrate on both sides, and the second bonding pads are electrically connected to each other. Features.

[Embodiments of the Invention] Next, embodiments of the present invention will be described with reference to FIGS. 1a and 1b.

FIG. 1a shows a cross-sectional view of an example of the main part of a multi-chip package according to the present invention, and FIG. 1b shows a state before the cap is sealed in an example of the main part of a multi-chip package according to the present invention. FIG.

In the figure, a large number of embedded wirings 11 (Do ₀ to Do ₇ , So ₁ to So _3, etc.) are embedded in a ceramic multilayer substrate 10 . This embedded wiring 11 (Do ₀
~Do ₇ , So ₁ ~ _{So 3} , etc.) There are many types depending on the application, but if this is a data bus, one end is an I/O bus installed on the periphery of the board.
It is connected to an I/O lead 13 via a pad 12. Reference numeral 14 indicates a silver solder layer connecting the I/O pad 12 and the I/O lead 13.

An IC chip or other chip components 17 are fixed onto a die pad 15 at ground or power supply potential provided on the surface of the ceramic multilayer substrate 10 via solder or conductive adhesive 16. Further, a frame-shaped seal ring pattern 18 is formed on the substrate 10 slightly inside the peripheral edge thereof, and the lower end of the metal cap 19 is hermetically connected to the seal ring pattern 18 by a solder layer 20.

The embedded wiring 11 (Do ₀ to Do ₇ , So ₁ to _{So 3,} etc.) is located slightly inside the seal ring pattern 18 and is separated from a first bonding pad group 23 to be described later. A non-conducting portion 21 is formed. The wiring 11a on the I/O lead 13 side and the wiring 11b on the chip component 17 side on both sides of this non-conducting part are connected to a second group of bonding pads 22a and 22b arranged on the substrate 10, respectively. Further, the wiring 11b is connected to a first group of bonding pads 23 placed at appropriate locations.

Bonding is performed between the first group of bonding pads 23 and the terminals of the chip component 17, and between the second group of bonding pads 22a and 22b using bond lines 24 and 25, respectively. Therefore, the second bonding pads 22a, 22b
Groups can be disconnected and reconnected as appropriate if wiring errors are confirmed during a functional evaluation test. In other words, if it is determined that it is appropriate to connect the wiring 11b on the chip component 17 side to an I/O lead different from the I/O lead 13, the bond line 2 between the bonding pads 22a and 22b
4 and connect the bonding pad connected to another I/O lead and the bonding pad 22b with a bond wire or additional wiring.

_{In this} regard, to explain in more detail with reference _{to FIG} . 22a,2
Interchanging the wiring can be achieved by removing the bonding wires 24 between the wires 2b and bonding them in a crossed manner, for example.

On the other hand, in normal traffic lights So ₁ to So ₃ , for example, So ₁ is the power supply or ground solid pattern 2.
6, it is difficult to find the shot point, and even if it were found, it would not be possible to cut it out if there is a die pad 15 for the chip component 17 on the surface of that area.
The reality is that it is virtually impossible to repair the shortened part. Moreover, since the area occupied by the die pad 15 for the chip component 17 is relatively wide, the probability of such a problem occurring is high. Furthermore, when it is necessary to separate the So ₁ from the ground solid pattern 26, the second bonding pads 22a, 2
This can be easily handled by cutting off the bonding wire 24 between the wires 2b. In addition, hybrid
Multilayer wiring boards for ICs often have a multilayer structure that includes a ground pattern and a solid layer 26 for the power supply in order to improve the shielding effect and resistance to induced noise. The probability of occurrence is also high.

[Effects of the Invention] As described above, in the multi-chip package of the present invention, the pattern wiring embedded in the substrate is separated in the middle, and bonding pads are provided at the ends of the embedded wiring on both sides of this separation point. Therefore, by changing the connections between these bonding pads, the connections of the circuit elements connected to the wiring on the chip component side can be changed all at once.

Also, a bonding pad 22 for connecting the breaking point.
Since a and 22b are provided near the inside of the seal ring pattern 18, there is no need to arrange bond wires or additional wiring across the seal ring pattern, and there is no need to lower the airtightness inside the metal cap. do not have.

[Brief explanation of drawings]

FIG. 1a is a cross-sectional view of an example of the configuration of a main part of a multi-chip package according to the present invention, and FIG. , second
3 and 3 are perspective views showing the main structure of a conventional multi-chip package. 1, 11... Embedded wiring, 2, 10... Ceramic multilayer substrate, 3a to 3f, 22a, 22b, 23
...Bonding pad, 4a-4c, 17...
Chip parts, 5a to 5f, 24, 25... Bond wire, 6... Additional pad, 7... Additional wiring, 12...
...I/O pad, 13...I/O lead, 15...
...Die pad, 18...Seal ring pattern,
19...Metal cap, 21...Non-conducting part.

Claims (1)

[Scope of Claims] 1. A substrate on which embedded wiring is arranged, a plurality of chip components mounted on the substrate, and a substrate formed on the substrate surface near each of the chip components and electrically connected to the embedded wiring. a first bonding pad group, a seal ring pattern formed on the substrate surface surrounding the first bonding pad group and the chip component group, and a seal ring pattern formed on the substrate surface surrounding the first bonding pad group and the chip component group; A multi-chip package comprising: a bond line connecting the chips; a cap having an open end surface sealed on the seal ring pattern; and an I/O lead formed around the outer periphery of the cap. The embedded wiring forms a non-conducting part between the first bonding pad group and the first group of bonding pads led out on the surface near the seal ring pattern at an inside position of the seal ring pattern. A multi-chip package characterized in that the chip is connected to a group of second bonding pads respectively formed on the chip, and has a configuration in which the second bonding pads are electrically connected.