JPH0368168A - Semiconductor memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor memory in which memory cells are configured using flip-flops. [Summary of the Invention] The present invention relates to a semiconductor memory as described above. , a gate electrode of a driving transistor of a flip-flop and a conductive layer on the side of this gate electrode are used as a pair of electrodes of a capacitive element,
And by connecting the conductive layer to the power line? This makes it possible to increase the resistance to soft errors caused by α rays even when Xk is made thinner.

[Conventional technology]

FIG. 4 shows a semiconductor memory (SRAM) in which memory cells are constructed using flip-flops 11.

In such an SRAM, in order to increase resistance to soft errors in which stored data is destroyed by the incidence of alpha rays, a capacitive element 12. with one electrode having a fixed potential is used.
13 to the storage node 14.15 of the memory cell (e.g. 1987 SYMPO5
IUM ON VLSI TBCI (NOLOGY.

DIGEST OF TEC）INTCAL PAPE
R3, Plot-102, MAY.

1987).

In SRA, M of the above-mentioned document, in order to realize such a structure, the load resistance 16.17 of the flip-flop 11 is
Of the polycrystalline Si film constituting the driving power supply line 18, the contact portion with the drain region of the driving transistor 21.22 is used as one electrode of the capacitive element 12.13, and the grounding power supply line 23 is The constituting polycrystalline Si film serves as the other electrode of the capacitive element 12.13.

[Problem to be solved by the invention]

However, the polycrystalline Si layer constituting the load resistor 16, 17, etc. is also the same as the polycrystalline SiN layer constituting the grounding power supply line 23.
It also extends substantially parallel to the surface of the semiconductor substrate.

For this reason, when SRAMs are miniaturized, the capacitive elements 12.
The opposing areas of the pair of electrodes 13 are reduced proportionally, and the capacitances of these capacitive elements 12 and 13 are rapidly reduced.

Therefore, in a miniaturized SRAM, the capacitive element 12.1
3 has a small capacity, and its resistance to soft errors caused by alpha rays is not necessarily high.

[Means for Solving the Problems] In the semiconductor memory according to the present invention, the flip-flop 11
A conductive layer 37 is formed on at least the sides of the gate electrode 31 of the driving transistor 21.22, and the gate electrode 31 and the conductive layer 37 form a pair of electrodes of the capacitive element 12.13. , the conductive N31 is the power source 123
It is connected to the.

[Effect]

In the semiconductor memory according to the present invention, the driving transistor 2
Since the gate electrode 31 of 1.22 serves as one electrode of the capacitive element 12.13, the storage node 14 of the memory cell
．． Capacitive elements 12 and 13 are connected to 15.

Further, since the conductive layer 37 serving as the other electrode of the capacitive element 12.13 is connected to the power supply line 23, the potential of this conductive layer 37 is fixed.

Since the conductive layer 37 is formed on the side of the gate electrode 31, the pair of electrodes of the capacitive elements 12 and 13 is connected to the semiconductor base +L! It extends perpendicularly to the surface of 6. Therefore, even if the semiconductor memory is miniaturized, the opposing area of the pair of electrodes will not be proportionally reduced, and the capacitive elements 12 and 13 can secure a large capacity.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

FIG. 1 and FIG. 2 show the storage node 14 in this embodiment.
It shows the vicinity of . This example is a MOS-3R, AM with a three-layer polycrystalline Si structure, and the driving transistor 2
1.22 and the gate electrodes of the transfer transistors 24.25, the ground power supply line 23, the load resistor 16.17, and the drive power supply N18 are formed of first to third layer polycrystalline Si films, respectively.

In this embodiment, the first layer and the second N-th polycrystalline S
With the i film and the dielectric film between them, capacitive element 12.13
is in great shape.

FIG. 3 shows the manufacturing process of this embodiment, and corresponds to the part shown in FIG. 1A. In this manufacturing process, as shown in FIG. 3A, first, a gate oxide film of Sin! is deposited on the surface of the Si substrate 26. Membrane 27 membrane shape 7.

Then, a 1Nth polycrystalline Si film 31 is deposited by CVD, and this polycrystalline Si film 31 is patterned to form gate electrodes of drive transistors 21, 22, etc.
Further, ions 32 are implanted into the Si substrate 26 using the polycrystalline St film 31 as a mask.

Next, as shown in FIG. 3B, the surface of the polycrystalline Si film 31 is oxidized to form a 5in2 film 33, then 5iNl 134 is formed by low pressure CVD, and then this SiN film 34 is formed.
A 5i02 film 35 is formed by oxidizing the surface of the 5i02 film 35.

Therefore, these Sin, film 33, SiN film 34, S
in.

The film 35 constitutes an ONO film.

Note that the heat treatment in these steps has already caused the Si substrate 2 to
The As'' ions 32 ion-implanted into the transistors 6 are activated, and a N e jl region 36 is formed which becomes the source/drain region of the driving transistors 21, 22, etc.

Next, a second N-th polycrystalline Si film 37 is deposited by CVD, and this polycrystalline Si film 37 is patterned to form a ground power supply 'fa23.

However, at this time, as shown in FIGS. 2 and 3C, the 11th! A second layer is placed on the first side of the polycrystalline Si film.
This polycrystalline Si film 37 is etched so that the N-th polycrystalline Si film 37 remains.

Next, as shown in FIG. 3D, the surface of the polycrystalline 5tl 137 is oxidized to form a Sin film 41, and a glabellar insulating film 42 is further deposited by CVD. And the glabella insulating film 4
Heat treatment is performed in an N2 atmosphere for densification of step 2 and thermal diffusion of impurities.

Thereafter, as shown in FIGS. 1 and 2, a load resistor 16, 17 and a driving power supply line 18 connected thereto are formed using the 3Nth polycrystalline Si film 43.

Also in this embodiment as described above, the gate electrode of the driving transistor 21.22 connected to the storage node 14.15 and the ground power supply line 23 serve as a pair of electrodes of the capacitive element 12.13. As shown in FIG.
．． Capacitive elements 12 and 13 are connected to 15.

In the region covered by the polycrystalline Si film 1 forming the gate electrodes of the driving transistors 21 and 22 and the polycrystalline Si film 37 forming the grounding power supply line 23,
As is clear from FIG. 1B, electricity can be stored in the upper and side portions of the polycrystalline Si film.

Furthermore, even in the area where the first polycrystalline Si film 37 on the polycrystalline Si film is not covered, as is clear from FIG.
Electricity can be stored on the sides of the T-film 31.

As MOS-S RAM is miniaturized, the height of the gate electrode becomes closer to its width, so the capacitive element 12.1
The ratio of the capacity in the area of the structure of FIG. 1A to the total capacity of 3 is high.

Therefore, even if the gate electrodes of the driving transistors 21 and 22 and the grounding power supply line 23 do not overlap in plan view and are only in the area of the structure shown in FIG. Highly tolerant to errors.

Moreover, in this embodiment, as described above, the SiO□ film 33, Si
The N film 34 and the SiO□ film 35 constitute an ONO film, and the ONO film has a high dielectric constant. Therefore, this also increases the capacitance of the capacitive elements 12 and 13, and in the structure of FIG. 1B, the polycrystalline St film 31 and the polycrystalline Si film 31
The dielectric strength between the polycrystalline Si film 37 and the upper polycrystalline Si film 37 is also guaranteed.

Note that if the gate electrodes of the driving transistors 21, 22 and the grounding power supply film 23 do not overlap in plan view as described above, as is clear from FIG. 1A, the transistors 21, 22, 24, . 25 can have an LDI) structure.

The reason why the Sing film 41 was formed on the surface of the polycrystalline 5il 137 was to prevent the ions implanted into the Si substrate 26 to form the high concentration impurity region of the LDD structure from penetrating the polycrystalline Si film 37. It is.

Therefore, if the LDD structure is not used, the 5i02 film 41 may be omitted.

〔Effect of the invention〕

In the semiconductor memory according to the present invention, a capacitor whose one electrode has a fixed potential is connected to the storage node of the memory cell, and this capacitor can secure a large capacity even in a miniaturized semiconductor memory. , even when miniaturized, it has high resistance to soft errors caused by alpha rays.

[Brief explanation of drawings]

1A and 1B show essential parts of an embodiment of the present invention, and FIG. FIG. 3 is a plan view of the main part and a side sectional view sequentially showing the manufacturing process of one embodiment. FIG. 4 is a circuit diagram of a MO3-3 RAM memory cell to which the present invention can be applied. In addition, in the symbols used in the drawings, 11---= ・-Fritub Flotub 12.13--
- One capacitive element 14.15 - - Storage node 21.22 - One driving transistor 23 - = ---- One grounding electric B line 26
~Si-based 4 anti-31.37--Polycrystalline Si film.

Claims (1)

[Claims] In a semiconductor memory in which a memory cell is configured using a flip-flop, a conductive layer is formed at least on a side of a gate electrode of a driving transistor of the flip-flop, and the gate electrode and A semiconductor memory, wherein the conductive layer is a pair of electrodes of a capacitive element, and the conductive layer is connected to a power supply line.