JPH0378007B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to electronic devices, particularly to a reference voltage generator and its applications, as well as an insulated gate field effect transistor and its manufacturing method. In various semiconductor electronic circuits, in order to generate a reference voltage, it is essential to use a physical quantity having the dimension of voltage. Until now, physical quantities such as the forward voltage drop V _F of a PN junction diode, the reverse breakdown voltage (Zena voltage) V _Z , and the insulated gate field effect transistor (often represented by an IGFET or MOSFET) have been considered. Threshold voltage V _th etc. are used. These physical quantities do not indicate absolute voltage values, and the voltage values are subject to fluctuations depending on various factors. Therefore, in order to utilize these physical quantities as a reference voltage generating device for various electronic circuits, it is necessary to pay attention to the fluctuation factors of the obtained voltage value and the permissible fluctuation range. First, regarding the temperature characteristics of these physical quantities, the above V _F and V _th usually have a temperature dependence of about 2 to 3 mV/°C, and the temperature change in the reference voltage that accompanies this temperature change varies depending on the application. It is so large that we have no choice but to abandon its practical use. For example, in an electronic watch that uses a nominally 1.5V silver oxide battery, if you are trying to realize a battery checker that is made to warn that the battery voltage has dropped, it is necessary to use a battery checker that is designed to warn that the battery voltage has dropped.
It is necessary to judge whether the battery voltage is high or low. This is the MOSFET threshold voltage of about 0.6V.
If you try to configure it using V _th or the forward drop voltage V _F of the diode, the detection level with a target of 1.4 V will be 1.4 (V) / 0.6 (V) × {2~6 (m
V/℃)} = 4.67 to 7.0 (mV/℃), with a practical operating temperature range of 0℃ to
Even if we make a narrow estimate of 50°C, the voltage will fluctuate significantly between 1.23V and 1.57V, making it impossible to use as a practical battery checker. Next, regarding manufacturing variations in these physical quantities, the threshold voltage V _th of the MOSFET has a variation of about ±0.2V, and this variation is larger than the temperature change. Therefore, when the battery checker described above is made into an IC (integrated circuit) using V _th , external components and connection pins (terminals) for reference voltage correction are required.
Not only that, but it also requires time and effort for adjustments after the IC is manufactured. In addition, in MOSFET integrated circuits such as semiconductor RAM, if you want to control the threshold voltage of the FET by applying a reverse bias voltage to the substrate (back gate), you need a reference voltage source that is independent of temperature dependence and manufacturing variations. Moreover, it is necessary that it can be integrated, but it is difficult to adopt it for the above-mentioned V _F and V _th for the same reason. Also, Zena voltage
V _Z has a low voltage limit of about 3V, which is inappropriate as a reference voltage for use in the low voltage range below 3V.Also, it is not suitable for using the Zener voltage and forward drop voltage of a diode as a reference voltage. is several meters
It is necessary to flow a current of approximately A to several tens of mA, which is inappropriate in terms of reducing power consumption. As is clear from the above explanation, V _th , V _F and
Conventional reference voltage generators that use _V In many cases, it was necessary to give up on commercialization and mass production. From the above studies, the present inventors learned that there are physical limits to the improvement of conventional reference voltage generators, and decided to research and develop a reference voltage generator with new ideas and ideas. . Incidentally, as a reference voltage generating circuit, for example, one shown in Japanese Patent Laid-Open No. 48-63257 is publicly known. An object of the present invention is to provide a reference voltage generation circuit based on a completely new idea not seen in the past, and to facilitate the design and mass production of electronic circuits. Another object of the present invention is to provide a reference voltage generator with small temperature changes. Another object of the present invention is to provide a reference voltage generator in which fluctuations in voltage values obtained are small relative to fluctuations in manufacturing conditions, for example, manufacturing variations (deviations) between lots are small. Another object of the present invention is to provide an integrated circuit reference voltage generating device that can reduce manufacturing variations to the extent that post-manufacturing adjustments are not required. Another object of the present invention is to provide an integrated electronic circuit device including a reference voltage generating device that can be manufactured with a large margin of tolerance to target specifications. Another object of the present invention is to provide an integrated electronic circuit device including a reference voltage generator with high manufacturing yield. Another object of the present invention is to provide a reference voltage generator suitable for IGFET integrated circuits. Still another object of the present invention is to provide a reference voltage generator and a voltage comparator that consume less power. Another object of the present invention is to provide a reference voltage generator capable of obtaining a low voltage (1.1 V or less) with excellent accuracy. Another object of the invention is a relatively low voltage (approximately 1 to
3V) power source, such as a 1.5V silver oxide battery or a 1.3V mercury battery. Another object of the present invention is to provide a reference voltage generator suitable for semiconductor integrated circuits. Another object of the present invention is to provide a highly accurate voltage comparator, stabilized power supply, constant current circuit, and battery checker. Another object of the present invention is to provide a semiconductor integrated circuit device for an electronic watch that has a built-in highly accurate battery checker and has a small number of external terminals. Another object of the present invention is to maintain the threshold voltage of an IGFET to which a back bias is applied at a substantially constant voltage independent of manufacturing variations and temperature changes;
An object of the present invention is to provide an IGFET integrated circuit that can improve manufacturing yield. Another object of the present invention is to provide a reference voltage generator compatible with complementary insulated gate field effect transistor integrated circuits (CMOS ICs), N-channel MOSICs, and P-channel MOSICs, and a method for manufacturing the same. The present invention returns to the origin of the physical properties of semiconductors and metals, and in particular, the energy gap E _g , the work function φ,
This was achieved by focusing on the Fermi level E _f etc. That is, it is well known that semiconductors have various levels such as energy gap E _g , donor, acceptor, and Fermi level, but we focused on the physical properties of these semiconductors, especially the energy gap E _g and Fermi level E _f . Since the discovery of semiconductors, such a reference voltage generator has made remarkable progress in a wide range of fields, and has never been seen before. In terms of results, the present inventors considered using this energy gap E _g , work function φ, Fermi level E _f, etc. as a reference voltage source, and succeeded in realizing it. Using energy gap E _g , Fermi level E _f, etc. as a reference voltage source is not a difficult theory in itself, and the results are easy to understand and accept. however,
In the field of semiconductor industry, which no longer has a short history, we are returning to the origins of semiconductor physical properties.
This successful example, which is believed to be unprecedented, brought about by the present inventors is original and groundbreaking, and is expected to greatly contribute to the further development of the electronic circuit and semiconductor industries in the future. According to one embodiment of the invention, two IGFETs with different conductivity types of silicon gate electrodes are fabricated within a silicon monolithic semiconductor integrated circuit chip. These FETs are manufactured under almost the same conditions except for the conductivity type of the gate electrode, so their V _th
The difference is approximately equal to the difference in the Fermi levels of P-type silicon, N-type silicon, and i-type (intrinsic semiconductor) silicon. The P-type and N-type gate electrodes are doped with respective impurities near the saturation concentration, and this difference is approximately equal to the silicon energy gap E _g (approximately 1.1V) or E _g /2 (0.55V). Used as a reference voltage source. A reference voltage generating device based on such a configuration has low temperature dependence and small manufacturing deviation, so it can be used as a reference voltage generating device for various electronic circuits. The present invention and further objects thereof will be more clearly understood from the following description with reference to the drawings. Numerous documents explain the physical properties of semiconductors, starting from the crystal structure of semiconductors and extending to the energy bands of semiconductors and the phenomena caused by donor and acceptor impurities in semiconductors. It is of course well known that semiconductors of different compositions each have their own energy gap E _g and that the energy gap E _g expressed in eV has the dimension of voltage. however,
As mentioned above, semiconductors have a unique energy gap E _g and the fact that this temperature dependence is small has been focused on, and there has never been an example of using this as a reference voltage source. Since this embodiment was developed starting from the basics of semiconductor physical properties, a detailed explanation of the present invention will first start from the fundamentals of the present invention with reference to the physical properties of semiconductors. The physical properties of semiconductors are explained in detail in many documents, so the following is one of those documents, S.
M. SZE, “physics of Semiconductor
Devices”, published by John Wiley & Sons, 1969, especially Chapter 2 “Physics and Properties”
of Semiconductors-A Resume", pages 11 to 65. Applications of Energy Gap E _g There are various compositions of semiconductors, among which the ones currently used industrially. Typical semiconductors are germanium (Ge), silicon (Si) non-compound semiconductors, and gallium arsenide (GaAs) compound semiconductors.The relationship between their energy gap E _g and temperature can be found in the book mentioned above.
It is explained on page 24 and is reproduced in Figure 1. As understood from Figure 1, Ge, Si and
The E _g of GaAs is 0.80 at room temperature (300〓), respectively.
(eV), 1.12 (eV) and 1.43 (eV). The temperature dependence is 0.39 (meV/〓), respectively.
0.24 (meV/〓) and 0.43 (meV/〓).
Therefore, by extracting a voltage corresponding to or close to these energy gaps E _g , the temperature of the forward voltage drop V _F of the PN junction diode and the threshold voltage V _th of the IGFET mentioned above can be reduced. A reference voltage generating device having a temperature dependence that is one order of magnitude smaller than the temperature dependence can be obtained. Furthermore, the voltage that can be obtained is determined by the energy gap E _g unique to semiconductors; for example, in the case of Si, it is approximately 1.12 (V) at room temperature, which is determined almost independently of other factors, and the reference voltage is not affected by variations in manufacturing conditions. It is possible to obtain. Then, the energy gap E _g of this semiconductor is
An example of how the voltage corresponding to can be derived will be explained below. Application of the difference in Fermi levels (work functions) of N-type, i-type, and P-type semiconductors The state of energy levels when a semiconductor is doped with donor and acceptor impurities is well known. Among these, the points we focused on in this invention are:
It is a physical property that the location of the Fermi energy of N-type and P-type semiconductors is divided into two toward the conduction band and the valence band, respectively, based on the Fermi energy level E _i of the intrinsic semiconductor. As the concentration of acceptor and donor impurities increases, the Fermi level E fp of the P-type semiconductor tends to move further away from the Fermi level E _i of the intrinsic semiconductor, and the Fermi level E _fp of the P-type semiconductor approaches the uppermost level E _v of the valence band. ,
The Fermi level E _fo of the N-type semiconductor approaches the lowest level E _c of the conduction band, and the difference between both Fermi levels (E _fo −
If we take E _fp ), this will be closer to the energy gap E _g of the semiconductor, and its temperature dependence will also be closer to that of the energy gap E _g . The same is true for the Fermi level difference (E _fo −E _i ) and (E _i −E _fp ) between the intrinsic semiconductor of the P-type semiconductor, and between the N-type semiconductor and the intrinsic semiconductor.
In this case the absolute value approaches E _g /2. Hereinafter, the difference from the intrinsic semiconductor will be omitted because it is half the difference between P type and N type. The details will be explained later, but the higher the impurity concentration (E _fo −E _fp )
The temperature dependence of is small, and it is preferable to set the concentration as close to the saturation concentration as possible. The Fermi levels E _fo and E _fp are related not only to the concentration of donor and acceptor impurities, but also to the donor and acceptor levels E _d and E _a , and this level
E _d and E _a differ depending on the impurity material. The closer the levels E _d and E _a are to the conduction band and valence band, respectively, the closer the Fermi levels E _fd and E _fa are to them, respectively. In other words, the shallower the impurity levels E _d and E _f of the donor and acceptor, the more the Fermi level difference (E _fo −E _fp ) becomes the energy gap E _g of the semiconductor.
becomes close to. Donor and acceptor impurity levels E _d , E _f
The closer E is to the Fermi level E _i of the intrinsic semiconductor, that is, the deeper it is, the further the Fermi level difference (E _fo −E _fp ) is away from the energy gap E _g of the semiconductor.
However, this does not necessarily mean that the temperature dependence becomes worse, but it means that the absolute value of the Fermi level difference (E _fo −E _fp ) becomes smaller. Therefore, the difference in Fermi level (E _fo −E _fp ) and the difference in work function are inherent to materials such as semiconductor materials and impurity materials, and from another perspective, they are the energy gap E _g of semiconductors. It can be used as a reference voltage source similar to Gap E _g , which is in a different category. In other words, the Fermi level difference (E _fo −E _fp ) has less temperature dependence by itself than the forward voltage drop V _F of the PN junction or the threshold voltage V _th of the IGFET, and is also less dependent on manufacturing variations. It is possible to extract the Fermi level difference (E _fo −E _fp ) using an impurity material that can serve as a reference voltage source that is not easily influenced by the voltage and exhibits shallow donor and acceptor levels E _d and E _f .
This can be one way to extract a voltage that is approximately close to the energy gap E _g of a semiconductor. On the other hand, when it comes to setting the voltage value to be obtained, if the purpose is to obtain a relatively large reference voltage equivalent to the energy gap of a semiconductor, an impurity exhibiting a shallow level is used, and a relatively large reference voltage is used. If the purpose is to obtain a small reference voltage, an impurity exhibiting a deep level may be used. Specific example of selection of impurity materials For the relationship between the Fermi level E _f , donor level E _d , acceptor level E _c , donor concentration N _d , acceptor concentration N _a and temperature T, see Figures 2 and 3. I will refer to it and explain it in more detail, but before that,
In order to understand what level each impurity exhibits in Ge, Si, and GaAs semiconductors and how to utilize these impurities in the present invention, the data on page 30 of the aforementioned document was used. It is reproduced as Figure 4 and an explanation is added. Figure 3 a, b and c are Ge, Si, respectively.
Figures 1 and 2 are diagrams showing the energy distribution of various impurities with respect to GaAs, and the numbers in each diagram are from the lowest level of the conduction band E _c to the level located above the gap center E _i represented by the broken line. The energy difference (E _c − E _d ) is shown for the lower level, and the energy difference (E _a − E _v ) from the uppermost level of the valence band E _v is shown for the lower level. is also (eV). Therefore, the impurity material indicated by a small value in the figure indicates that its level is close to the lowest source level E _c of the conduction band or the highest upper level E _v of the valence band, and the energy It is suitable as an impurity to obtain a voltage close to the gap E _g . For example, for Si, which is currently most frequently used, Li,
Donor impurities of Sb, P, As and Bi and B,
The level differences (E _c − E _d ) and (E _a −E _v ) exhibited by acceptor impurities of Al and Ga are the smallest, and each level difference is approximately 6% or less of the energy gap E _g of Si. It is. N using these impurities
Difference in Fermi level between type Si and P type Si (E _fd −
E _fa ) is Si
The energy gap is approximately 94% to 97% of E _g , which is approximately equal to E _g . In addition, the donor impurity that shows the next smallest level difference (E _c - E _d ), (E _a - E _v ) after the above impurities is S (approximately 16% of E _g ), and the acceptor impurity is I _o (E _g The difference in Fermi level between N-type Si and P-type Si using each impurity (E _fd - E _fa ) is about 0.85E _g at 0〓,
It can be seen that the deviation from the energy gap E _g of Si is about 15%, and the deviation becomes extremely large due to the above-mentioned impurities. Therefore, the impurity materials for P-type and N-type Si to obtain a voltage approximately equal to the energy gap E _g of Si include one donor impurity selected from the group of Li, Sb, P, As, and Bi; One acceptor impurity selected from the group B, Al and Ga is preferred; other impurities may be suitable for the purpose of obtaining voltages significantly smaller than the energy gap E _g of Si. Physical Properties of Fermi Level E _f Next, the physical properties of the Fermi level difference (E _fo −E _fp ) will be explained with reference to FIG. Second
The figure shows the energy level of a semiconductor. Figures a and b show an energy level model of an N-type semiconductor and its temperature characteristics, and c and d show an energy level model of a P-type semiconductor, respectively. and its temperature characteristics. The carrier in the semiconductor is a pair of an electron nd generated by ionization of the donor impurity N _d and an electron and a hole excited from the valence band. When the impurity N _d is sufficiently large, the excited electron and hole pairs can be ignored, and the number n of conduction electrons is n≒nd (1). nd is determined from the probability of being trapped in the donor level, and n is determined from the number of electrons existing in the conduction band, respectively. nd = N _d {1-1/1 + e (E _d - _{E f} /KT)} = N _d・1/1+e( _EF −E _d /KT) ...(2) n=N _c・e(E _f −E _c /KT) ...(3) Here, N _c = 2 (2πm ^* / h ² KT) ^3/2 h: blank constant, m ^* ; effective mass of electrons From this, N _c・e (E _F −E _c /KT) = N _d /1 + e (E _F −E _d /KT)…
…(4), N _d /N _c = e(E _F −E _c /KT) + e(2E _F −E _d −E _c /KT)
...(5) becomes. Here, since the Fermi level is determined to be at a position close to E _c , the first term of equation (5) can be ignored, and E _F = 1/2 (E _d + E _c ) − 1/2KTlnN _c /N _d ...(6). This equation shows that not only when the temperature is low but also when the impurity concentration N _d is high even at room temperature, N _c /N _d approaches 1, and lnN _c /N _d → 0, so the Fermi level is located between the lower end of the conduction band and the donor level, and its temperature dependence is approximately equal to the temperature characteristic of E _c . However, when the temperature becomes high enough, the number of pairs of electrons and holes excited from the valence band becomes large, and the influence of impurities decreases, causing Fermi
The level approaches the level E _i of an intrinsic semiconductor. FIG. 2b shows the above relationship. The same is true for a P-type semiconductor containing only acceptor impurities as shown in Figure 2c; at low temperatures and when the acceptor impurity concentration is high,
The Fermi level is located approximately between the top of the low electron band and the acceptor level, and as the temperature increases, it approaches the Fermi level of an intrinsic semiconductor. This relationship is shown in FIG. 2d. The relationship between the temperature characteristics of the Fermi level E _f and impurity concentration - a concrete example We have explained the physical properties of the relationship between the temperature dependence of the Fermi levels E _fp and E _fo and the impurity concentration. Using Si semiconductors that are in practical use as a specific example, and referring to the data on page 37 of the book mentioned above, we can calculate the Fermi level difference (E _fo −
E _fp ) and its temperature dependence. The data is reproduced in Figure 3. In the normal Si semiconductor integrated circuit manufacturing process, boron B and phosphorus P are mainly used as impurity materials, and in areas where the impurity concentration is high, 10 ²⁰
(atoms/cm ³ ), but even if the impurity concentration is two orders of magnitude lower, 10 ¹⁸ (atoms/cm ³ ), as can be read from Figure 3, the Fermi level of the N-type and P-type semiconductors will be The difference (E _fo −E _fp ) is 0.5 − (−0.5) = 1.0 (eV) at 300ⓓ, which is a value relatively close to the energy gap E _g 1.1 eV at the same temperature. The change with temperature is from 200〓 to 40〓(-70
℃ to 130℃), approximately 1.04 (eV) to 0.86
(eV), the rate of change is 0.9 (mV/°C). This is about 1/1 of the rate of change with temperature of the threshold voltage V _th of the IGFET and the forward drop voltage V _F of the diode, which was 2 to 3 mV/°C, as mentioned earlier.
It is a small value of 3. If the impurity concentration is 10 ²⁰ cm ^-3 or higher, silicon
The energy gap (E _g ) is almost equal to Si = 1.1 (V), and the rate of change in temperature is approximately 0.2 mV/℃,
This is a sufficiently small value. Therefore, if the impurity concentration is about 10 ¹⁸ cm ^-3 or more, it is possible to obtain a temperature dependence that is at least 1/2 to 1/3 smaller than that of the conventional method, and more preferably 10 ²⁰ cm ^-3
or higher (improved to about 1/10), and most preferably saturation concentration. Principle and example of extracting Fermi level difference In this Fermi level difference (E _fo −E _fp ), (E _fo
-E _i ) and (E _i -E _fp ) can be extracted based on what principle. One example is that the voltages corresponding to two
This method uses the difference in threshold voltage V _th of MOSFETs. A specific example will be explained below. FIG. 5 shows a conceptual cross-sectional structure of each FET. From now on, for simplicity, a MOS transistor with a P ⁺ type semiconductor as a gate electrode will be referred to as a P ⁺ gate.
MOS, a MOS transistor with an N ⁺ type semiconductor as a gate electrode is called an N ⁺ gate MOS transistor with an Si type semiconductor as a gate electrode is referred to as an i-gate MOS. In the same figure, the left half is P ⁺ , i
and N ⁺ gate P channel MOS transistors, and the right half is N ⁺ , i and P ⁺ gate N channel MOS transistors. MOSFET (Q ₁ ) ~ (Q ₃ ), (Q ₄ ) ~ in Figure 5
The difference in threshold voltage between (Q ₆ ) is shown in the table below.

[Table] Figures 6a, b to 11a, b show plane patterns actually used in circuit structures and cross-sections of plane patterns taken along the line A ^- A.
Each P-channel and N-channel of N gates
This is a representation of a MOS transistor along with its cross-sectional structure. In each of the above figures, source and drain P
The mold region is formed by diffusing impurities using polycrystalline Si as a mask. In order to ensure sufficient mask alignment between the mask for selectively diffusing P-type impurities and N-type impurities and the source and drain regions, P ⁺ gate MOS, The same impurities as the source and drain regions are diffused in both N ⁺ gate MOS. For example, in a P-channel MOS, boron, which is a P-type impurity, is diffused. In the center of the gate electrode, the P ⁺ gate MOS has a P type impurity, while the N ⁺ gate MOS
In MOS, N-type impurities are diffused. The above FIGS. 6, 7, and 8 respectively represent the plan view and cross-sectional view of the P channel P ⁺ gate, i gate, and N ⁺ gate MOS, and FIGS. 9, 10, and 11 The figure shows N ⁺ gates of N channels, respectively.
A plan view and a cross-sectional view of an i-gate N ⁺ gate MOS are shown. In Figures 6 to 11, the same impurity diffusion regions as the source and drain regions of the gate, which were taken for self-alignment, were formed on the left and right sides (source side or drain side) during manufacturing due to mask alignment errors. Due to one side being biased
In order to minimize the deviation (change) in the effective channel length of the MOS transistor, the rows of source and drain regions are arranged alternately, and the left and right halves are generally line-symmetrical with respect to the channel direction. It is arranged so that Therefore, even if the misalignment of the mask alignment in the channel direction (left and right) changes the effective channel length of the FET in each column, the P ⁺ gate MOSi gate MOS and N ⁺ gate MOS in each column connected in parallel The average effective channel length of is almost constant as the deviations are canceled out as a whole. Figure 12 shows how P ⁺ gate MOS
This shows how an N ⁺ gate MOS is constructed. In Figure 12a, 101 is a specific resistance of 1Ωcm to 8Ω
cm N-type silicon semiconductor with a thermal oxide film on top.
102 is grown to a thickness of approximately 400 Å to 16,000 Å, and a window for selective diffusion is opened using photoetching technology. Boron as a P-type impurity at 50KeV~
Boron implantation is performed at an energy of 200 KeV at an energy of about 10 ¹¹ to 10 ¹³ cm ^-2 , and then thermal diffusion is performed for about 20 hours from 8 o'clock to form a P ^-well 103 which is the substrate of an N-channel MOS transistor. In FIG. 1B, the thermal oxide film 102 is removed, a thermal oxide film 104 is formed to a thickness of about 1 μm to 2 μm, and the regions that will become the source, drain, and gate of the MOS transistor are removed by etching. Thereafter, a gate oxide film 105 with a thickness of about 300 Å to 1500 Å is formed. Polycrystalline Si 106 is grown thereon to a thickness of about 2,000 Å to 6,000 Å, and is removed by etching, leaving the gate portion of the MOS transistor. In FIG. 3c, an oxide film 107 is formed by vapor phase growth, and a region where P-type impurities are to be diffused is removed by photoetching. Then 10 ²⁰ ~ 10 ²¹ cm
By diffusing boron, which becomes a P-type impurity at a high concentration of ^-3 , the source of a P-channel MOS transistor,
A drain region 108 is formed, and at the same time, a P-type semiconductor gate electrode is formed. In Figure d, an oxide film 109 is formed by vapor phase growth as before, and the region where the N-type impurity is to be diffused is removed by photoetching. after that,
Phosphorus, which serves as an N-type impurity, is diffused at a high concentration of about 10 ²⁰ to 10 ²¹ cm ^-3 to form the source and drain regions 110 of the N-channel MOS transistor, and at the same time, the N-type impurity is diffused.
form a gate electrode of a type semiconductor. Next, the oxide film 109 is removed and by vapor phase growth.
An oxide film of approximately 4000 Å to 8000 Å is formed, and the electrode lead portion is removed by photoetching. Thereafter, metal (Al) is deposited, and electrode wiring portions are formed using photo-etching technology. Next, it is covered with an oxide film of 1 μm to 2 μm by vapor phase growth. Here, in Figure 12d, Q ₃ and Q ₄ are the general
It is a MOS that constitutes a CMOS inverter, and Q ₁ ,
_Q2 is P ⁺ gate, N ⁺ gate for reference voltage generation
It is MOS. Figures 13 a to d show P channel type P ⁺
It shows a cross section in the manufacturing process of a gate MOS and an i-gate MOS. In this example, up to c in the same figure are the same as up to c in figure 12, but in d in the same figure,
N-type impurities are diffused without removing the oxide film 1096 on the gate of _MOSFETQ2 . FIGS. 14a to 14d show cross sections during the manufacturing process of an N-channel type P ⁺ gate MOS and an N ⁺ gate MOS. FIGS. 15a to 15d show cross sections during the manufacturing process of an N channel type N ⁺ gate MOS and an i gate MOS. Next, MOS using a semiconductor as the gate electrode
The threshold voltage of the transistor will be explained with reference to FIG. First, for the case of P ⁺ gate MOS, from the energy band diagram in Figure 16a, It is shown that However _, here, V _G : Potential difference between the semiconductor substrate and _the gate electrode (P ⁺ semiconductor ₎ Fermi potential of the P-type semiconductor with reference to φ _F ; Fermi potential of the N-type semiconductor substrate q with reference to the Fermi potential of the intrinsic semiconductor; Electron potential charge V ₀ ; Potential difference applied to the insulator E _c ; Conduction Lower limit of the energy level of the band E _v ; Upper limit of the energy level of the valence band E _i ; Fermi level of the intrinsic semiconductor In Equation (7), the work function of the gate electrode is expressed as a potential and is set as φ _MP +. Similarly, if the work function of the semiconductor is φ _si , then φ _MP +=x+E _g /2q+φ _FP + ...(8) φ _si =x+E _g /2q−φ _F ...(9) Therefore, V ₀ =- V _G +φ _M −φ _si −φ _s ……(10). Also, from the charge relationship shown in FIG. 16b, -COX·V ₀ +Q _ss +Q _i +Q _B =0 (11). Here, COX; capacitance of the insulator per unit area Q _ss ; fixed charge in the insulator Q _B ; fixed charge Q _i due to ionization of impurities in the semiconductor substrate; carrier formed as a channel (10), (11) −COX(−V _G +φ _MP +−φ _S −φ _srf ) ...(12) +Q _ss +Q _i +Q _B =0 ...(12) The gate voltage V _G when channel Q _i is formed is
Since it is the threshold voltage, if the P ⁺ gate MOS threshold voltage is V _thp+ , then V _thp+ = V _G Q = 0 = φ _MP+ −φ _si −φ _s −Q _ss /COX−Q _B /COX …… (13) At this time, φ _s = 2φ _F. Similarly, in the N ⁺ gate MOS transistor, the difference is only in the work function φ _MN+ of the gate electrode, φ _MN+ =x+E _q /2q+φ _FN+ (14). Therefore, the threshold voltage V _thN+ is V _thN+ =φ _MN+ −φ _si −φ _s −Q _ss /COX−Q _B /COX (15) Here, φ _s =2φ _F. From this, the difference in threshold voltage between P ⁺ gate MOS and N ⁺ gate MOS, V _thp+ −V _thN+ , is as follows: V _thp+ −V _thN+ =φ _MP+ −φ _MN+ = φ _FP+ −φ _FN- ……(16) This is the difference in the fermi potential of the semiconductors that make up the gate electrode. This can be easily understood by comparing a and c in Figure 16 and finding that the gate voltage when the charge distribution is the same is the difference in work function of the gate electrodes, which is the difference in Fermi level. . With the above, P ⁺ gate MOS and N ⁺ gate MOS
It was found that it is possible to extract a voltage approximately equal to the energy gap E _g as the difference in the threshold voltage of
MOS (described below) threshold voltage and P ⁺ gate MOS
Alternatively, the voltage of the energy gap E _g can also be extracted from the difference with the threshold voltage of the N ⁺ gate MOS. If the threshold voltage of i-gate MOS is V _thi ,
Since the Fermi level of an intrinsic semiconductor is 0 (because it is based on the Fermi level of an intrinsic semiconductor) i
The difference in threshold voltage between the gate MOS and the P ⁺ gate MOS′ is |V _thi −V _thp+ |=|0−φ _FP+ |≒1/2E _g ……(17), and the difference between the i gate MOS and the N ⁺ gate The difference in the threshold voltage of the MOS is |V _thi −V _thN+ |=|φ _FN+ −0|≒1/2E _g ……(18), which means that the voltage is just half of the energy gap E _g It is easy to see that. The voltage obtained by the difference in threshold voltage between the i-gate MOS and the P ⁺ gate or N ⁺ gate MOS is approximately 0.55V, which is suitable for a low reference voltage source, and as will be explained later, it is possible to Without,
Since the step of doping the gate electrode with impurities can be performed in one step, it is very useful in that a highly accurate reference voltage source can be easily obtained even in the manufacturing process of a single channel MOS. Next, the process of an N-channel MOS semiconductor integrated circuit will be explained using the cross sections shown in FIGS. 17a to 17e. (1) Prepare a semiconductor substrate 101 with a specific resistance of 8 to 20 Ωcm, and deposit a thermal oxide film with a thickness of 1 μm on the surface of this substrate.
Form 103. (2) The thermal oxide film is selectively etched to expose the surface of the semiconductor substrate where the MISFET is to be formed. (3) After that, a thickness is applied to the exposed semiconductor substrate surface.
Form a gate oxide film (SiO ₂ ) 103 with a thickness of 750 to 1000 Å (Fig. 17a) (4) Selectively etch the portion of the gate oxide film 103 that should be in direct contact with the polycrystalline silicon layer to form a direct contact hole. Form 103a. (Figure 17b) (5) Oxide film 102, gate oxide film 103, contact hole
Silicon is deposited over the entire main surface of semiconductor substrate 101 having 103a by CVD (Chemical Vapor Deposition) to form a polycrystalline silicon layer with a thickness of 3000 to 5000 Å. (6) Selectively etching polycrystalline silicon layer 104. (Figure 17c) (7) The entire main surface of the semiconductor substrate 101 is coated by CVD method.
Deposit a CVD-SiO ₂ film to a thickness of 2000-3000 Å. (8) High resistance parts such as memory cell load resistance and
The CVD-SiO ₂ film 105 is selectively left only on the polycrystalline silicon layer of the intrinsic level gate portion 104a.
(Figure 17d) (9) Semiconductor substrate using polycrystalline silicon layer as a mask
Diffusion of phosphorus into 101 to reduce impurity concentration
10 ²⁰ atoms/cm ³ source and drain regions
form 106. At this time, impurities are also introduced into the polycrystalline silicon layer to form gate electrode 104b, direct contact 104c, and polycrystalline silicon wiring portion 104d. (Fig. 17d) (10) PSG (Phospho
Silicate Glass) film 107 is formed to a thickness of 7000 to 9000 Å. (11) After that, Al is deposited on the entire main surface of the quasi-conductor substrate 101 to form an Al film 108 with a thickness of 1 mm. (12) The Al film is selectively etched to form a wiring region 108. (Fig. 17e) The circuit described below can be a method for extracting the Fermi level difference (E _fo −E _fp ) (E _fo −E _i ), (E _i −E _fp ) mentioned above. , etc. Generally, it can be applied as a reference voltage generating device that uses a voltage based on the difference in V _th of FETs having different V _th as a reference voltage. FIG. 18b shows a circuit that generates a voltage corresponding to the threshold voltage of a MOS transistor. _T1 ,
T ₂ constitutes a so-called MOS diode whose drain and gate are commonly connected. I ₀ is a constant current source, T ₁ and T ₂ are different threshold voltages
It is a MOSFET with mutual conductance β almost equal to V _th1 and V _th2 , and each drain voltage is
If V ₁ and V ₂ , then I ₀ = 1/2β (V ₁ −V _th1 ) ² = −1/2β (V ₂ −V _th2 ) ² ... (17) Therefore, V ₁ = V _th1 +√ 2 ₀ ... (18) V ₂ = V _th2 +√2 ₀ ... (19) If we take the difference in drain voltage, we can extract the difference in threshold voltage. As a constant current source, a sufficiently large resistor may be used, and as long as it has the same characteristics, a diffused resistor,
Polycrystalline Si resistors, resistors made by ion implantation, and resistors made from MOS transistors can be used. If the N ⁺ gate MOS and P ⁺ gate MOS described earlier are used as T ₁ and T ₂ in this circuit, the ferromagnetism of the N-type semiconductor and the P-type semiconductor will be approximately equal to the difference in threshold voltage.・Level difference (E _fo
−E _fp ) can be extracted. FIGS. 19 and 20 are examples of circuits in which FETs having different threshold voltages are connected in series in a MOS diode format to extract the difference in threshold voltage. T ₁ is the threshold voltage V _th1 , T ₂ is the threshold voltage
Suppose you have V _th2 . Under the condition that resistance R ₁ is sufficiently large compared to the impedance of T ₁ and resistance R ₂ is sufficiently large compared to the impedance of T ₂ , V ₁ −V ₂ ≒V _th1 ...(23) V ₁ ≒V _th2 ... …(24) Therefore, V ₂ ≒V _th1 −V _th2 …(25). In FIG. 21a, a voltage corresponding to the threshold voltage is applied to both terminals of the capacitor, and the voltage held in the capacitor is extracted as a differential voltage. FIG. 21b shows the operation timing. Clock pulse φ ₁ turns on T ₅ and T ₆ and sets the capacitance to C _1.
The difference voltage between the threshold voltages V _th1 and V _th2 of T ₁ and T ₂ is charged. After φ ₁ is cut off, T ₃ is turned on by clock φ ₂ and the node of C ₁ is grounded. At this time, since the difference voltage between the threshold voltages is held in _C1 , that potential is output to the node as is. When used in a voltage detection circuit as described later, the potential of the node at this time can be used as it is as a reference voltage. However, in order to be able to use it in a more general form, the transmission gates T ₆ and T ₇ are turned on by the clock φ ₃ during the time when the clock φ ₂ is on, and the capacitance C ₂ is If the potential is taken in and received by a so-called voltage follower that fully returns the output to the negative phase input (-) of the operational amplifier 5, the output will meet the thresholds of T ₁ and T ₂ with a sufficiently low internal impedance. The difference between the value voltages is obtained as a reference voltage. FIG. 22 shows a reference voltage generating device that similarly utilizes capacitance C ₂ . Turn on _T8 by clock _φ1 . At this time, _T9 is in an off state due to clock _φ2 . The potential of the node is T ₁ less than the potential of the node
The potential of the node is lowered by the threshold voltage V _th2 of T ₂ than the potential of the node, and _the difference voltage between the two is charged across the capacitor C. Next, by turning off _T8 with _φ1 and turning on _T9 with _φ2 , a voltage difference between the threshold voltages is obtained at the node. FIG. 23 shows an operational amplifier used in the circuit of FIG. 21. T ₁ and T ₂ are a differential pair forming a differential amplifier circuit, and T ₅ and T ₆ are active loads thereof. _T7 constitutes a constant current circuit together with a bias circuit formed by _T3 and _T4 . _T8 ,
_T7 is a level conversion/output buffer circuit that uses _T7 as a constant current source load. The figure shows an example of a C-MOS circuit configuration, but single channel
Needless to say, it can also be configured with MOS. FIG. 24 schematically represents a general operational amplifier by taking only its differential part, and here MOS transistors T ₁ and T ₂ have different threshold voltages V _th1 and V _th2 , respectively. , and other characteristics are assumed to be equal. Further, the (-) and (+) symbols appearing on the input side mean that the output is in opposite phase and in phase with the output, respectively. If the input of T ₁ is V ₁ and the input of T ₂ is V ₂ , then V ₁ −V _th1 = V ₂ −V _th2 , that is, V ₁ −V ₂ = V _th1 −V _th2 (26). As a result, the output level changes. An operational amplifier has an input offset equal to the difference between the threshold voltages, and if one of the inputs is connected to ground or the power supply, it can operate as a comparator using this offset voltage as the reference voltage. I can do it. Therefore, as shown in FIG. 24, by connecting the output to the (-) input terminal and installing the (+) input terminal, a difference in threshold voltage can be obtained at the output out. In this case, _T2 needs to be in depletion mode in order to operate as an operational amplifier. For example P ⁺ gate MOS to _T1 ,
When using N ⁺ gate MOS for _T2 , both
Ion implantation may be performed under the same conditions into the channel portion of the MOSFET to form a depletion type MOSFET. In FIG. 25, the reference voltage can be arbitrarily limited using the operational amplifier shown in FIG. 24. The output is passed through voltage dividing means R ₅ and R ₆ (−)
If it is fed back to the input, and the voltage division ratio is r, then
The output voltage V ₀ is V ₀ =V _th1 −V _th2 /r (27). The voltage dividing means R ₅ and R ₆ are preferably linear resistors, but any resistors with sufficiently uniform characteristics may be used. The circuits in Figures 24 and 25 are depletion type.
While it is a prerequisite to use MOS, the second
The circuits in Figures 6 and 27 are enhancement type.
It is designed to be able to operate on MOS as well. Of course, a depression type is also acceptable. The example in Figure 26 is similar to the example in Figure 24, in which the output is directly fed back to the (-) input, and the output V ₀ is
If the power supply voltage is V _DD , then V ₀ = V _DD − (V _th1 − V _th2 ) (28). In the circuits shown in Figures 24 and 25, it is necessary to put at least one of the differential pairs into depreciation mode, which may require an increase in the number of manufacturing steps depending on the case, but it is necessary to ground the differential voltage of V _th . It can be extracted based on the potential. Conversely, in the circuits shown in FIGS. 26 and 27, the reference for the difference voltage obtained is the power supply voltage other than the ground potential, but there are no particular conditions for the operation mode of the FET. Which circuit format to adopt can be decided depending on which advantages and disadvantages are considered more important. The example in Figure 27 is the same pressure dividing means as the example in Figure 25.
The output is fed back to the (-) input through R ₇ and R ₈ , and the output is V ₀ =V _DD −V _th1 −V _th2 /r (29). Next, regarding the application of the reference voltage generator described above, the circuit, IC chip structure, etc. will be explained. Control of threshold voltage This is a local element in MOS integrated circuits.
The threshold voltage (V _th ) of a MOSFET is an important parameter that determines the characteristics of an LSI. this
V _th has large variations due to manufacturing processes and changes due to temperature, and controlling VS _th is a difficult point in MOSFSI manufacturing. On the other hand, in the MOS memory shown as an example in FIG. 28, a bias voltage is applied to the substrate to reduce parasitic capacitance. A substrate bias generation circuit is used to obtain this bias voltage. The substrate bias generation circuit has the configuration shown in FIG. 29. Conventional substrate bias generation circuits consist only of an oscillation section and a waveform shaping section, and generally do not provide feedback based on V _th . For this reason, differences in oscillation frequency and waveform shaping ability occur due to manufacturing variations and temperature, resulting in a stable back bias voltage.
V _BB could not be obtained, and the fluctuations in V _th were large. In the present invention, a comparator using the aforementioned work function difference between the gate electrodes is used in this substrate bias generation circuit to control V _th to a constant voltage. V _th changes depending on the substrate bias and is expressed by the following equation. V _th =V _th0 +K(2φ _F +|V _BB |−2φ _F ) Here, V _th0 is V _th of V _BB =OG, K is the substrate effect constant, and φ _F is the Fermi level. Therefore, V _th can be controlled by changing the substrate bias V _BB . In FIG. 29, the oscillation circuit section uses a ring onlator. This oscillation circuit may be replaced by another oscillation circuit. The waveform shaping section consists of two MOS diodes Q ₁ ,
It consists of Q ₂ and capacitor C ₁ , and has the function of drawing the charge of V _BB to GND by pumping action.
Due to this pumping action, V _BB is pulled to a negative voltage, but the maximum voltage V _BBM of |V _BB | is determined at the point where the drawing voltage due to this pumping action and the substrate leakage current are stable. As long as the oscillation circuit is operating, V _BB is maintained at this stable point V _BBM , but when oscillation stops, the charge on the substrate leaks due to substrate leakage current and approaches the GND level. V _BB is
V _th decreases as it approaches the GND level. The comparator section shown in FIG. 29 utilizes the aforementioned work function difference between the gate electrodes, and an example in an N-channel process is shown in FIG. 30. Third
In Figure 0, _Q1 uses an intrinsic level gate MOS, and _Q2 uses an N gate MOS. Also, these are depression type MOS. For this reason,
The comparator is inverted when a voltage of E _g /2 = 0.55V is input to one input. The V _th sense section in FIG. 29 consists of one resistor and MOSFET _Q3 . The resistance here can be either a polysilicon resistance diffusion layer resistance or a MOS resistance, but the resistance value is determined by the V _th of Q ₃ .
The output is set to 0.55V when the voltage reaches 0.55V. Now V _BB is close to GND level and V _th of Q ₃
When is below 0.55V, the input voltage to the comparator section is below 0.55V, the output of the comparator becomes "1" and the oscillation circuit continues to operate. _VBB
approaches _VBBM , _Vth increases, and when it exceeds 0.55V, the comparator output becomes "0", oscillation stops, and _VBB approaches the GND level due to leakage. That is, a feedback loop is formed, and V _th is controlled by this substrate bias generation circuit. Voltage obtained at comparator section: 0.55V
is 1/2 of the energy gap, and as mentioned above, there is little change with temperature, manufacturing variations, and power supply voltage, so it is possible to control V _th with extremely high accuracy, and the temperature margin, manufacturing process margin, A MOSLSI with a wide power supply margin can be obtained. In addition, as will be explained later, there is also a third
Intrinsic level gates are formed using exactly the same process as the process used to obtain high resistance R in the memory cell shown in Figure 2.
Since MOS can be obtained, it can be easily realized using conventional processes. In the level shift circuit MOSLSI, a 5V power supply is used as the power supply,
When using a signal from a TTL logic circuit as input, 2.0V as high level and 2.0V as low level.
The signal will be 0.8V. Conventionally, when converting this TTL signal to MOS level, the ratio of the input inverter was taken and converted to MOS level, but V _th
There was a problem that the input level margin became smaller due to variations and temperature changes. An example of a TTL to MOS conversion circuit using the reference voltage generation circuit using the work function difference of the gate electrodes described above is shown. FIG. 32 shows a specific example of using this method in an address buffer circuit of a MOS memory. The reference voltage is set as V _ref by the circuit shown in Figure 25 above.
Generates 1.4V. An input buffer with an input logic V _th of 1.4V is created using the differential amplifier shown in FIG. 33 as an amplifier. With this method, TTL→
A MOS conversion circuit is obtained. Alternatively, V _ref, that is, GND in FIG. 24 may be input to the amplifier using the path shown in FIG. 23. In this case, depletion type MOSs are used for T ₁ and T ₂ . Logic V _th Stabilization Circuit Figure 34 shows the logic thresholds of logic circuits such as inverters used for power supply voltage,
The goal is to keep the threshold voltage of the MOS transistor constant despite changes in the threshold voltage, temperature, etc. Inverter 1 consisting of Q ₁ , Q ₂ , Q _{3 ,} Q ₄ ,
The inverter 2 composed of Q ₅ and Q ₆ each has MOS Q ₁ and Q ₄ for logic threshold control. Q ₇ , Q ₈ , and Q ₉ are configured to be similar to inverter 1 and inverter 2 (the MOS pattern size ratio is the same), and the input and output of the inverter are combined, so that The logic threshold voltage can now be obtained. CMP1 is a comparator circuit having the reference voltage described above as the offset of the differential circuit.
CMP1 compares this logic threshold with its internal reference voltage and controls the gate voltage of _Q7 so that the difference between the two becomes almost zero. In other words, if logic threshold > reference voltage, the output of CMP1 will be high level and Q ₇
The equivalent resistance becomes larger, which acts to lower the logic threshold. If the logic threshold is smaller than the reference voltage, the opposite is true, and the two are in equilibrium when they are equal. The gate voltages of Q ₁ and Q ₄ are common to the gate voltage of Q ₇ , and the former and the latter have a similar relationship, so the logic thresholds of inverters 1 and 2 become equal to the reference voltage,
This results in very stable inverter characteristics. As mentioned at the outset, this is not necessarily applicable only to inverters, but is equally applicable to other logic circuits such as Nando-Noah. Even if it is not a CMOS configuration, it can also be used for logic circuits such as ordinary single channel inverters.
Easy to apply. These circuits are particularly useful as input interface circuits that can reliably digitally process signals even when the range of input level and logic amplitude is narrow. Voltage Detector Figure 35 shows how the reference voltage from the reference voltage generator that uses the difference in V _th is applied to one input of the comparator, the detected voltage is added to the other input, and the reference voltage of the detected voltage is This is a voltage detection circuit that can distinguish between high and low voltages. In the example shown in FIG. 36, the reference voltage from the reference voltage generator using the difference in V _th is applied to one input of the comparator, and the detected voltage is applied to the other input of the voltage dividing means R ₉ ,
This is a voltage detection circuit that applies a voltage divided by _R10 . Let r be the voltage division ratio, V _ref be the reference voltage, and V _seose be the detection level, then V _seose = V _ref /r (30), and the detection level V _seose can be arbitrarily set by the voltage division ratio r. The example shown in FIG. 37 is a voltage detection circuit that uses an operational amplifier having an offset corresponding to the difference in V _th and uses the offset voltage as the reference voltage as described above. Also, R ₁₁ and R ₁₂ are the 36th
This is the same pressure dividing means as in the example shown. In the examples shown in FIGS. 36, 36, and 37, if the voltage to be detected is the power supply voltage, it can be used as a battery checker in a system using a battery as the power supply. A specific example in which the voltage detection circuit of FIG. 37 is applied to a battery checker for an electronic watch is shown in FIG. 44, and detailed explanation will be given later. Constant Voltage Device The example shown in FIG. 38 is applied to a stabilized power supply circuit. The reference voltage generation circuit is constructed using the several methods described above, and compares a part of the stabilized output with the reference voltage using R ₁₃ and R ₁₄ , and adjusts the gate voltage of T ₂₀ so that they match. control and stabilize the output voltage. Any operational amplifier may be used as long as its characteristics are acceptable. The example of FIG. 39 uses a bipolar transistor TR ₁ instead of the MOS transistor T ₂₀ in the example of FIG. 38. The example shown in FIG. 40 uses the operational amplifier having the offset voltage shown in the example shown in FIG. Of course, T ₂₁ may be a MOS transistor, a bipolar transistor, or a junction field effect transistor. Constant Current Device The example in FIG. 41 is a constant current circuit determined by the difference between the threshold voltages of T ₁ and T ₂ . T ₁ and T ₂ have the same mutual conductance β,
The threshold voltages are V _th1 and V _th2 which are different from each other. If the resistance R ₂₀ is sufficiently high compared to the impedance of T ₁ , the drain voltage (= gate voltage) V ₁ of T ₁ will be
Almost equal to V _th1 . When T ₂ is in the saturation region, the current I ₂ flowing through T ₂ is I=1/2β(V _th1 −V _th2 ) ² (31). The example in Figure 42 is a constant current circuit that compares the voltage drop I _put R ₂₁ due to the current I flowing through T ₂₂ with the reference voltage V _ref and controls the gate voltage of T ₁ so that both are always equal. It is. From I _put R ₂₁ = V _ref , I _put = V _ref /R (32). Here, the reference voltage may be obtained by providing an operational amplifier with an offset, as in the previous example. The example shown in FIG. 43 is a constant current circuit using a so-called current mirror circuit in which T ₃₁ and T ₃₃ are the same transistor. Electronic clock The example shown in FIG. 44 is an example in which the battery checker shown in FIG. 37 is applied to an electronic clock. T ₁ , T ₁ , T ₄₁ to T ₄₉ and R ₄₁ and R ₄₂ are nominally 1.5V
Construct a circuit to check the voltage level of the mercury battery _E1 . The transistor pair in the differential section is composed of P ⁺ gate/N channel - MOS, N ⁺ gate/N channel - MOST ₁ , T ₂ , and the threshold voltage of both is 1.0 V ~ which is the operating power supply range of electronic watches. 1.5V
Ion implantation is performed in the channel part so that the The difference in threshold voltage, which is the reference voltage, is approximately 1.1V in the case of silicon semiconductors, and in order to adjust the level at which the battery voltage drops to around 1.4V, the resistance means R ₁ and R ₂ are used. It is adjusted by the resistance ratio. This battery checker is operated intermittently by the clock signal φ obtained from the frequency divider circuit FD through the timing circuit TM in order to reduce the current consumption to a practically negligible level. The output of the battery checker is a NAND gate
It is held statically by a latch composed of NA ₁ and NA ₂ , and the logic level of this latch circuit output controls the timing circuit TM, thereby changing the drive output of the motor and changing the way the hands move. to display battery voltage drop. The decrease in battery voltage does not change the movement of the pointer, and can also be indicated by blinking an electro-optical element such as a liquid crystal or a light emitting diode. In the same figure, the OSC is composed of a CMOS inverter, and a partial crystal X _ta1 and a capacitance C _G ,
A crystal oscillation circuit including C _D , WS is a waveform shaping circuit that converts the oscillation output from a sine wave to a square wave,
_CM is an excitation coil for a step motor that drives the second hand, and BF ₁ and BF ₂ are buffers that are composed of CMOS inverters and drive the excitation coil _CM by reversing its polarity every second. All circuits within the IC are powered by a mercury battery _E1 with a nominal 1.5V. In addition, TM is a timing pulse generation circuit that generates an pulse with an arbitrary period and pulse width by inputting the divided outputs of the frequency divider circuit FD with different frequencies and the control output of the latch composed of NA ₁ and NA ₂ . It is. The IC is a monolithic Si semiconductor chip for a pointer type electronic wristwatch manufactured using the Si gate CMOS process shown in Fig. 6. Although the present invention has been described above based on various embodiments, it is not limited thereto, and the technical idea described herein may be applied to electronic devices for various other uses. Next, a specific example will be described in which the reference voltage generating means according to the present invention is applied to a state setting circuit, an auto clear circuit, etc. of an electronic device. FIG. 45 is a circuit diagram showing an example of a state setting circuit, which is composed of four MOSFETs. In the same figure, when the potentials at points a and b are 0, MOSFETT ₁ and T ₃ are N- when the power supply (-V _DD ) is turned on.
Since it is a MOSFET, both are in the “ON” state,
Points a and b are on the power supply side (-
V _DD ). At this time, N- of T ₃
MOSFETs utilize the energy band difference of semiconductors, and their V _thN is approximately three times that of MOSFET ₁ (e.g. T ₁ V _th = 0.45V, T ₃ V _th = 1.25V), so the power supply In the middle of the fall of
MOSFETT ₃ is turned “OFF” first.
Since MOSFETT ₁ continues to be in the "ON" state, point b becomes stable at the potential of -V _DD and point a becomes stable at the potential of GND. Also, with the power (-V _DD ) turned off, at point a
OV, if a charge remains at about 1V at point b, V _DD =
T ₃ is “OFF” until V _thN of MOSFETT ₃ , and MOSFETT ₁ is “ON” at V _DD = T ₁ V _thN .
In the initial state, point a is OV and point b is
Even if the voltage is about 1 V (or up to V _thN of T ₃ ), in a stable state, point b is V _DD and point a is OV. Furthermore, since this circuit is entirely composed of E-MOSFETs, current consumption in a stable state is almost zero. FIG. 46 is a circuit diagram showing an example of a conventionally proposed state setting circuit. In the same figure, a _T1 N-channel D (depletion) MOSFET is inserted to increase the stability of the latch circuit. .
When the power (-V _DD ) is turned on by this D-MOSFET,
Point a always falls at the same time as the power supply, and point b
If the power does not fall to V _th of MOSFETT ₄ ,
Since it is not turned on, in a stable state, point b is at V _DD and point a is at OV. However, in this circuit, a D-MOSFET is used between point a and V _DD , so next time when point a becomes V _DD and point b OV (RESET) state, P-MOSFET ₃ becomes “ON” and T ₁
A DC path occurs due to T ₃ and current consumption increases.
On the other hand, the state setting circuit of the present invention as shown in FIG. 45 can reliably set the state as described above and consumes only a very small amount of current, thus providing an effective state setting means. Next, a voltage regulator according to the present invention and an example of its application will be explained. FIG. 47 shows a voltage regulator according to the present invention, and FIG. 48 shows its characteristic diagram. The comparison type voltage regulator shown in FIG. 47 has a structure similar to that of a known one,
It differs from a normal voltage comparator in that the voltage level is asymmetrical when viewed from both the positive and negative input terminals. In other words, this voltage comparator is not balanced when the voltage levels of both the positive and negative inputs are equal, but is balanced when a predetermined high input voltage (in absolute value) is applied to the negative side. In other words, in this voltage comparator, the positive and negative input levels have offsets with respect to the balance point. According to such a voltage regulator, when the input voltage V _io is high, the output voltage V _put depends on the reference voltage V _ref and a large difference |V _put −V _io | is taken, but when the input voltage V _io is low V _put depends exclusively on V _io ,
The difference between |V _io −V _put | is made small. Both change points P are set at the point V _io V ₁ with respect to the input voltage V _io (V ₁ is the lowest operating voltage of the regulator load ∠). According to the voltage regulator configured in this way, when the input voltage V _io is high, the load ∠ is operated at the output voltage V _put which is higher than the minimum operating voltage V ₁ but lower than the input voltage V _io . , power consumption is reduced while operation is guaranteed. Also the input voltage
When V _io is low, the load ∠ is operated with an output voltage V _put approximately equal to or slightly less than the input voltage V _io , thus guaranteeing a minimum operating voltage V ₁ for the input voltage V _io of the load ∠, and a high For the input voltage V _io , the output voltage V _put is reduced to a voltage that matches the load ∠, so this voltage regulator has low power consumption and a wide range of input voltage V _io for the load ∠. be able to. These effects will be explained in detail using the graph of FIG. 48 in comparison with a voltage comparator regulator having no offset. In the same figure, the horizontal axis is the input voltage V _io and the vertical axis is the output
V _put and reference voltage V _ref are shown. Curve a is
It shows V _put equal to V _io , in other words,
This shows a hypothetical curve when the load ∠ is operated directly at the input voltage V _io without using a voltage regulator. Curve C shows the general reference voltage _Vref1 ,
Normal reference voltage generation circuit V _ref GENFET threshold voltage V _th , current amplification factor 13 transconductance
g _n , or the forward and reverse voltage drop V _F of the PN junction,
Since V _Z and the current amplification factor h _fe of the bipolar transistor are used, the output voltage V _ref of V _ref GEN depends on its power supply voltage V _io {V _ref =f(V _io )}. When such a reference voltage V _ref1 is used as the reference voltage of the voltage comparison circuit CP, and the offset described above is not provided in the comparison circuit CP,
The output voltage V _put is equal to the reference voltage V _ref1 and curve C
matches. And the reference voltage V _ref1 is the input voltage
Since it can never be higher than V _io , the output voltage V _put
is lower than the input voltage V _io in any range. As a result, the input voltage V _io when the output voltage V _put is equal to the lowest operating voltage V ₁ of the load ∠ (point R)
becomes V ₂ (V ₂ >V ₁ ). Therefore, in the usable range of the input voltage V _io seen from the load ∠, a loss occurs by a voltage corresponding to |V ₂ −V ₁ |. In order to reduce this loss, in the voltage regulator of FIG. 47, the comparator CP is configured so that it is balanced when the negative input becomes higher than the positive input by the offset voltage ΔV _pff . In addition, as a reference voltage, a virtual reference voltage V _ref1
Using a reference voltage V _ref2 (curve d) that is smaller than , and has similar characteristics, the effective comparison voltage (V _ref2 +ΔV _pff ) at the target normal input voltage V ₃ is the virtual reference voltage.
The values of V _ref2 and ΔV _pff are set to be equal to V _ref1 , that is, to match the target operating point S. According to such a configuration, the voltage comparator CP is
Equilibrium is achieved under the condition of V _put = V _ref2 + ΔV _pff , and the input voltage V _io that satisfies this equilibrium condition is V _io V _put .
This occurs only when V _io V _ref2 +ΔV _pff . If the input voltage V _io is smaller than (V _ref2 + ΔV _pff ), the output voltage V _io will also be smaller than that, so the comparator CP works to increase the output voltage V _put , but this feedback control works by inputting the output voltage V _put It is limited when it is equal to the voltage V _io (because of V _put V _io ). Therefore, the output voltage V _put is reduced (limited) to V _ref2 + ΔV _pff when the input voltage V _io is higher than the inflection point (P) with V _io = V _ref2 + ΔV _pff as the inflection point (P) (curve b ₁ ), approximately the input voltage when V _io is lower than
V _io (curve a ₂ ). If this inflection point P is equal to or higher than the lowest operating voltage V ₁ (point Q) with respect to the input voltage V _io (on the horizontal axis), the above-mentioned loss can be avoided. This is because curve b has an intersection with curve a due to ΔV _pff , and this effect cannot be obtained when curve d does not have an intersection with curve a. Note that the FET in Figure 47 works as a source follower but is a depletion mode N-channel FET, so V _put = V _io is possible.
There is no loss of its threshold voltage V _th . Therefore, this is effective when the input voltage V _io is small. However, this does not negate the use of enhancement mode source follower FETs, but rather depletion mode FETs where the input voltage is large and V _th losses are not a critical issue.
It is extremely effective when it is difficult to adopt a manufacturing process. In this case, the lower output voltage V _put
(below the change point P) curve a ₂ (V _put = V _io )
is shifted downward by V _th (V _put = V _io −
V _th ), and it is still possible to give the output voltage V _put the effect described above. In addition, the N-channel FET in the diagram is replaced with the P-channel FET.
It can also be replaced with a FET; in this case, the P-channel FET works as a common source, so the above-mentioned
There is no loss of V _th . There is no essential difference whether a source-grounded or source-follower is used as a control FET, but if a source-grounded FET is used, special consideration must be given to threshold voltage V _th loss, such as when using a depletion mode FET. Not. In addition, when using a source follower, it is useful when it is necessary to sample the voltage comparison operation (for example, when the comparator
When clock driving the CP to reduce power consumption), this FET is useful because it works as a voltage follower. In other words, if the mutual conductance g _n of this FET is sufficiently high, the output voltage is uniquely determined by the gate voltage. It is also possible to use a bipolar transistor as the control transistor. Although it is not necessarily denied that the offset V _pff is a function of the input voltage V _io , in setting the inflection point P, it is desirable that it be constant with respect to V _io . Furthermore, if a reference voltage having a variable element similar to that of the load ∠ is used as the reference voltage V _ref2 , it is also convenient because the output voltage V _put can be obtained in accordance with the characteristics of the load ∠. In that case, if you set V _ref2 to the lowest voltage that operates the load ∠,
ΔV _pff can be used as a constant margin measure. The configuration that provides the offset ΔV _pff and its application circuit will be described later, but here the output voltage
Another method of providing an inflection point to V _put will be explained using the circuit diagram of FIG. 49 and the graph of FIG. 50. In the following explanation and the graph of FIG. 50, all voltage values are absolute values. In FIG. 49, _Q107 is a control transistor consisting of an N-channel depletion mode FET. Q ₁₀₁ and Q ₁₀₂ as well as Q ₁₀₄ and Q ₁₀₆ constitute a current mirror circuit, and a drain current approximately equal to the drain current of Q ₁₀₃ flows through the diode-grounded FETs _{Q 104} and Q ₁₀₅ . Diode connected P-channel FETQ ₁₀₄ , N-channel
The source-drain voltage drop V _DS of FETQ ₁₀₅ is
The high impedance loads Q ₁₀₂ and Q ₁₀₆ result in approximately the respective threshold voltages V _thp and V _tho . Therefore, voltages of V _thp and (V _io −V _tho ) are applied to both the positive and negative input terminals of the comparator CP, respectively (curves d and b in FIG. 50). Comparator CP has no offset and is therefore balanced when both inputs are equal. Therefore, the equilibrium condition is (V _put - V _tho ) = V _tho , that is, V _put = V _thp
+V _tho . From the conditions of V _io V _put , the output voltage
V _put is limited to (V _thp +V _tho ) when V _io V _thp +V _tho , and becomes approximately equal to V _io when V _io V _thp +V _tho . Therefore, if the load ∠ is composed of CMOS, its lower operating limit voltage is usually (V _thp +
V _tho ), so the output voltage V _put can compensate for it. Note that the threshold voltage taken out by the MOS diode circuit is close to the original threshold voltage, but not equal, and follows its drain current.
The output voltage V _put at the equilibrium point is of course the original (V _thp + V _tho )
It is better to make each
The mutual conductance of FETQ ₁₀₃ should be made small so that the current flowing through MOS diodes Q ₁₀₄ and Q ₁₀₅ is made small. In addition, since the near threshold voltage extracted by the MOS diode is based on the assumption that drain current flows, the circuit must be configured so that current flows through both diodes even if the input voltage V _io becomes low. Must be. Next, an example in which the voltage regulator shown in FIG. 49 is applied to an electronic timepiece will be explained using FIG. 51. In Figure 51, OSC is a crystal oscillator, WS is a waveform shaping circuit that converts the sine wave oscillation output into a rectangular wave, FD is a frequency dividing circuit, and TM is the timing for creating a pulse with a predetermined period and width from the frequency divided output.・Pulse generation circuit, LF is a level shift circuit that converts a low level signal to a high level signal, BC is a battery life detector, VC is a voltage comparator, VR is a voltage regulator using it, H is a hold circuit,
DT is an oscillation state detector, and LM is an excitation coil for the step motor that drives the second hand. The detector DT detects that the OSC oscillates using a frequency divider.
FD is detected through the timing circuit TM, and when oscillation occurs, the voltage regulator VR is activated to adjust the operating power supply voltage of the oscillator OSC and WS, FD, TM, etc.
Drop from 1.5V. At the moment when battery E is inserted, the input node of inverter _I7 is connected to ground potential (logic "0") by discharge resistor _R104 .
Since it is becoming popular, N Qiuyannel FETQ ₂₀₁ is
ON state, and the output of the regulator is set to the battery voltage.
Set it to 1.5V. At this time, Q ₂₀₃ is also turned on,
Keep the gate node of FETQ ₂₀₂ charged. This is to activate the negative feedback loop of the regulator in advance so that the regulator output does not drop the moment FETQ ₂₀₁ is next switched OFF. When the oscillator starts operating, other logic circuits are already in operation, so the timing circuit
A pulse φ _B is supplied from TM to the detector DT. The exclusive OR circuit EX ₁ detects the output of this pulse φ _B , and one input is delayed by inverters I ₄ , I ₅ and integration circuits C ₁₀₁ , R ₁₀₃ relative to the other. A pulse φ _B is applied. Therefore, when the pulse φ _B is output, a pulse with a width corresponding to the delay time is generated at the output of the gate _EX1 . This pulse is
It is integrated in the rectifier circuit consisting of FETQ ₂₂₅ , inverter I ₆ and capacitor C ₁₀₂ , and after a while after φ _B starts appearing, the N channel, FETQ ₂₀₁ and Q ₂₀₃ are integrated.
Turn it off. Thereby, the regulator VR generates a predetermined output voltage (less than 1.5V) only by its own control loop, contributing to low power consumption. Below, this regulator, especially the voltage comparator VC
Explain the operation. This comparator VC is the comparator CP explained in the principle diagram in Figure 47 and the characteristic diagram in Figure 48.
Since the operation is similar to that, I will keep the explanation simple. In order to obtain the offset voltage V _pff of the P channel MOSFETs Q ₂₀₆ and Q ₂₀₇ , the gate of Q ₂₀₆ is made P type as shown in _FIG . ₅ and Q 1 in FIG. _2. It is made into an N type as shown in Figure 7.
Therefore, _the threshold voltage V _th of Q ₂₀₇ is approximately
0.55V higher, which is the offset voltage mentioned above.
Take V _pff . N channel FETQ ₂₀₈ and P channel
FETQ ₂₀₉ are both diode connected, so
The sum of both V _th (V _thp +V _tho ) is applied to the gate of Q ₂₀₇ , which is the positive input of the comparator VC, and this becomes the voltage V _ref2 shown in curve d of FIGS. 48 and 50. Therefore, the output voltage V _put of the voltage regulator VR
is V _put = V _thp + V _tho + ΔV _pff (V _io V _thp + V _tho +
ΔV _pff ). When the input voltage V _io is low, V _put =V _io as described above. The operating time of this comparator is limited by the timing signal _φA in order to reduce power consumption. Of course, the same applies to the circuit that obtains the reference voltage V _ref2 , so the capacitor C ₁₀₄ holds the voltage of the reference voltage V _ref2 , and the capacitor C ₁₀₅ holds the gate voltage of Q ₂₀₂ due to the parasitic capacitance such as the gate capacitance. has been added separately. The capacitor _C103 is used to prevent oscillation caused by a phase rotation caused by several FETs connected in series in the feedback loop. Since the battery checker BC has almost the same structure as shown in FIG. 44, its explanation will be omitted. In addition, the excitation coil drivers I ₂ and I ₃ are used at the output stage of the IC.
uses a 1.5V battery as a direct power source to increase drive capacity. Figure 52 shows the voltage regulator VR according to the present invention.
An example of applying the Batsuteri-Chetzker BC to a digital display electronic clock is shown. In the same figure, OSC, WS, and FD are powered by a regulated voltage lower than 1.5V, similar to the example in Figure 51,
In addition, logic circuits inside the IC such as the deco radar DC time correction circuit TC also use a low voltage as a power source. DB is a signal voltage circuit that boosts the voltage of 1.5V to 3.0V, and this voltage is used as the drive voltage of the liquid crystal display device DP (the driver is omitted). ∠
S is a level shift circuit, which converts a low signal level into a high DC signal level and supplies it to a circuit with a high power supply voltage. In this way, normal logic circuits inside ICs that operate at low operating voltages require low operating power supplies, and display drivers, etc. that require high operating voltages at the input/output interface of the IC, use high operating power supplies. It is effective in reducing power consumption and expanding the range of power sources used.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the energy gap E _g of GaAs, Si and Ge semiconductors and its temperature dependence. Figure 2 shows the semiconductor band structure and Fermi level.
This is a diagram showing E _f , and a and b of the same diagram are
Figures c and d are diagrams showing the band structure and Fermi level of a P-type semiconductor, respectively. Figure 3 shows N type and P type
FIG. 3 is a diagram showing the temperature characteristics of the Fermi level of Si using impurity concentration as a parameter. FIGS. 4a, 4b and 4c are diagrams showing the distribution of energy levels of Ge, si and GaAs semiconductors and various donor and acceptor impurities, respectively. Figure 5 shows ^{the P +} _{gate and} N ⁺
The cross-sectional structure of a gate MOSFET is schematically shown, with the left half showing a P-channel FET and the right half showing an N-channel FET. Figures 6a and b show a plan view and cross-sectional view of a P ⁺ gate P-channel MOSFET, respectively, and Figures 7a and b show an i-gate P channel MOSFET.
Figure 8 a and b are the plan view and cross-sectional view of the MOSFET.
The plan view and cross-sectional view of the N ⁺ gate P channel ^MOSFET are shown in Figure 9 a and b.
The plan view and cross-sectional view of the MOSFET are shown in Figure 10a and b.
11A and 11B show a plan view and a sectional view of an i-gate N-channel MOSFET, and FIGS. 11a and 11b show a plan view and a sectional view of a P ⁺ gate N-channel MOSFET. Figure 12 a-d, Figure 13 a-d, Figure 14 a-d
and FIGS. 15a to 15d are cross-sectional views of main steps in manufacturing complementary MOS. Figure 16a and b are respectively P ⁺
The energy state and charge state of the type semiconductor-insulator-N type semiconductor structure are shown in c and d of the same figure, respectively.
FIG. 3 is a diagram showing the energy state and charge state of an N ⁺ type semiconductor-insulator-N type semiconductor structure. FIGS. 17a to 17e are cross-sectional views in each manufacturing process of the N-channel MOSFET. Figures 18a and b show the V _th of two FETs with different threshold voltages V _th .
FIG. 2 is a diagram showing a characteristic diagram of a MOS diode circuit for extracting the difference between the two and the circuit thereof. 19 and 20 each show an example of a reference voltage generation circuit that utilizes the difference in V _th , FIG. 21a shows an example of another reference voltage generation circuit, and FIG. 21b shows its timing signal waveform. shows. FIGS. 22 to 27 show reference voltage generating circuits based on still other embodiments. FIG. 28 shows a block diagram of a semiconductor memory, and the second
FIG. 9 shows a detailed circuit diagram of the substrate bias generation circuit of FIG. 28. Figure 30, Figure 31, Figure 32,
FIG. 33 shows circuit diagrams of a comparator circuit, a memory cell circuit, an address buffer circuit, and a differential amplifier, respectively. FIG. 34 shows a circuit diagram of the logic circuit. Figures 35 to 37 show examples in which the reference voltage generation circuit is applied to a voltage detection circuit, Figures 38 to 40 show examples in which it is applied to a voltage regulator, and Figures 41 to 40 show examples in which it is applied to a voltage regulator.
FIG. 43 shows an example of application to a constant current circuit, and FIG. 44 shows an example of application to a battery checker for an electronic wristwatch. FIGS. 45 and 46 are circuit diagrams for explaining examples of the present invention and conventional state setting circuits, respectively. FIG. 47 is a circuit diagram for explaining an example of the voltage regulator according to the present invention, and FIG. 48 is an electrical characteristic diagram for explaining its operation. FIG. 49 is a circuit diagram for explaining another example of the voltage regulator according to the present invention, and FIG. 50 is an electrical characteristic diagram for explaining its operation. FIG. 51 is a circuit diagram for explaining an example in which the present invention is applied to an electronic watch;
The figure is a circuit system diagram for explaining an example of application to a digital display electronic watch. T...MOSFET, R...resistor, C...capacitor, X _ta1 ...crystal resonator, OSC...crystal oscillation circuit, WS...sine wave-square wave conversion waveform shaping circuit,
FD...Binary counter multi-stage connection frequency divider circuit, TM...
...Timing circuit, CM...Excitation coil of step motor for driving the second _hand , BF...Buffer for driving CM, N _A ...NAND gate, IC...Monolithic Si semiconductor integrated circuit chip, φ...Clock pulse, E _g ...Semiconductor energy gap, E _v
...the highest level of the valence band, E _c ...the lowest level of the conduction band, E _i ...the Fermi level of the intrinsic semiconductor, E _fo ,
E _fp ... Fermi level of N-type and P-type semiconductors, E _d ,
E _a ...donor, acceptor level.

Claims (1)

[Claims] 1. A logic circuit having an input terminal and a control terminal, the logic threshold voltage of which is changed in accordance with a control signal supplied to the control terminal; a logic threshold voltage such that the potential at a point is determined by the potential at the output point, thereby forming a detection voltage at the output point corresponding to the logic threshold voltage of the logic circuit; The first and second input IGFETs include a detection circuit and first and second input IGFETs having different threshold voltages.
and a voltage comparator circuit having a threshold voltage formed based on the threshold voltage difference of two IGFETs, one of the pair of inputs of the voltage comparator circuit is brought to a predetermined potential, and the logic threshold voltage is set to a predetermined potential. The detected voltage of the voltage detection circuit is supplied to the other input of the voltage comparison circuit, and the output of the voltage comparison circuit is supplied to the control terminal of the logic circuit and the logic threshold voltage detection circuit. Features of semiconductor integrated circuit devices. 2. The logic circuit is provided between a logic stage and a first potential point, and has a gate connected to the control terminal so as to be controlled by an output signal taken out from the output terminal of the comparison circuit. The first time
3IGFET, the logic threshold voltage detection circuit is provided between a logic threshold voltage detection stage and a first potential point, and is controlled by the output signal. 3. The semiconductor integrated circuit device according to claim 2, further comprising a fourth IGFET whose gate serves as the control terminal. 3. Claim 1, wherein the difference in threshold voltage of the first and second IGFETs is based on the Fermi level difference of their gate electrodes.
The semiconductor integrated circuit device according to item 2 or 3. 4. The semiconductor integrated circuit device according to claim 4, wherein each of the gate electrodes of the first and second IGFETs has a semiconductor layer portion having a different conductivity type.