JPH039682A - Time compressing circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a time compression circuit, and in particular, to digital processing when displaying a reproduced image of an NTSC television signal converted to progressive scanning on a high-definition display. This relates to a circuit that compresses time so that the linearity of reproduced images does not change.

[Conventional technology]

A reproduced image of an NTSC television signal converted to progressive scanning (hereinafter referred to as an NTSC signal) has a frame frequency of 59.94 (Hz) and a horizontal frequency of 31.4.
7 (K)Iz). On the other hand, high-definition signals
Field frequency is 60 (llz), horizontal frequency is 3
3.75 (Kflz). Therefore, since the vertical and horizontal frequencies of the NTSC signal and the high-definition signal are very close, the NTSC signal can be displayed on a high-definition display. At this time, since the ratio of the vertical blanking period to one frame period is defined at exactly the same value for the NTSC display and the high-definition display, there is no problem in displaying in the vertical direction.

However, while the aspect ratio of NTSC signals is 4:3, the aspect ratio of high-definition signals is 16:9.
It is.

Further, the ratio of the horizontal blanking period to one horizontal scanning period is approximately 5:4 in an NTSC display and a high-definition display. Therefore, if we keep the vertical ratio constant and find the ratio of the number of unit pixels per horizontal scanning month between the NTSC signal and the high-definition signal from these values, we get:
The ratio is approximately 4:5.

That is, in order to display an NTSC signal on a high-visibility display while maintaining linearity, it must be compressed approximately 415 times in the horizontal direction. A method using a line memory can be considered to compress the image by a factor of 415 in the horizontal direction. Therefore, FIG. 4 shows a general configuration of this time compression circuit.

In the figure, 1 is the NTSC signal input terminal, and 2 is the NTSC signal input terminal.
An A/D converter that receives the signal arriving at the signal input terminal 1, 3 a synchronization/timing pulse generation circuit that receives the output of the A/D converter 2, and 4 a synchronization/timing pulse generation circuit that receives the output of the A/D converter 2. IDT whose input is the output of the timing pulse generation circuit 3
V decoder, 5 is a horizontal synchronization circuit that receives the output of the synchronization/timing pulse generation circuit 3, 6 to 8 are line memories that receive the output of the IDTV decoder 4 and the output of the horizontal synchronization circuit 5, and 15 is the line memory 6. D whose input is the output of
16 is a D/A converter that receives the output of the line memory 7 as an input, 17 is a D/A converter that receives the output of the line memory 7 as an input, and 18 receives the output of the D/A converter 15. 9 is a G signal output terminal that receives the output of the D/A converter 16; 20 is the D/A converter 17;
21 is a synchronization signal output terminal that uses the output of the synchronization/timing pulse generation circuit 3 as human power.

Next, the operation will be explained.

An analog signal arriving at the NTSC signal input terminal 1 is input to an A/D converter 2 and converted into a digital signal. The output of the A/D converter 2 is input to a synchronization/timing pulse generation circuit 3 and an IDTV decoder 4. The synchronization/timing pulse generation circuit 3 generates a clock synchronized with the output signal of the A/D converter 2, and outputs the clock and various timing pulses to the IDTV decoder 4 and the horizontal synchronization circuit 5. Further, a synchronization signal is output to the synchronization signal output terminal 21. The IDTV decoder 4 digitally processes the output of the A/D converter 2, separates the luminance signal and chrominance signal, and performs sequential scan conversion, and has a frame frequency of 59.94 (Hz).
A sequentially scanned RCB signal with 525 scanning lines is output to the line memory 6.7.8. (2) Digital processing of the DTV decoder 4 is controlled by the output of the synchronization/timing pulse generation circuit 3. (2) The RGB outputs of the DTV decoder 4 are time-compressed by the line memories 6, 7, and 8, respectively. At this time, the line memories 6.7.8 are controlled by the output of the horizontal synchronization circuit 5.

Next, the configuration of the horizontal synchronization circuit 5 is shown in FIG.

The clock (WCK) output from the synchronization/timing pulse generation circuit 3 is horizontally synchronized at the same frequency as the transmission rate of the output data of the rDTV decoder 4. Horizontal counter 22 counts WCK. Further, the horizontal counter 26 counts the clock (RCK) output from the voltage control generator (VCO) 25. The number of samples for one horizontal scanning period is set in advance in the horizontal counters 22 and 26, and the set value of the horizontal counter 22 is 415 times the set value of the horizontal counter 26. The outputs of the horizontal counters 22 and 26 are input to a phase comparator 23, and their phases are compared every horizontal scanning period.The output of the 0-phase comparator 23 is integrated by a loop filter 24 and becomes a control voltage for a voltage controlled oscillator 25. . When the loop of the horizontal synchronization circuit 5 is stabilized, a clock horizontally synchronized with the output of the voltage controlled oscillator 25 and having a frequency 5/4 times that of the clock of the horizontal counter 22 is obtained. Therefore, WCK is used as the write clock for the line memory 6.7.8, and a reset pulse (WRT) obtained from the horizontal counter 22 is used for resetting. Similarly, RCK is used as the read clock for the line memory 6.7.8, and a reset pulse (RRT) obtained from the horizontal counter 26 is used for resetting. In addition, in order to determine the horizontal position when the power is turned on, the horizontal timing pulse (HD
) to reset. Therefore, the read clock RCK of the line memory 6.1.8 is horizontally synchronized with the write clock WCK, and since RCK has a frequency 5/4 times that of WCK, the output of the IDTV decoder 4 is 475 in the horizontal direction.
Time is compressed twice. The outputs of the line memories 6.7.8 are input to D/A converters 15-18 and converted into analog signals. The output of the D/A converter 15 is input to the R signal output terminal 18, the output of the D/A converter 16 is input to the G signal output terminal 19, and the output of the D/A converter 17 is input to the B signal output terminal 20. is input.

[Problems to be Solved by the Invention] Since the conventional time compression circuit is configured as described above, there is a problem in that a portion where a signal is missing appears on the screen of a high-definition display, causing burn-in on the cathode ray tube.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a time compression circuit that can eliminate missing portions of signals and prevent burn-in on a cathode ray tube.

[Means to solve the problem]

The time compression circuit according to the present invention is an A/D converter that converts an NTSC decoded television signal into a digital signal.
A converter, a synchronization/timing pulse generation circuit that generates clocks and timing pulses from the output signal of the A/D converter, and output signals from the output signal of the A/D converter and the output signal of the synchronization/timing pulse generation circuit. an IDTV decoder that outputs a digital progressive scanning RCAB signal;
In a receiver for displaying on a high-definition display, the receiver is equipped with a character decoder that reproduces and outputs character information of teletext broadcasting from the output signal of the /D converter and the output signal of the synchronization/timing pulse generation circuit, and displays the character information on a high-definition display.
three line memories that use the GB output signal as an input signal;
A buffer memory that receives the output signal of the character decoder as an input signal, a memory control circuit, three selectors that switch between the output signals of the line memory and the buffer memory, and an output signal of the timing pulse generation circuit for one horizontal scanning period. A first horizontal counter that counts and is reset every horizontal scanning period, a phase comparator, a loop filter and a voltage controlled oscillator, and a second horizontal counter that counts the output signal of the voltage controlled oscillator for one horizontal scanning period. It outputs a control signal to the three line memories to compress the time of the RGB signal by 415 times in the horizontal direction, and outputs the output of the three line memories to the three selectors and memory control circuits for planking. and a horizontal synchronization circuit that outputs a control signal that causes the output signal of the buffer memory to be output at times.

[Effect]

In this invention, when the output of the line memory is blanking, the line memory is switched to the buffer memory based on the control signal of the horizontal synchronization circuit, and characters are added to the missing portion of the signal caused by time-compressing the video signal. Since the information signal is inserted, burn-in of the cathode ray tube is prevented.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a time compression circuit according to an embodiment of the present invention. /D converter, 3 is A /'D converter 2
A synchronization/timing pulse generation circuit whose input is the output of
4 is an IDTV decoder that receives the outputs of the A/D converter 2 and the synchronization/timing pulse generation circuit 3, and 5 is a synchronization/timing pulse generation circuit 3.
6 to 8 are line memories that receive the outputs of the IDTV decoder 4 and the horizontal synchronization circuit 5 as inputs; 9 is a synchronization circuit that receives the output of the A/D converter 2; A character decoder that receives the output of the timing pulse generation circuit 3 as an input; 10 a memory control circuit that receives the output of the horizontal synchronization circuit 5; 11 a buffer memory that receives the outputs of the character decoder 9 and the memory control circuit 10; 12 13 is a selector that inputs the outputs of horizontal synchronous circuit 5, line memory 6, and buffer memory 11; 14 is horizontal synchronous circuit 5; and 14 is horizontal synchronous circuit 5. 15 is a D/A converter that receives the output of selector 12 as input; 16 is a D/A converter that receives the output of selector 13; 17 is a selector 18 is an R signal input terminal that receives the output of D/A converter 15, and 19 is a G signal input terminal that receives the output of D/A converter 16. , 20 is a B signal input terminal which inputs the output of the D/A converter 17, and 21 is a 5YNC signal output terminal which inputs the output of the synchronization/timing pulse generation circuit 3.

Next, the operation will be explained.

An analog signal arriving at the NTSC signal input terminal 1 is input to an A/D converter 2 and converted into a digital signal. The output of the A/D converter 2 is input to a synchronization/timing pulse generation circuit 3, an IDTV decoder 4, and a character decoder 9. The synchronization/timing pulse generation circuit 3 generates a clock synchronized with the output signal of the A/D converter 2, and outputs the clock and various timing pulses to the IDTV decoder 4, character decoder 9, and horizontal synchronization circuit 5. Additionally, a synchronizing signal is output to the 5YNC signal output terminal 21.

The IDTV decoder 4 digitally processes the output of the A/D converter 2, performs luminance signal color signal layer separation, and progressive scan conversion.
Frame frequency 59.94 (Hz), number of scanning lines 525
This outputs the sequentially scanned RGB signals to the line memory 6.7.8. The digital processing of the fDT■ decoder 4 is controlled by the output of the synchronization/timing pulse generation circuit 3. Line memory 6.7.8 is R of the output of IDTV decoder 4.
The GB signal is time-compressed horizontally by a factor of 415 through digital processing. At this time, the line memory 6°7.8 is controlled by the output of the horizontal synchronization circuit 5. The configuration of the horizontal synchronization circuit 5 is shown in FIG. Control of the line memory 6.7.8 is similar to the conventional example.

Further, the output of the A/D converter 2 is input to a character decoder 9, and the character information of the teletext broadcast is reproduced.

The digital processing of the character decoder 9 is controlled by the output of the synchronization/timing pulse generation circuit 3. The output of the character decoder 9 is input to a buffer memory 11. Selector 12
, 13.14 switch between the output of the line memory 6.7.8 and the output of the buffer memory 11. At this time, the buffer memory 11 is controlled by the output of the memory control circuit IO,
Memory control circuit 10. The selectors 12, 13, and 14 are controlled by the output (SEL) of the horizontal synchronization circuit 5. Selector 1
The outputs 2 to 14 are switched so that the output of the buffer memory 11 is output only when the outputs of the line memories 6 to 8 are at the blanking level, and the display screen changes to the state shown in FIG. 3(a), (b), or The display is controlled to be as shown in (C). In FIG. 5, the shaded area indicates the display area of character information. Further, the content of character information is controlled by the output of the memory control circuit 10;
The output of 14 is converted into an analog quantity by D/A converters 15-17.

The R signal output from the selector 12 is connected to the R signal output terminal 1.
8 is output. The G signal output from the selector 13 is output to the G signal output terminal 19.

The B signal output from the selector 14 is sent to the B signal output terminal 2.
Output to 0.

According to the above-mentioned embodiment, the output of the buffer memory into which character information is input is output only when the output of the line memory is at the blanking level, thereby eliminating signal loss caused by time-compressing the video signal. Since the structure is configured so that a character information signal is inserted into the exposed portion, it is possible to prevent burn-in of the cathode ray tube.

〔Effect of the invention〕

As described above, according to the present invention, since the text information signal is inserted into the portion where the signal is missing due to time compression of the video signal, it is possible to prevent burn-in on the cathode ray tube. be.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a time compression circuit according to an embodiment of the present invention, Fig. 2 is a diagram showing the configuration of a horizontal synchronization circuit of the time compression circuit of Fig. 1, and Fig. 3 shows display on a high-definition display. 4 is a block diagram of a conventional time compression circuit, and FIG. 5 is a diagram showing the configuration of a conventional horizontal synchronization circuit. In the figure, 1 is an NTSC signal input terminal, 2 is an A/D converter, 3 is a synchronization/timing pulse generator, and 4 is an IDT.
V decoder, 5 horizontal synchronization circuit, 6.7.8 line memory, 9 character decoder, 10 memory control circuit, 11
is buffer memory, 12.13.14 is selector, 15
, 16.17 is the D/A converter, 1st is the R signal output terminal,
19 is a G signal output terminal, 20 is a B signal output terminal, 21 is a 5YNC signal output terminal, 22 is a horizontal counter, 23 is a phase comparator, 24 is a loop filter, 25 is a voltage controlled oscillator, and 26 is a horizontal counter. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) An A/D converter that converts a decoded NTSC television signal into a digital signal, and a synchronization/timing pulse generation circuit that generates clocks and timing pulses from the output signal of the A/D converter. , an IDTV decoder that outputs a digital sequentially scanned RGB signal from the output signal of the A/D converter and the output signal of the synchronization/timing pulse generation circuit; A receiver for displaying a reproduced image of the NTSC television signal on a high-definition display, comprising a character decoder that reproduces and outputs character information of a teletext broadcast from an output signal of a timing pulse generation circuit, the IDTV decoder as described above; three line memories whose input signals are the RGB output signals of the character decoder; a buffer memory whose input signals are the output signals of the character decoder; a memory control circuit that controls the buffer memories; and outputs of the line memories and the buffer memory. The three selectors that switch signals and the output of the synchronization/timing pulse generation circuit described above are input, and the R of the IDTV decoder is stored in the three line memories described above.
A control signal that compresses the time of the GB signal by 4/5 times in the horizontal direction is output, and the output of the buffer memory is output to the three selectors and memory control circuits when the outputs of the three line memories are blanking. a horizontal synchronization circuit that outputs a control signal for outputting a signal, and the horizontal synchronization circuit is configured to count the output signal of the synchronization/timing pulse generation circuit for one horizontal scanning period, and to reset it every horizontal scanning period. a phase comparator that receives the outputs of the first horizontal counter and a second horizontal counter (described later); a loop filter that integrates the output of the phase comparator; and a loop filter that integrates the output of the phase comparator. 1. A time compression circuit comprising: a voltage controlled oscillator that receives the output of a filter; and a second horizontal counter that counts the output signal of the voltage controlled oscillator for one horizontal scanning period.