JPH10105702A - Density histogram calculation device for multi-gradation image - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly calculate a density histogram by avoiding the reduction of the processing speed due to the occurrence of unnecessary access of frequency 0. SOLUTION: Each time gradation data is inputted, coincidence discrimination is performed in each of modules gradation data was latched in the past, and the frequency is counted up in a module where data coincides, and new gradation data is latched in a new module if data doesn't coincide in any module where gradation data was not latched in the past. After frequencies of all gradation data are counted, gradation data and frequencies are read out in order from the gradation and frequency module #1 and are stored in a gradation and frequency memory 20, and the processing is terminated with a module whose frequency is 0. Thus, the reduction of the processing speed due to the occurrence of unnecessagry access of frequency 0 is avoided to quickly transfer histogram data to the processing in the succeeding stage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for calculating a density histogram of a multi-tone image at a high speed by a hardware circuit.

[0002]

2. Description of the Related Art Conventionally, in order to calculate a density histogram from a multi-tone image, software processing by a computer is often used. In this software processing,
Generally, a procedure of reading density data (gradation data) from an image memory storing multi-gradation image data and adding 1 to a memory storing a frequency corresponding to the read density data is repeated. .

In this case, in order to cope with a multi-tone image signal having a wide sample area, it is necessary to reserve memory areas for the number of tones × the number of samples. In software processing, these memory areas are required. It takes an enormous amount of processing time since the processing is performed sequentially, and it is difficult to obtain a histogram in real time.

To cope with this, Japanese Patent Application Laid-Open No. 61-1537 discloses
Japanese Patent Application Laid-Open No. 71-71709 provides a gate circuit of a number corresponding to each density value of a gradation signal and a counter for counting the frequency of each density value based on the output of each gate circuit, so that the density histogram of an image signal can be processed at high speed. The technology required in the above is disclosed.

[0005]

However, in the above-mentioned prior art, in order to obtain a histogram, it is necessary to read the values of all counters. Access often occurs. For example, even if the number of samples is 10 in an 8-bit 256-gradation image, all 256 counter circuits must be read out, and a large number of data having a frequency of 0 exists randomly in them.

Therefore, even if the circuit for calculating the histogram operates at high speed, it takes time to transfer the calculated histogram data to the subsequent processing, and the throughput of the entire system may be reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and eliminates a reduction in processing speed due to the occurrence of useless accesses having a frequency of 0, and calculates a density histogram of a multi-tone image capable of calculating a density histogram at a high speed. It is intended to provide a device.

[0008]

According to the first aspect of the present invention,
A circuit for holding each gradation data of the multi-gradation image signal, a circuit for judging whether the newly inputted gradation data matches the held gradation data, and a circuit for judging the coincidence judgment signal from this circuit. A plurality of circuit modules each including a circuit for integrating the frequency of the held gradation data are connected in parallel.

According to a second aspect of the present invention, in the first aspect, the circuit modules are connected in parallel by a larger one of the number of samples and the number of tones in the multi-tone image. Features.

According to a third aspect of the present invention, in the first aspect of the present invention, the multi-tone image is obtained by dividing the image into a plurality of small regions with respect to a set of images of a subject taken from different positions. A distance distribution image in which the amount of shift in small area units is obtained by stereo matching, the frequency of valid data in the small area is obtained, and this frequency and tone data in which the amount of shift in the small area unit is used as a representative tone is calculated. A pre-processing circuit for outputting to the circuit module is provided.

[0011] The invention according to claim 4 is the invention according to claims 1, 2, 3
In the invention according to any one of the above, further, the gradation data is sequentially held in the plurality of circuit modules,
At that time, a control circuit for holding the input gradation data at that time in the next circuit module only when a data mismatch determination signal is output from all the circuit modules that previously held the gradation data was provided. It is characterized by.

That is, according to the first aspect of the present invention, a plurality of circuit modules are connected in parallel, each of the circuit modules holds gradation data, and newly inputted gradation data and the held gradation data. Is determined, and if the data match, the density histogram is calculated at high speed by integrating the frequencies of the held gradation data.

In this case, according to the second aspect of the present invention, the circuit modules are connected in parallel by a larger one of the number of samples and the number of tones in the multi-tone image. According to the present invention, when the multi-tone image is a distance distribution image in which a shift amount of each small area is obtained by stereo matching, a pre-processing circuit is provided for the circuit module, and the pre-processing circuit causes the effective data in the small area to be provided. And outputs to the circuit module the frequency and tone data having the shift amount in the small area unit as a representative tone. Also, when holding gradation data in a plurality of circuit modules,
As described in claim 4, only when a data mismatch judgment signal is output from all the circuit modules that previously held the gradation data, the input gradation data at that time is held in the next circuit module. It is desirable to provide a control circuit.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 5 show a first embodiment of the present invention.
1 is an overall configuration diagram of a histogram calculation device, FIG. 2 is a circuit block diagram of a self-addition type tone / frequency module, and FIG. 3 is an explanatory diagram of distance data obtained by comparing a basic image and a comparison image. 4 is an explanatory diagram showing an area setting for calculating a histogram, and FIG. 5 is a time chart showing a process for each module.

In FIG. 1, reference numeral 10 denotes a histogram calculation device for processing a multi-tone image data to calculate a density histogram. The histogram data including the tone data and its frequency data is stored in a tone / frequency memory. 20.

In the present embodiment, the input data to the histogram calculator 10 is a set of CCD cameras 1a,
1b is a distance image obtained by processing the stereo image pair picked up by the CCD camera 1b.
A pair of analog images taken at 1b are respectively represented by A /
The digital images are converted into digital images of a predetermined luminance gradation (for example, 256 gray scales) by the D converters 2a and 2b and stored in the image memories 3a and 3b, and the basic image and the comparative image of these image memories 3a and 3b are stored. Generated by stereo matching.

The stereo matching of the basic image and the comparison image is performed by the distance data calculation circuit 4. The distance data calculation circuit 4 is provided with the image memories 3a and 3b.
City block distance calculation for searching for a portion where the same object is shown for each micro area for the basic image and the comparison image stored in, and calculating the city block distance for evaluating the degree of coincidence of the corresponding position Unit, a minimum / maximum value detection unit for detecting the minimum value and the maximum value of the city block distance,
The minimum / maximum value detection unit is configured to include a shift amount determining unit that checks whether or not the minimum value obtained by each of the small regions in the basic image and the comparison image indicates the coincidence of the small regions and determines the shift amount. , The distance distribution data output from the shift amount determining unit is stored in the distance data memory 5 as a distance image.

That is, assuming that the upper left of the screen is the origin, the horizontal direction of the image is the i coordinate axis, the vertical direction is the j coordinate axis, and the unit is pixels, as shown in FIG.
The image is divided into small regions of pixels, and for each small region of each image, a city block distance Z based on the difference between the i, j-th luminance Ai, j of the basic image and the i, j-th luminance Bi, j of the comparison image. (= Σ | A
i, j−Bi, j |: i, j = 0 to 3) is determined to be the minimum position, that is, the corresponding position, and the deviation amount of the corresponding position (the deviation amount when the city block distance is the minimum value; FIG. 4) Is 2
0H) is stored in the distance data memory 5 as distance distribution data.

The detailed configuration and operation of the circuit for calculating the city block distance and generating the distance image are described in detail in Japanese Patent Application Laid-Open No. H5-114099 filed by the present applicant.
Issue.

On the other hand, the histogram calculation device 10
It is composed of n self-addition type gradation / frequency modules 11 # 1 to #n connected in parallel, and a control circuit 12 for controlling the operation of each gradation / frequency module 11, and the number of samples and the number of gradations in the input image. As many gradation / frequency modules 11 as the number corresponding to the larger of the two are used.

Each tone / frequency module 11
As shown in FIG. 2, the circuit comprises a gradation latch 13, a match detection circuit 14 using a comparator, an OR circuit 15, and a frequency counter 16. D input terminal of the above-mentioned gradation latch 13, CK
To the terminal, the EN terminal, and the SET terminal, gray scale data from the distance data memory 5, a synchronous clock, a load signal (latch enable signal) from the control circuit 12, and a clear signal for initializing the device are input, respectively. The gradation data from the distance data memory 5 and the latch data from the Q terminal of the gradation latch 13 are input to each input terminal of the coincidence detection circuit 14.

The CK terminal of the frequency counter 16
The synchronous clock, the output of the OR circuit 15, and the clear signal from the control circuit 12 are input to the EN terminal and the CL terminal, respectively. The OR circuit 15 receives a match determination signal from the match detection circuit 14 and
The load signal from the control circuit 12 is inverted and input.
Then, the coincidence determination signal of the coincidence detection circuit 14 is input to the control circuit 12, the gradation data is output from the Q terminal of the gradation latch 13, and the frequency counter 1
Frequency data is output from the Q terminal 6 and stored in the gradation / frequency memory 20.

The calculation of the density histogram by the histogram calculator 10 is performed as shown in FIG. 4 by dividing the distance image into, for example, an area of 12 × 6 pixels and for each area. Each piece of data in each area is provided to the gradation / frequency module 11, and the frequency is counted. Less than,
The operation of the histogram calculation device 10 will be described.

First, initialization is performed when calculating a histogram. In this initialization, the grayscale
Control circuit 1 for designating number of frequency module 11
The module number counter in 2 is set to 0, and the frequency counters 16 in all the tone / frequency modules 11 are set to 0 by the clear signal, and the tone latch 13 is set to the initial value. The initial value of the gradation latch 13 is, for example, 100H data when the maximum value of the input gradation data is FFH (256 gradations).

When the first gradation data is input after the initialization, the module number counter in the control circuit 12 is set to 1, and the # 1 gradation / frequency module 11 # 1 (hereinafter referred to as the module number) The load signal is output to the gradation latch 13 # 1 within the subscripts # 1 to #n) and
A load signal is output to the frequency counter 16 # 1 via the R circuit 15 # 1. As a result, the grayscale latch 13 # 1 is enabled and the first grayscale data is written and latched by the synchronous clock, and the frequency counter 16 # 1 is enabled and the frequency counter 16 # 1 is enabled by the synchronous clock.
The count value is set to 1 by adding 1 to # 1.

Next, when the second gradation data is input to the gradation / frequency module 11 # 1, the gradation / frequency module 11 # 1 latches the first gradation data latched by the internal gradation latch 13 # 1. Match detection circuit 1 for the gradation data and the second gradation data
The comparison is performed at 4 # 1, and a match determination signal is output to the OR circuit 15 # 1 and the control circuit 12. This match determination signal is a signal of 1 when the data matches, and a signal of 0 when the data does not match.
When the output of the coincidence detection circuit 14 # 1 is 1, that is, when the first gradation data matches the second gradation data,
The frequency counter 16 # 1 is enabled via the OR circuit 15 # 1, and 1 is added by the synchronous clock, and the count value becomes 2.

On the other hand, when the output of the coincidence detection circuit 14 # 1 is 0, that is, when the first gradation data does not match the second gradation data, the frequency counter 16 # is output via the OR circuit 15 # 1. While 1 remains disabled, the count value of the frequency counter 16 # 1 is maintained at 1, while the control circuit 12 sets the internal module number counter to 2,
The load signal is output to the # 2 gradation / frequency module 11 # 2. As a result, the grayscale latch 13 # 2 and the frequency counter 16 # 2 of the grayscale / frequency module 11 # 2 are enabled, and the second grayscale data is written into the grayscale latch 13 # 2 by the synchronous clock, and the frequency counter 16 # 2 is set to 1.

Thereafter, the third gradation data is # 1, # 2
Are input to the respective tone / frequency modules 11 # 1 and # 2, and as described above, in each of the coincidence detection circuits 14 # 1 and # 2,
Each data is compared with the latched gradation data. That is, in the gradation / frequency module 11 # 1 of # 1, the first gradation data latched by the gradation latch 13 # 1 and the third gradation data inputted this time are determined by the coincidence detection circuit 14 # 1. Then, in the gradation / frequency module 11 # 2 of # 2, the second gradation data latched by the gradation latch 13 # 2 and the third gradation data inputted this time match each other. Compared by two.

When the third gradation data coincides with the first gradation data, 1 is added to the frequency counter 16 # 1 inside the # 1 gradation / frequency module 11 # 1, and the third When the gradation data of # 1 coincides with the second gradation data, the frequency counter 16 # 1 inside the gradation / frequency module 11 # 1 of # 1 is not counted up, and
Frequency counter 16 inside gradation / frequency module 11 # 2
1 is added to # 2 and counted up.

When the third gradation data does not match with either the first gradation data or the second gradation data, the frequency counter 16 # 1 inside the # 1 gradation / frequency module 11 # 1 And # 2 gradation / frequency module 1
None of the frequency counter 16 # 2 inside 1 # 2 is counted up, and the module number counter inside the control circuit 12 becomes 3, and a load signal is output to the # 3 gradation / frequency module 11 # 3. Then, the gradation latch 13 # 3 and the frequency counter 1 inside the # 3 gradation / frequency module 11 # 3
6 # 3 is enabled, the third gradation data is written into the gradation latch 13 # 3, and the frequency counter 16 # 3
Is added to 1 to make the count value 1.

That is, as shown in the time chart of FIG. 5, each time gray-scale data is input, a coincidence determination is made in each module whose gray-scale data has been latched in the past.
The frequency is increased only in the module that matched the data,
The match determination signals from each module are all 0, that is,
Only when the data does not match in any module in which the gradation data has been latched in the past, the module number counter in the control circuit 12 is counted up and the load signal is output to the new module, and the new gradation data is transferred to the new module. Latched. By repeating such a process, all types of gradation data of the input image are latched one after another, and the frequency is counted.

As described above, when the frequencies of all the gradation data in the 12 × 6 area are counted, the gradation data and the frequencies are sequentially read out from the gradation / frequency module 11 # 1 of # 1, and the gradation / frequency memory 20 is read out. Then, the processing is terminated by the module having the frequency of 0 and the gradation data kept at the initial value.
Then, after re-initialization by the clear signal, the processing shifts to processing of the next 12 × 6 area.

That is, in the process of sequentially reading out the gradation data and the frequency from the # 1 module, there is no module having the frequency 0 between the modules having the frequency, and when the module having the frequency 0 appears, the histogram data It is the end. As a result, it is possible to avoid a reduction in processing speed due to the occurrence of useless access with a frequency of 0, and to transfer the histogram data at a high speed to subsequent processing, thereby improving the throughput of the entire system and realizing image processing in real time. it can.

6 to 10 relate to a second embodiment of the present invention. FIG. 6 is a diagram showing the overall configuration of a histogram calculating device, FIG. 7 is a circuit block diagram of a self-addition type gradation / frequency module, and FIG. FIG. 9 is an explanatory diagram of frequency calculation using a bit pattern, FIG. 9 is an explanatory diagram showing data masking using a mask pattern, and FIG. 10 is a time chart showing processing for each module.

In the present embodiment, as in the case of stereo image processing, the shift amount (gradation data) in small areas (for example, 4 × 4 pixels) is used.
Is calculated as an average value (representative gradation data) of the entire small area and used as distance data, that is, when the same gradation data is always obtained in a fixed small area such as a distance image, In order to improve the processing speed, a pre-processing circuit for processing the data in advance is provided.

That is, for each 4 × 4 pixel small area of the basic image stored in the image memory 3a,
The distance distribution data is obtained by calculating the city block distance from the comparison image stored in b. In parallel with this processing, the effective distance distribution data calculation in the 4 × 4 pixel small area of the basic image is performed. The frequency of the data is calculated in advance, and the representative grayscale data (the amount of displacement when the city block distance is the minimum value) and the frequency for each of the small areas of 4 × 4 pixels and the frequency are used as input data. A similar histogram calculation process is performed.

For this reason, in the histogram calculation apparatus 10A of this embodiment, as shown in FIG.
#N n self-addition type gradation / frequency modules 31 and a control circuit 3 for controlling the operation of each gradation / frequency module 31
2, a bit pattern generation circuit 33, a mask pattern generation circuit 34, an AND circuit 35,
A bit adder 36 is provided. Note that the number of the tone / frequency modules 31 is a number corresponding to the larger one of the number of samples and the number of tones in the input image, as in the first embodiment.

The distance data calculation circuit 4 calculates 4 ×
The displacement amount when the city block distance, which is the representative gradation of the small area of 4 pixels, is the minimum value, and the bit pattern of the effective data calculated by the bit pattern generation circuit 33 based on the basic image data in the image memory 3a are the distances. The gradation data stored in the data memory 5 is input to the gradation / frequency module 31 from the distance data memory 5, and the bit pattern data of the distance data memory 5 and the data from the mask pattern generation circuit 34 described later are stored. AND by the AND circuit 35 is input to the gradation / frequency module 31 via the bit adder 36 as frequency data.

Further, the gradation / frequency module 31
As shown in FIG. 7, the frequency counter 1 is provided for the gradation latch 13, the coincidence detection circuit 14, and the OR circuit 15 similar to those of the first embodiment.
6, a frequency latch 17 is employed.
8 is provided.

The D input terminal, the CK terminal, the EN terminal, and the SET terminal of the gradation latch 13 have gradation data from the distance data memory 5, a synchronization clock, a load signal from the control circuit 32, and a device, respectively. , And the input terminal of the coincidence detection circuit 14 receives the gradation data from the distance data memory 5 and the latch data from the Q terminal of the gradation latch 13. .

A value obtained by adding the frequency data from the bit adder 36 and the latch data from the Q terminal of the frequency latch 17 by the adder 18 is input to the D input terminal of the frequency latch 17. , The frequency latch 1
7, a CK terminal, an EN terminal, and a CL terminal respectively have a synchronous clock, the output of the OR circuit 15, and the control circuit 3
2 is input. The OR circuit 15 receives the match determination signal from the match detection circuit 14 and receives the inverted load signal from the control circuit 32. Then, the coincidence determination signal of the coincidence detection circuit 14 is input to the control circuit 32, the gradation data is output from the Q terminal of the gradation latch 13, and the frequency data is output from the Q terminal of the frequency latch 17. Are stored in the gradation / frequency memory 20.

In the histogram calculating apparatus 10A according to the present embodiment having the above-described configuration, similar to the above-described first embodiment, the histogram calculating process is performed using an area of 12 × 6 pixels as one evaluation unit, but one 12 × 6 pixel area is used. 4x for the area
A small area of 4 pixels is treated as a whole, and the representative gradation data of this small area (the amount of displacement when the city block distance is the minimum value) and the frequency of the effective data calculated in the pre-processing are represented by gradation /
The process of inputting to the frequency module 31 is performed six times while shifting in the j direction and the i direction.

As shown in FIG. 8, the frequency calculation of the pre-processing for the small area of 4 × 4 pixels is performed for 16 data of the small area of 4 × 4 pixels in the basic image stored in the image memory 3a. For example, the bit pattern generation circuit 33 generates a bit pattern of 1 (valid bit) when the difference in luminance between adjacent pixels is larger than a predetermined threshold, and generates a bit pattern of 0 when the difference is smaller than the threshold.

FIG. 8 shows an example in which a bit pattern (2 byte data of EC8OH) of 1110, 1100, 1000, 0000 is formed for a small area of 4 × 4 pixels of the basic image, and corresponds to one small area. In the 4-byte area of the distance data memory 5, the shift amount when the city block distance is the minimum value and the bit pattern data are stored. That is, the deviation amount when the city block distance calculated by the distance data calculation circuit 4 is the minimum value is stored in the first one-byte area, and the bit pattern data by the bit pattern generation circuit 33 is stored in the next two-byte area. Is stored. The last one-byte area is a spare empty area. As a result, 16-byte data in a small area of 4 × 4 pixels of the distance image can be compressed to 4-byte (substantially 3 bytes) data.

In this case, as shown in FIG. 9, the pre-processing is performed while shifting the small area of 4 × 4 pixels in the area of 12 × 6 pixels in the j direction and the i direction. In such a case, a part of the small area of 4 × 4 pixels is protruded from the area of 12 × 6 pixels, and the data stored in the distance data memory 5 includes data outside the area of 12 × 6 pixels. become.

Therefore, data outside the area of 12 × 6 pixels is masked by the mask pattern generated by the mask pattern generation circuit 34. That is, since the portion to be masked outside the 12 × 6 pixel region is the lower half 4 × 2 region of the 4 × 4 pixel small region, the mask pattern generation circuit 34 performs the operation as shown in FIG. , 0,000,000
A mask pattern of 0, 1111, 1111 (= 00FFH) is generated. Then, the AND of each bit of the mask pattern and the bit pattern data is calculated by an AND circuit 35.
By outputting the data as byte data (frequency data) having an effective number of bits to the grayscale / frequency module 31 # 1 of # 1 by the bit adder 36, the data outside the area of 12 × 6 pixels can be masked. it can.

The bit pattern data to be masked is data obtained from the second, fourth and sixth small areas when the small area of 4 × 4 pixels is shifted within the area of 12 × 6 pixels. For the data (1, 3rd, 5th), the bit pattern generated by the mask pattern generation circuit 34 is 1111, 1111, 1111, 1111 (=
FFFFH) and the data is not masked.

Next, a description will be given of the histogram calculation processing of the present embodiment involving the above preprocessing. First, in the same manner as in the first embodiment, the module number counter in the control circuit 32 is set to 0 by the clear signal, the frequency latches 17 in all the gradation / frequency modules 31 are set to 0, and 13 is the initial value (the maximum value of the input gradation data is FF
In the case of H, it is set to 100H). And 4 of the basic image
The distance when the city block distance calculated by the distance data calculation circuit 4 using the comparison image is the minimum value and the bit pattern data by the bit pattern generation circuit 33 are stored in the distance data memory 5 for the small area of × 4 pixels. Is stored in

Next, the module number counter in the control circuit 32 is counted up to 1 and the load signal is supplied to the gradation latch 13 # 1 and the frequency latch 17 # 1 in the # 1 gradation / frequency module 31 # 1. The signal is output and the internal gradation latch 13 # 1 and frequency latch 17 # 1 are enabled. Then, the grayscale data of the first small area is written into the grayscale latch 13 # 1 and the frequency data after the preprocessing is written into the frequency latch 17 # 1 by the synchronous clock.

As described above, since it is not necessary to mask the bit pattern data for the first small area, the data generated by the mask pattern generation circuit 34 is FFFFH, and the AND circuit 35,
The gradation / frequency module 31 # 1 via the bit adder 36
Is the same as the number of effective bits of the bit pattern data in the distance data memory 5.

Next, the small area of 4 × 4 pixels is shifted in the j direction within the area of 12 × 6 pixels, and a part of the small area is shifted by 12 × 6 pixels.
In the state of being out of the area of 6 pixels, the bit pattern of the data is obtained again by the processing by the bit pattern generation circuit 33, and the bit pattern data is calculated when the city block distance calculated by the distance data calculation circuit 4 is the minimum value. The distance data is stored in the distance data memory 5 together with the deviation amount.

Then, the gradation data of the second small area is output from the distance data memory 5 to the # 1 gradation module 31 # 1, and the bit pattern data of the second small area is output to the AND circuit 35. I do. This AND circuit 35
Contains the 00FF generated by the mask pattern generation circuit 34.
The mask data of H is input, and the data outside the area of 12 × 6 pixels included in the bit pattern data is masked by a logical AND for each bit with the bit pattern data of the second small area. Is output to the # 1 gradation / frequency module 31 # 1 as frequency data of valid bits after pre-processing via the.

In the # 1 gradation / frequency module 31 # 1,
The gradation data of the first small area latched by the gradation latch 13 # 1 is compared with the gradation data of the second small area inputted this time by the coincidence detection circuit 14 # 1, and the coincidence determination signal is output to the OR circuit 1
5 # 1 and output to the control circuit 32.

When the coincidence determination output of the coincidence detecting circuit 14 # 1 is 1, that is, when the gradation data of the latched first small region matches the gradation data of the second small region inputted this time. , The frequency latch 17 # 1 is enabled via the OR circuit 15 # 1, and the frequency data latched by the frequency latch 17 # 1 and the currently input frequency data (frequency data after masking) are added to the adder 18 #. It is added by 1 and written to the frequency latch 17 # 1.

On the other hand, when the output of the coincidence detection circuit 14 # 1 is 0, that is, the gradation data of the latched first small area does not match the gradation data of the second small area inputted this time. Occasionally, the latch data is held via the OR circuit 15 # 1 while the frequency latch 17 # 1 is in a disabled state, while the control circuit 32 sets the internal module number counter to 2, and the # 2 gradation / frequency Module 31 # 2
Output the load signal.

As a result, the grayscale latch 13 # 2 and the frequency latch 17 # 2 inside the # 2 grayscale / frequency module 31 # 2 are enabled, and the grayscale latch 13 # 2 stores the grayscale of the second small area. While data is written, the frequency latch 17
In # 1, frequency data (data after masking) of the second small area is written.

Thereafter, the small area of 4 × 4 pixels is shifted in the i direction from the initial position, and the bit pattern data is obtained by the processing by the bit pattern generation circuit 33. The calculation result of the bit pattern data in the third small area is obtained. To
The city block distance calculated by the distance data calculation circuit 4 is stored in the distance data memory 5 together with the deviation amount when the distance is the minimum value. Since the bit pattern data in the third small area need not be masked, the bit pattern data is converted into frequency data by the bit adder 36 without being masked by the data from the mask pattern generation circuit 34, At the same time, they are input to the tone / frequency modules 31 # 1 and # 2 of # 1 and # 2.

Then, the # 1 gradation / frequency module 11
In # 1, the match detection circuit 14 # 1 compares the gradation data of the first small region latched by the gradation latch 13 # 1 with the gradation data of the third small region inputted this time, In the second gradation / frequency module 11 # 2, the gradation data of the second small area latched by the gradation latch 13 # 2 matches the gradation data of the third small area inputted this time. The comparison is made by the circuit 14 # 2.

As a result, if the gradation data of the third small region matches the gradation data of the first small region, the gradation is latched by the frequency latch 17 # 1 of the # 1 gradation / frequency module 31 # 1. The frequency data of the first small area and the frequency data of the third small area input this time are added by the adder 18 # 1 and written into the frequency latch 17 # 1. When the gradation data of the third small region matches the gradation data of the second small region, the gradation data is latched by the frequency latch 17 # 2 of the # 2 gradation / frequency module 31 # 2. The frequency data of the second small area and the frequency data of the third small area input this time are added by the adder 18 # 2 and written into the frequency latch 17 # 2.

On the other hand, when the gradation data of the third small area does not match any of the gradation data of the first small area and the gradation data of the second small area, the module number counter in the control circuit 32 is set to 3 As a result, a load signal is output to the # 3 gradation / frequency module 31 # 3, and the gradation latch 13 # 3 and the frequency latch 17 # 3 inside the gradation / frequency module 31 # 3 are enabled, and the gradation is performed. The gradation data of the third small area is written into the latch 13 # 3, and the frequency data of the third small area is written into the frequency latch 17 # 3.

Thereafter, the data of the fourth small area, the fifth small area, and the sixth small area are processed in the same manner, and
When the processing for two 12 × 6 areas is completed, the gradation and frequency data are read out sequentially from the # 1 gradation / frequency module 11 # 1 and stored in the gradation / frequency memory 20, and the module having the frequency of 0 is read out. To stop the operation, re-initialize by the clear signal, and proceed to the processing of the next 12 × 6 area.

That is, as shown in the time chart of FIG. 10, the gradation data and the frequency data calculated in the preprocessing are latched as input data of each module in each module, and the inputted gradation data is stored in the past. If the data coincides with the gradation data latched in the module, the frequency data is accumulated by adding new frequency data to the frequency data latched by the module and re-latching.

On the other hand, if the data does not match in any of the modules in which the grayscale data has been latched in the past, the module number counter in the control circuit 32 is counted up and a load signal is output to the new module, and the new grayscale data is output. Repeat the process of latching the data and frequency data in the new module, all types of gradation data of the input image and frequency data after pre-processing are latched one after another,
Frequency data accumulates.

In this embodiment, it is possible not only to avoid a reduction in processing speed due to the occurrence of useless access with a frequency of 0, but also to obtain a multi-level image such as a distance image in which the same gradation data can always be obtained in a fixed small area. Since the frequency of data in the small area is counted by the preprocessing circuit for the toned image, the processing speed can be further improved.

[0065]

As described above, according to the present invention, a plurality of circuit modules are connected in parallel, the gradation data is held in each circuit module, and the newly input gradation data is held. It is determined whether or not the data matches the gradation data. If the data matches, the frequency of the held gradation data is integrated, so that the processing speed is prevented from lowering due to the useless access of frequency 0 to avoid the lower processing speed. Histogram data can be transferred to the processing at high speed, and excellent effects can be obtained, such as improving the throughput of the entire system and realizing image processing in real time.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a histogram calculation device according to a first embodiment of the present invention.

FIG. 2 is a circuit block diagram of the self-addition type gradation / frequency module.

FIG. 3 is an explanatory diagram of distance data obtained by comparing a basic image and a comparative image.

FIG. 4 is an explanatory diagram showing an area setting for calculating a histogram;

FIG. 5 is a time chart showing processing for each module;

FIG. 6 is an overall configuration diagram of a histogram calculation device according to a second embodiment of the present invention.

FIG. 7 is a circuit block diagram of the self-addition type gradation / frequency module.

FIG. 8 is an explanatory diagram of frequency calculation using a bit pattern according to the embodiment;

FIG. 9 is an explanatory view showing a data mask using a mask pattern;

FIG. 10 is a time chart showing processing for each module;

[Explanation of symbols]

10, 10A: histogram calculation device 11, 31: self-addition type gradation / frequency module (circuit module)

Claims (4)

[Claims] 1. A circuit for holding each gradation data of a multi-gradation image signal, a circuit for determining whether newly input gradation data and the held gradation data match, A multi-tone image density histogram calculating apparatus, wherein a plurality of circuit modules each including a circuit for integrating the frequency of held gradation data in accordance with the coincidence determination signal are connected in parallel. 2. The density of a multi-tone image according to claim 1, wherein the circuit modules are connected in parallel by the larger one of the number of samples and the number of tones in the multi-tone image. Histogram calculation device. 3. A distance distribution obtained by dividing the multi-tone image into a plurality of small regions with respect to a set of images obtained by photographing a subject from different positions and obtaining a shift amount in small region units by stereo matching. A preprocessing circuit that obtains the frequency of the effective data in the small area as an image, and outputs the frequency and the gradation data having the deviation amount in the small area unit as a representative gradation to the circuit module. The apparatus for calculating a density histogram of a multi-tone image according to claim 1. 4. A method of causing the plurality of circuit modules to sequentially hold grayscale data, and in this case, when a data mismatch determination signal is output from all circuit modules that previously held grayscale data. 4. A multi-gradation image density histogram calculating apparatus according to claim 1, further comprising a control circuit for holding only the input gradation data at that time in a next circuit module. .