JPH10125819A - Substrate for semiconductor device, semiconductor device, and manufacturing method thereof - Google Patents

Abstract

(57) [Problem] To provide a mounting surface having high density and thinness and high smoothness, and to improve the reliability of mounting. SOLUTION: An insulating layer 1 obtained by curing a liquid resin,
A plurality of connection electrodes 2 formed on one surface of the insulating layer and arranged to be connectable to the semiconductor chip, and a plurality of wiring regions 3 formed on one surface of the insulating layer and individually connected to each connection electrode Is formed in the other surface of the insulating layer so that the surface is not covered by the insulating layer but is recessed from the surface of the insulating layer, and the side surface is covered by the insulating layer, and can be connected to external elements A semiconductor device substrate and a semiconductor device, comprising: a plurality of land electrodes 4 arranged in the semiconductor device; and a plurality of vias 5 for individually connecting each land electrode and each wiring region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BGA (Ball Grid Array) type semiconductor device substrate on which a semiconductor chip is mounted, a semiconductor device, and a method of manufacturing the same. The present invention relates to a semiconductor device substrate, a semiconductor device, and a method of manufacturing the same, which can prevent a short circuit due to the like.

[0002]

2. Description of the Related Art Recently, portable electronic devices such as notebook personal computers, handy video devices, and mobile phones have been widely sold. For this reason, there is an increasing demand for smaller and more sophisticated semiconductor device substrates when mounting semiconductor devices in these electronic devices.

As this type of semiconductor device substrate, there is a BGA type substrate on which a semiconductor chip such as an LSI can be mounted. Specifically, for example, a substrate disclosed in Japanese Patent Application Laid-Open No. Hei 8-37345 is known. It is known. A semiconductor device that can be mounted on a motherboard or the like as an external element is manufactured by mounting a semiconductor chip on a semiconductor device substrate and sealing the resin with a resin.

FIG. 8 is a sectional view showing a configuration of a semiconductor device using the semiconductor device substrate. As this semiconductor device, a copper-clad laminate for a printed wiring board is used as a base substrate 31.
A plurality of holes 32 are formed in the base substrate 31 in a substantially matrix shape by mechanical processing using a drill.

Next, of the copper layers on both surfaces of the base substrate 31 by photolithography, the copper layer on the upper surface becomes a wiring pattern 33 and the copper layer on the other surface becomes an electrode terminal (hereinafter referred to as a land electrode) 34. Is patterned as follows.

When a pattern that cannot be formed by a single layer is provided as the wiring pattern 33 because of its high density and complexity,
It is necessary to arrange the wiring patterns 33 in multiple layers to increase the wiring density. When the wiring pattern 33 is multilayered, a conductive layer (copper layer) is similarly formed after an insulating layer 35 is formed on the surface including the lower wiring pattern 33, and the conductive layer is patterned to form a new wiring pattern 33. It is said.

At this time, in order to establish conduction between the upper and lower wiring patterns 33, a through hole 36 is formed in the insulating layer 35, and both wiring patterns 33 are conducted through the conductive layer formed in the through hole 36. At this time, the insulating layer 35
Is preferably made of a material that can be patterned by a photolithography method so that a through hole 36 can be formed in a desired portion. For example, a photosensitive resin is appropriate.

After forming the wiring pattern 33 of each layer,
Au plating is applied to the surface of the uppermost wiring pattern 33 to improve the suitability for connection (wire bonding) with the semiconductor chip 37.

[0009] As shown in FIG.
Lower surface is solder resist 3 to protect from solder etc.
8 is formed between each land electrode 34, and a conductive ball 39 made of solder or the like is formed on each land electrode.

[0010]

However, in the semiconductor device substrate described above, the base substrate 31 is drilled in order to make the wiring pattern 33 and the land electrode 34 conductive. However, in general, drilling is not suitable for fine drilling. Therefore, this type of semiconductor device substrate has no problem when applied to products of normal integration, but has a higher density. It is not suitable for applications that require high integration.

The base substrate 31 functions as a support substrate in a process of forming an insulating layer 35 coated with a photosensitive resin or the like. That is, since the base substrate 31 requires a certain degree of rigidity (thickness), as described above, there is no problem as a normal product, but it is not suitable for applications requiring further thinning. Has become.

Also, as shown in FIG.
The method of applying a solder resist 38 to the land electrode 3
There is a problem that the smoothness of the solder resist 38 other than 4 is insufficient. In this method, since the solder resist 38 is applied and cured on the uneven base substrate 31 on which the wiring patterns 33 and the land electrodes 34 are formed, the unevenness of the base substrate 31 is inherited by the upper surface of the solder resist 38. And smoothness cannot be obtained. Also, since the upper surface of the solder resist 38 having insufficient smoothness becomes the mounting surface,
Since a large amount of solder is used from the viewpoint of ensuring mounting, the adjacent conductive balls 39 and land electrodes 34 are used.
However, there is a possibility of short-circuiting due to the solder bridge. For this reason, it is required that a smooth mounting surface can be mounted with a minimum necessary amount of solder.

Further, the method of applying the solder resist 38 on the base substrate 31 has a problem that it is difficult to control the thickness of the solder resist 38. The thickness of the solder resist 38 is the amount of depression of the land electrode 34 from the surface of the solder resist 38. In order to mount using the minimum amount of solder necessary for mounting, it is necessary to appropriately control the amount of depression. I have.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances and provides a semiconductor device substrate and a semiconductor which can realize a high-density, low-profile, high-smoothness mounting surface and can improve the reliability of mounting. It is an object to provide devices and methods for their manufacture.

[0015]

According to a first aspect of the present invention, there is provided an insulating layer formed by curing a liquid resin, and a plurality of insulating layers formed on one surface of the insulating layer and arranged so as to be connectable to a semiconductor chip. And a plurality of wiring regions formed on one surface of the insulating layer and individually connected to the respective connection electrodes, and the surface is not covered with the insulating layer, and is recessed from the surface of the insulating layer. A plurality of land electrodes formed in the other surface of the insulating layer so that the side surface is covered with the insulating layer, and arranged so as to be connectable to an external element; A semiconductor device substrate including a plurality of vias that individually connect to respective wiring regions.

According to a second aspect of the present invention, there is provided a semiconductor device using the semiconductor device substrate according to the first aspect, wherein the semiconductor chip electrically connected to the connection electrodes and the land electrodes are provided. And a plurality of conductive balls individually formed on the semiconductor chip, and at least the semiconductor chip and a connection portion to each of the connection electrodes are sealed with a resin.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device substrate according to the first aspect.
A first insulating layer forming step of selectively applying and curing a liquid resin on a sheet-shaped metal material at a position different from the formation position of each of the land electrodes to form an insulating layer; And a stopper layer forming step of selectively forming a plurality of etching stopper layers serving as surfaces of the land electrodes in a portion surrounded by the insulating layer; and plating the land electrodes on the etching stopper layers by plating. Forming a land and forming a second insulating layer by applying and curing a liquid resin on each of the land electrodes and the insulating layer so as to partially expose each of the land electrodes; By the forming step and plating, each of the vias,
A semiconductor device including a wiring forming step of forming the wiring regions and the connection electrodes, an etching step of removing the metal material by etching, and a stopper layer removing step of removing at least a surface of the etching stopper layer It is a method of manufacturing a substrate for use.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the second aspect, wherein the semiconductor device is selectively formed on a sheet-like metal material at a position different from the formation position of each of the land electrodes. A first insulating layer forming step of applying and curing a liquid resin to form an insulating layer; and forming a plurality of portions that are to be surfaces of the land electrodes on the metal material and selectively in a portion surrounded by the insulating layer. A stopper layer forming step of forming an etching stopper layer, a land forming step of forming the land electrodes on the etching stopper layers by plating, and the land electrodes so as to partially expose the land electrodes. A second insulating layer forming step of applying and curing a liquid resin on the upper portion of the insulating layer and the upper portion of the insulating layer to form an insulating layer; and plating, the vias, the wiring regions and the respective A wiring forming step of forming a connection electrode, a chip connecting step of connecting a semiconductor chip to each of the connection electrodes, and a resin sealing step of resin sealing at least the semiconductor chip and a connection portion to each of the connection electrodes. A semiconductor device comprising: an etching step of removing the metal material by etching; a stopper layer removing step of removing at least a surface of the etching stopper layer; and a step of individually forming a conductive ball on each of the land electrodes. It is a manufacturing method of.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device substrate according to the first aspect.
A stopper layer forming step of selectively forming a plurality of etching stopper layers to be surfaces of the land electrodes on a sheet-like metal material and at a position where the land electrodes are formed; A land forming step of forming each land electrode, and applying and curing a liquid resin on the top of each land electrode and the top of the metal material so as to partially expose each land electrode, thereby forming an insulating layer. An insulating layer forming step, a wiring forming step of forming the vias, the wiring areas and the connection electrodes by plating, an etching step of removing the metal material by etching, and at least a surface of the etching stopper layer. And a stopper layer removing step of removing the substrate.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the second aspect, each of the land electrodes is selectively formed on a sheet-like metal material and at a position where each of the land electrodes is formed. A stopper layer forming step of forming a plurality of etching stopper layers serving as surfaces of the substrate, a land forming step of forming the land electrodes on the etching stopper layers by plating, and partially exposing the land electrodes. An insulating layer forming step of applying and curing a liquid resin on the land electrodes and the metal material to form an insulating layer; and plating, the vias, the wiring regions, and the connection electrodes. Forming a wiring, a chip connecting step of connecting a semiconductor chip to each of the connection electrodes, and connecting at least the semiconductor chip and the connection electrodes thereof. A method of manufacturing a semiconductor device, comprising: a resin sealing step of sealing a connection portion with a resin; an etching step of removing the metal material by etching; and a stopper layer removing step of removing at least a surface of the etching stopper layer. It is. (Terminology) Next, the materials applied to the present invention as described above will be supplementarily described.

The insulating layer is formed by curing a liquid resin applied by screen printing or curtain coating. As the liquid resin, an epoxy resin, a polyimide resin, an acrylic resin, or the like can be used. Further, as the liquid resin, it is preferable to use a photosensitive resin from the viewpoint of easily processing via holes and the like with high accuracy. However, even if a non-photosensitive resin is used, it can be formed into a desired shape by fine processing using an excimer laser or the like.

The insulating layer covers the side surface of the land electrode, the surface protrudes below the surface of the land electrode, and has an opening substantially the same size as the land electrode. Further, the semiconductor device substrate may have either a structure in which one semiconductor chip can be mounted or a structure in which two or more semiconductor chips can be mounted.

In the semiconductor device substrate, the printed circuit portion has a required number of layers for wiring, for example, a power supply layer,
A multilayer structure having a ground layer may be used. The etching stopper layer serves as a stopper when the sheet-like metal material is removed by etching. For example, the metal material is copper, and a persulfate etching solution such as ammonium persulfate or potassium persulfate, or a copper ammonium complex ion is mainly used. When using an etching solution composed of an alkaline aqueous solution as a component, solder or the like is used.

It is desirable that the material of the etching stopper layer has a strong adhesion to the wiring material, is hardly corroded by an etching solution, and is desirably easily formed of a metal material. Specifically, it is appropriately selected in relation to the metal material and the etching solution.

Further, at least the surface of the etching stopper layer is removed after the etching of the metal material. For this reason, it is preferable that the material be different from the etching solution for the metal material and be a material that can be etched or removed. After removing at least the surface of the etching stopper layer, the surface protection layer may be formed of a metal such as Au or Pd with a thickness smaller than the removed thickness.

Here, when the surface of the etching stopper layer is removed, the amount of depression of the land electrode can be appropriately controlled by controlling the amount of etching. In addition, when the etching stopper layer is removed, the depth of the land electrode can be appropriately controlled by controlling the thickness of the etching stopper layer. Such a control method can be controlled with high accuracy, unlike the conventional thickness control of the solder resist. In particular, the method of completely removing the etching stopper layer is preferable because the thickness of the etching stopper layer such as the amount of plating can be controlled with high precision.

The material of the etching stopper layer is desirably a material having a high wettability with respect to a material (for example, solder) used for connecting an external element to a printed wiring board or the like. Methods for forming the etching stopper layer include plating, vapor deposition, sputtering, and the like, and can be appropriately selected.

Taking solder as an example, the solder can be easily formed by plating. If the metal material is a copper alloy, an alkaline etching solution containing copper ammonium complex ions as a main component is used. When used and etched, the copper alloy is etched and the solder layer becomes a stopper layer.

As the sheet-like metal material, for example,
Copper, copper alloy, or 42 alloy (42% by weight Ni, balance
An iron-Ni alloy represented by Fe) can be used, and a copper alloy is particularly preferable because it has excellent thermal conductivity and low electric resistance.

The thickness of the sheet-like metal material is required to be thick enough to function as a supporting substrate and not too thick so as to be easily removed by etching.
It is preferable that the distance is in the range of about 15 mm to 0.35 mm. Further, the metal material is required to have smoothness, which may be a degree of smoothness of a normal metal material.

In the via forming step, it is preferable to fill the via holes by plating from the viewpoint of preventing the formation of bubbles in the via holes. Specifically, it is possible to perform electroplating by applying a current to a metal material, and it is possible to fill the inside of the via hole with a simple process.

In the step of forming a conductor circuit composed of the wiring region and the connection electrode on the via, a conventional electrolytic Cu plating such as a subtractive method, a semi-additive method or a full-additive method can be applied. Since it has been formed, the conductor circuit can be easily formed.

As the subtractive method, for example, electroless plating or sputtering can be used. Specifically, for example, after forming a thin copper layer having a thickness of 0.2 μm, electrolytic copper plating having a thickness of 10 μm is applied to the entire surface. Is done. After a resist (eg, PMER; trade name: manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied and dried, each step of exposure, development, etching, and resist peeling is performed. Further, as the resist, a negative photosensitive resist is desirable, and for example, a resist referred to by the trade name PMER can be used. As a coating method, immersion, screen printing, spin coating, or the like can be appropriately used.

As the semi-additive method, for example, electroless plating or sputtering can be used. Specifically, for example, after forming a thin copper layer having a thickness of 0.2 μm, a resist (eg, PMER) is applied. After being dried, it is exposed and developed, and a 10 μm-thick electrolytic copper plating is applied to a wiring region and a pattern portion serving as a connection electrode. After stripping the resist, the thin copper layer is etched away.

As a fully additive method, for example, after applying a catalyst and forming a resist, a wiring region and a connection electrode are formed by electroless plating. As a method for connecting a semiconductor chip to a semiconductor device substrate, there are wire bonding, bumps, and the like. Further, the metal material is etched after at least the semiconductor chip and the connection between the semiconductor chip and the semiconductor device substrate are sealed with resin. (Operation) Therefore, in the invention corresponding to claim 1, the insulating layer is formed of a liquid resin by taking the above means, so that a drilling step by a drill can be omitted. Shape can be realized,
The mounting surface with high smoothness can be realized, and the surface of each land electrode is located at a position that is more concave than the surface of the insulating layer. When mounting the semiconductor device with the ball formed on an external element, the protruding insulating layer surface acts as a dam, so that the amount of solder for connection can be appropriately controlled, thereby improving the reliability of mounting. Can be expected.

According to a second aspect of the present invention, a semiconductor chip is connected to the semiconductor device substrate according to the first aspect, and the semiconductor chip and a connection portion thereof are resin-sealed.
Since the conductive ball is formed on each land electrode, a semiconductor device having the same operation as the first embodiment can be realized.

Further, according to a third aspect of the present invention, an insulating layer is selectively formed on a sheet-like metal material, and thereafter, an etching stopper layer serving as a surface of each land electrode is formed. A land electrode is sequentially formed, an insulating layer is formed again, each via, each wiring region and each connection electrode are formed, a metal material is removed by etching, and at least a surface of the etching stopper layer is removed. It is possible to easily and reliably manufacture a semiconductor device substrate exhibiting the same operation as the operation corresponding to 1, and to improve the stability of the manufacturing process.

Further, according to a fourth aspect of the present invention, an insulating layer is selectively formed on a sheet-like metal material, and thereafter, an etching stopper layer serving as a surface of each land electrode is formed. A land electrode is formed sequentially, an insulating layer is formed again, each via, each wiring region and each connection electrode are formed, a semiconductor chip is connected to each connection electrode, and the semiconductor chip and the like are resin-sealed, and a metal material is formed. Is removed by etching,
Since at least the surface of the etching stopper layer is removed, it is possible to easily and reliably manufacture a semiconductor device having the same effect as that of the second aspect, and to improve the stability of the manufacturing process.

According to a fifth aspect of the present invention, an etching stopper layer and each land electrode are selectively formed on a sheet-shaped metal material, and thereafter, an insulating layer is sequentially formed, and each via is formed. Since each wiring region and each connection electrode are formed, the metal material is removed by etching, and at least the surface of the etching stopper layer is removed, a semiconductor device substrate having the same function as that of claim 1 can be easily and easily provided. It can be reliably manufactured, the stability of the manufacturing process can be improved, and when forming the etching stopper layer selectively, a higher-density and finer pattern is formed by using a high-resolution resist. can do.

According to a sixth aspect of the present invention, an etching stopper layer and each land electrode are selectively formed on a sheet-like metal material, and thereafter, an insulating layer is sequentially formed to form each via, Since each wiring region and each connection electrode are formed, a semiconductor chip is connected to each connection electrode, the semiconductor chip and the like are sealed with a resin, a metal material is removed by etching, and at least a surface of the etching stopper layer is removed. A semiconductor device having the same function as the function corresponding to Item 2 can be easily and reliably manufactured, the stability of the manufacturing process can be improved, and when the etching stopper layer is selectively formed, a high resolution can be obtained. By using a suitable resist, a finer pattern with higher density can be formed.

[0041]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a sectional view showing the structure of a semiconductor device substrate according to a first embodiment of the present invention. The substrate for a semiconductor device includes an insulating layer 1 formed by curing a liquid resin, a plurality of connection electrodes 2 formed on one surface of the insulating layer 1 and arranged to be connectable to a semiconductor chip.
A plurality of wiring regions 3 formed on one surface of the semiconductor device 1 and individually connected to the respective connection electrodes 2, and a surface which is not covered with the insulating layer 1 but is recessed from the surface of the insulating layer 1. Are formed in the other surface of the insulating layer 1 so as to be covered by the insulating layer 1, and the plurality of land electrodes 4 arranged so as to be connectable to an external element, and each land electrode 4 and each wiring region 2 are individually formed. And a plurality of vias 5 connected to the plurality of vias.

The surface composed of each wiring region 3 and the insulating layer 1 is covered with a protective layer 6 except on the connection electrode 2. Here, the insulating layer 1 is formed by applying and drying a liquid insulating resin. As the insulating resin, an epoxy resin-based or acrylic resin-based insulating resin or the like can be applied.

Each connection electrode 2 has a plating layer 2a formed on the surface for good connection to a semiconductor chip. The plating layer 2a has a Ni layer as a base on a conductive layer (copper layer), and an Au layer is formed on the Ni layer.

Each land electrode 4 has a solder layer 4a as an etching stopper layer formed on the surface thereof.
Is partially or entirely removed, as shown in FIG. 2, the surface is not covered with the insulating layer 1 but at a position recessed from the surface of the insulating layer 1 and the side surface is covered with the insulating layer 1. Is formed in the other surface of the insulating layer 1 as shown in FIG.

Next, a method of manufacturing such a semiconductor device substrate will be described. First, 0.2mm sheet
The thick copper alloy 10 is cleaned. After drying, the copper alloy 10
A dry film (not shown) as an acid-resistant tape is adhered to the entire area of the back surface of the substrate. Then, this copper alloy 1
On the surface of No. 0, a photosensitive insulating resin (DPR-105; trade name: manufactured by Asahi Chemical Laboratory Co., Ltd.) to be the insulating layer 1 is printed by screen printing.

The photosensitive insulating resin is exposed and developed in a pattern corresponding to the position where the land electrode 4 is to be formed, whereby the insulating layer at the position where the land electrode 4 is to be formed has a hole diameter of 0.6.
mm, and as shown in FIG.
An insulating layer 1a having a thickness of 0 μm is selectively formed.

Subsequently, an electrolytic nickel plating step is performed using the copper alloy 10 as an electrode, and as shown in FIG.
A solder layer 4a having a thickness of 5 μm is formed on the portion of the copper alloy 10 surrounded by the insulating layer 1a. Since the solder layer 4a serves as a stopper layer when the copper alloy 10 is removed by etching in the final step, the thickness is about 1 μm to 10 μm, particularly 2 μm so that there is no pinhole and sufficient etching resistance is provided. To about 8 μm.

Further, such a copper alloy 10 is immersed in a copper sulfate plating solution and subjected to an electrolytic copper plating step, so that a 10 μm thick copper layer 11 is formed as shown in FIG.
Is formed.

Again, a photosensitive insulating resin to be the insulating layer 1 is printed by screen printing. The insulating resin is exposed and developed in accordance with a pattern that partially exposes the solder layer 4a on each land electrode surface, so that the central insulating layer at the position where the land electrode 4 is formed has a hole diameter of 0.0
The via hole 12 is formed by removing the insulating layer 1a to a thickness of 20 μm as shown in FIG.
In addition, the insulating layer 1 having a thickness of 40 μm is formed.

Next, an electrolytic copper plating process is performed using the copper alloy 10 as an electrode, and a copper plating layer having a thickness of 20 μm is formed in the via hole 12, so that the inside of the via hole 12 is filled with the copper layer and the via hole 5 is formed. Is formed. Thereafter, the upper surface of the via hole 12 and the surface of the insulating layer 1 are buffed and smoothed.

Subsequently, electroless copper plating is applied to the entire surface to a thickness of 0.1 mm.
The copper layer having a thickness of 10.5 μm is formed over the entire surface by performing the plating at 5 μm and the electrolytic plating at a thickness of 10 μm. Further, a photosensitive liquid resist (PMER; trade name: manufactured by Tokyo Ohka Kogyo Co., Ltd.)
It is applied in a thickness of μm. This liquid resist is used for connecting electrode 2
Exposure, development and patterning are performed corresponding to the pattern forming the wiring region 3.

Thereafter, the copper layer is selectively etched and removed, and the resist on the back surface is peeled off together with the dry film, so that the connection electrode 2 and the wiring region 3 are formed as shown in FIG. The structure is as follows.

On the wiring region 3, a resin of the same material as the insulating resin is screen-printed as a protective layer 6, and is exposed and developed in accordance with a pattern for exposing the connection electrode 2 to the semiconductor chip. The upper resin is removed.

The connection electrode 2 was formed by electroless plating with nickel plating having a thickness of 2 μm and gold plating having a thickness of 0.1 μm.
It is applied at 3 μm. That is, as shown in FIG. 4C, a plating layer 2a composed of a Ni layer and an Au layer is formed on the connection electrode 2. The structure shown in FIG. 4C is a semiconductor device substrate that can be shipped.

Subsequently, a dry film for protection is adhered to the circuit formation surface composed of the protective layer 6, the wiring region 3 and the connection electrode 2 (not shown). Thereafter, the copper alloy 10 is formed using ammonium persulfate. Is removed by etching. At this time, the solder layer 4a becomes an etching stopper layer,
As shown in FIG. 4D, only the copper alloy 10 is removed. Subsequently, as shown in FIG. 4E, the solder layer 4a is peeled off and the dry film is peeled off, and the semiconductor device substrate is completed.

As described above, according to the first embodiment, since the insulating layer 1 is formed of a liquid resin, a hole drilling step can be omitted, so that a high-density pattern and a thin shape can be realized. Since a mounting surface having high smoothness can be realized and the surface of each land electrode 4 is located at a position depressed from the surface of the insulating layer 1, the conductive ball is formed on each land electrode 4. When the semiconductor device having the conductive balls formed thereon is mounted on an external element, the protruding surface of the insulating layer 1 acts as a dam, so that the amount of solder for connection can be appropriately controlled,
A failure such as a short circuit in the circuit due to the solder bridge is unlikely to occur, so that an improvement in the reliability of the mounting can be expected.

Further, since the copper alloy 10 is built up on the sheet-shaped copper alloy 10 and then the copper alloy 10 is removed, the insulating layer 1 having high smoothness can be realized. Can be manufactured with reliability.

Further, since the surface of each land electrode 4 is formed of a material functioning as an etching stopper layer, the above-described effects can be easily and reliably achieved. As a manufacturing process, an insulating layer 1a is selectively formed on the sheet-like copper alloy 10, and then a solder layer 4a to be a surface of each land electrode 4 is formed. 4, the insulating layer 1 is formed again, the vias 5, the wiring regions 3 and the connection electrodes 2 are formed, the copper alloy 10 is removed by etching, and the solder layer 4a is removed. Can be easily and reliably manufactured, and the stability of the manufacturing process can be improved.

Further, since the solder layer 4a is provided with high precision and the thickness is easily controlled, and then the solder layer 4a is removed, the amount of depression of the land electrode 4 can be easily controlled.
The amount of solder during mounting can also be controlled with high precision. (Second Embodiment) Next, a semiconductor device substrate according to a second embodiment of the present invention will be described with reference to FIG.

That is, the semiconductor device substrate according to the present embodiment is a modification of the manufacturing method of the first embodiment, and the insulating layer 1 is formed after forming the solder layer 4a on each land electrode 4. The structure of the finished product is the same as the structure shown in FIG.

Next, a method for manufacturing such a semiconductor device substrate will be described. First, 0.2mm sheet
The thick copper alloy 10 is cleaned. After drying, the copper alloy 10
A dry film (not shown) is adhered to the back surface of.
Thereafter, a photosensitive liquid resist (PMER; trade name: manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied to the surface of the copper alloy 10 at a thickness of 25 μm by immersion. The coating thickness of the liquid resist needs to be larger than the thickness of the land electrode 4 to be formed later, and is preferably, for example, about 25 to 50 μm.

The liquid resist is exposed and developed in accordance with the pattern of the land electrode 4 forming position, and developed so that the land electrode 4 forming position has a hole diameter of 0.6 mm.
, And as shown in FIG.
An m-thick resist layer 13 is selectively formed.

Subsequently, electrolytic solder plating is performed using the copper alloy 10 as an electrode, and a 10 μm thick solder layer 4b is formed on the copper alloy 10 surrounded by the resist layer 13 as shown in FIG. Is done. Since the solder layer 4a serves as a stopper layer when the copper alloy 10 is removed by etching in the final step, a part of the solder layer 4a is later etched by etching so as not to have pinholes and to have sufficient etching resistance. For removal, the thickness should be between 5 μm and 15
The thickness is preferably about μm, and particularly preferably about 8 μm to about 10 μm.

The solder layer 4a is subjected to electrolytic copper plating to form a copper layer having a thickness of about 15 μm.
May be reinforced. Next, as shown in FIG. 5C, the resist 13 is stripped.

Subsequently, as described above, a photosensitive insulating resin (DPR-105;
Product name: printed by Asahi Chemical Laboratory Co., Ltd.) The insulating resin is exposed and developed in accordance with the pattern that partially exposes each land electrode 4, and is developed so that the insulating layer at the center of the land electrode 4 forming position has a hole diameter of 0.0.
8 mm to form a via hole 12, and FIG.
As shown in (d), the insulating layer 1 having a thickness of 40 μm is formed.

Electrolytic copper plating is performed using the copper alloy 10 as an electrode, a copper plating layer having a thickness of 20 μm is formed in the via hole 12, and the via hole 12 is filled with the copper layer to form the via 5. . After a while, Via Hole 1
The upper surface 2 and the surface of the insulating layer 1 are buffed and smoothed.

Subsequently, electroless plating was applied to the entire surface to a thickness of 0.5
By applying a thickness of 10 μm and electrolytic plating to a thickness of 10 μm, a 10.5 μm thick copper layer is formed on the entire surface.
Further, a photosensitive liquid resist (PMER) is applied to both surfaces with a thickness of 10 μm by immersion. This liquid resist is exposed corresponding to a pattern for forming the connection electrode 2 and the wiring region 3, and is developed and patterned.

Thereafter, the copper layer is selectively removed by etching using ferric chloride, and the resist on the back surface is peeled off together with the dry film.
As shown in FIG. 7, the structure has a connection electrode 2 and a wiring region 3 formed thereon.

On the wiring region 3, a resin of the same material as the insulating resin is screen-printed as a protective layer 6, and is exposed and developed corresponding to a pattern for exposing the connection electrode 2 to the semiconductor chip, and is developed. The upper resin is removed.

The connection electrode 2 was formed by electroless plating with nickel plating having a thickness of 2 μm and gold plating having a thickness of 0.1 μm.
As shown in FIG. 5F, a plating layer 2a composed of a Ni layer and an Au layer is formed. The structure shown in FIG. 5F is a semiconductor device substrate that can be shipped.

Subsequently, a dry film for protection is adhered to the circuit forming surface composed of the protective layer 6, the wiring region 3 and the connection electrode 2 (not shown), and thereafter, the copper alloy 10 is removed by etching. At this time, the solder layer 4a serves as an etching stopper layer, and only the copper alloy is removed as shown in FIG. Further, as shown in FIG. 5H, the solder layer 4a is etched by 5 μm with ferric chloride, the dry film is peeled off, and the semiconductor device substrate is completed.

As described above, according to the second embodiment, in addition to the effects of the first embodiment, the manufacturing process
A solder layer 4a and each land electrode 4 are selectively formed on a sheet-like copper alloy 10, and thereafter, an insulating layer 1 is sequentially formed, and each via 5, each wiring region 3 and each connection electrode 2 are formed. After the formation, the copper alloy 10 is removed by etching and the solder layer 4a is partially removed, so that a semiconductor device substrate exhibiting the effects of the first embodiment can be easily and reliably manufactured, and the manufacturing process is stable. In addition, when a solder layer 4a is selectively formed, a high-density pattern can be formed by using a high-resolution resist. (Third Embodiment) Next, a semiconductor device according to a third embodiment of the present invention will be described.

FIG. 6 is a cross-sectional view showing the structure of this semiconductor device. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. Only different parts will be described here. That is, the semiconductor device according to the present embodiment
Alternatively, in a modification of the second embodiment, as shown in FIG. 6, a semiconductor chip 21 electrically connected to each connection electrode 2 and a land electrode 4 are individually provided for the device shown in FIG. A plurality of conductive balls 22 are formed, and at least a semiconductor chip 21 and a connection portion to each connection electrode 2 are sealed with an insulating resin 23.

FIG. 4 in the first embodiment.
Since FIG. 5C and FIG. 5F in the second embodiment have the same contents, only the step of FIG. 4C will be described as an example, and the present embodiment will be continued thereafter. Form will be described.

Next, a method for manufacturing such a semiconductor device will be described. After the step shown in FIG. 4C, the semiconductor chip 21 is mounted on the semiconductor chip mounting portion at the center of the substrate,
As shown in FIG. 7A, the semiconductor chip 21 and the connection electrode 2 are connected via the bonding wires 24.

Subsequently, as shown in FIG. 7B, the mounting surface of the semiconductor chip is placed on an insulating resin 23 such as an epoxy resin.
Is sealed. Further, as shown in FIG. 7C, the copper alloy 10 is removed by etching. At this time, since the solder layer 4a of the land electrode 4 serves as an etching stopper, the inside of the land electrode 4, the via 5, and the like are not removed, and only the copper alloy 10 is removed.

Thereafter, as shown in FIG. 7D, the solder layer 4a is peeled and removed, and further, as shown in FIG. 7E, conductive balls 22 are formed on each land electrode 4. Thereby, the semiconductor device is completed.

As described above, according to the third embodiment, the semiconductor chip 21 is connected to the semiconductor device substrate according to the first embodiment, and the semiconductor chip 21 and its connection portion are resin-sealed. Therefore, the operation and effect of the first embodiment can be expected to increase the density and reduce the thickness, and thus to expect higher functionality.

In the manufacturing process, starting from the beginning, an insulating layer 1a is selectively formed on a sheet-shaped copper alloy 10, and then a solder layer 4a to be the surface of each land electrode 4 is formed. Hereinafter, land electrodes 4 are sequentially formed,
The insulating layer 1 is formed again, each via 5, each wiring region 3 and each connection electrode 2 are formed, and the semiconductor chip 2 is connected to each connection electrode 2.
1 are connected, the semiconductor chip 21 and the like are sealed with resin, the copper alloy 10 is removed by etching, the solder layer 4a is peeled off, and the conductive balls 22 are formed on each land electrode 4. Can be easily and reliably manufactured, and the stability of the manufacturing process can be improved.

Although the present embodiment has been described in detail,
In the case where the semiconductor device is manufactured by continuing the post-process of FIG. 5 (f), the solder layer 4 a and the land electrodes 4 are selectively formed on the sheet-shaped copper alloy 10 from the beginning as a manufacturing process. Thereafter, the insulating layer 1 is sequentially formed, each via 5, each wiring region 3, and each connection electrode 2 are formed, and the semiconductor chip 21 is connected to each connection electrode 2.
1 and the like, the copper alloy 10 is removed by etching, the solder layer 4a is partially removed, and the conductive ball 22 is formed on each land electrode 4 (solder layer 4a). It is possible to easily and reliably manufacture a semiconductor device exhibiting the function and effect, improve the stability of the manufacturing process, and further use a high-resolution resist when selectively forming the solder layer 4a. A finer pattern with higher density can be formed. (Other Embodiments) In the third embodiment,
Although the case where the semiconductor device is manufactured by mounting the semiconductor chip 21 and finally removing the copper alloy 10 after the process shown in FIG. 4C or FIG. 5F has been described, the present invention is not limited to this. 4 (e) or solder layer 4 shown in FIG. 5 (h)
After the step of removing a, the step of connecting the semiconductor chip 21 and the connection electrode 2 via the bonding wire 24, the step of sealing the mounting surface of the semiconductor chip 21 with the insulating resin 23, and the step of By adding the step of forming the conductive balls 22, even if a semiconductor device having the structure shown in FIG. 6 is manufactured, the same effect can be obtained by implementing the present invention in the same manner. In addition, the present invention can be implemented with various modifications without departing from the scope of the invention.

[0081]

As described above, according to the first aspect of the present invention, since the insulating layer is formed of a liquid resin, the step of drilling can be omitted, so that a high-density pattern and a thin shape can be realized. In addition, a mounting surface having high smoothness can be realized, and the surface of each land electrode is located at a position recessed from the surface of the insulating layer, so that conductive balls are formed on each land electrode. When mounting the semiconductor device on which the conductive balls are formed on an external element, the protruding insulating layer surface acts as a dam, so that the amount of solder for connection can be appropriately controlled, thereby ensuring the reliability of mounting. It is possible to provide a substrate for a semiconductor device which can be expected to be improved.

Further, according to the invention of claim 2, according to claim 1
A semiconductor chip is connected to the semiconductor device substrate, and the semiconductor chip and its connection portion are resin-sealed, and a conductive ball is formed on each land electrode. Equipment can be provided.

Further, according to the third aspect of the present invention, an insulating layer is selectively formed on a sheet-like metal material, and thereafter, an etching stopper layer serving as a surface of each land electrode is formed. A land electrode is sequentially formed, an insulating layer is formed again, each via, each wiring region and each connection electrode are formed, a metal material is removed by etching, and at least a surface of the etching stopper layer is removed. It is possible to easily and reliably manufacture a semiconductor device substrate exhibiting the effect of 1 and to provide a semiconductor device substrate capable of improving the stability of the manufacturing process.

Further, according to the invention of claim 4, an insulating layer is selectively formed on a sheet-like metal material, and thereafter, an etching stopper layer serving as a surface of each land electrode is formed. A land electrode is formed sequentially, an insulating layer is formed again, each via, each wiring region and each connection electrode are formed, a semiconductor chip is connected to each connection electrode, and the semiconductor chip and the like are resin-sealed, and a metal material is formed. Is removed by etching,
Since at least the surface of the etching stopper layer is removed, a semiconductor device having the effect of the second aspect can be easily and reliably manufactured, and a method of manufacturing a semiconductor device capable of improving the stability of the manufacturing process can be provided.

According to the fifth aspect of the present invention, an etching stopper layer and each land electrode are selectively formed on a sheet-like metal material, and thereafter, an insulating layer is sequentially formed, and each via is formed. Since each wiring region and each connection electrode are formed, the metal material is removed by etching, and at least the surface of the etching stopper layer is removed, so that a semiconductor device substrate exhibiting the effects of claim 1 can be easily and reliably manufactured. It is possible to improve the stability of the manufacturing process, and furthermore, when selectively forming the etching stopper layer, by using a high resolution resist, a semiconductor device substrate capable of forming a finer pattern with higher density can be obtained. Can be provided.

Further, according to the invention of claim 6, an etching stopper layer and each land electrode are selectively formed on a sheet-like metal material, and thereafter, an insulating layer is sequentially formed, and each via is formed. Since each wiring region and each connection electrode are formed, a semiconductor chip is connected to each connection electrode, the semiconductor chip and the like are sealed with a resin, a metal material is removed by etching, and at least a surface of the etching stopper layer is removed. A semiconductor device having the effects of item 2 can be easily and reliably manufactured, and the stability of the manufacturing process can be improved.
By using a high-resolution resist when selectively forming an etching stopper layer, a semiconductor device capable of forming a finer pattern with higher density can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of a semiconductor device substrate according to a first embodiment of the present invention;

FIG. 2 is a perspective view illustrating a schematic configuration of a land electrode in the embodiment.

FIG. 3 is a process sectional view for illustrating the manufacturing method in the embodiment.

FIG. 4 is a process sectional view for illustrating the manufacturing method in the embodiment.

FIG. 5 is a process cross-sectional view for explaining a manufacturing method according to a second embodiment of the present invention.

FIG. 6 is a sectional view showing a configuration of a semiconductor device according to a third embodiment of the present invention;

FIG. 7 is a process sectional view for illustrating the manufacturing method in the embodiment.

FIG. 8 is a cross-sectional view illustrating a configuration of a semiconductor device using a conventional semiconductor device substrate.

FIG. 9 is an enlarged cross-sectional view showing a part of a semiconductor device using a conventional semiconductor device substrate.

[Explanation of symbols]

 1, 1a insulating layer 2 connection electrode 2a plating layer 3 wiring area 4 land electrode 4a solder layer 5 via 6 protective layer 10 copper alloy 11 copper layer 12 via hole 13 resist layer 21 ... Semiconductor chip 22 ... Conductive ball 23 ... Insulating resin 24 ... Bonding wire

Claims (6)

[Claims] An insulating layer formed by curing a liquid resin; a plurality of connection electrodes formed on one surface of the insulating layer and arranged so as to be connectable to a semiconductor chip; A plurality of wiring regions formed and individually connected to the respective connection electrodes; and a surface not covered by the insulating layer but at a position recessed from the surface of the insulating layer, and a side surface covered by the insulating layer. A plurality of land electrodes formed in the other surface of the insulating layer so as to be connectable to an external element, and a plurality of vias for individually connecting the land electrodes and the wiring regions. A substrate for a semiconductor device, comprising: 2. The semiconductor device using the semiconductor device substrate according to claim 1, wherein: a semiconductor chip electrically connected to each of the connection electrodes; and a plurality of conductive layers individually formed on each of the land electrodes. A semiconductor ball, wherein at least the semiconductor chip and a connection part to each of the connection electrodes are sealed with a resin. 3. The method for manufacturing a substrate for a semiconductor device according to claim 1, wherein a liquid resin is selectively applied and cured on a sheet-like metal material at a position different from a position where each of said land electrodes is formed. A first insulating layer forming step of forming an insulating layer by etching, and a plurality of etching stopper layers selectively forming a surface of each of the land electrodes on the metal material and in a portion surrounded by the insulating layer. A layer forming step; a land forming step of forming the land electrodes on the etching stopper layers by plating; and an upper part of the land electrodes and the insulating layer so as to partially expose the land electrodes. A second insulating layer forming step of applying and curing a liquid resin on the upper part to form an insulating layer; and a wiring type for forming the vias, the wiring regions, and the connection electrodes by plating. Step and the etching step of removing the metallic material by etching method of manufacturing a substrate for a semiconductor device characterized by and a stopper layer removing step of removing at least the surface of the etching stopper layer. 4. The method of manufacturing a semiconductor device according to claim 2, wherein a liquid resin is selectively applied and cured on a sheet-like metal material at a position different from a position where each of said land electrodes is formed. A first insulating layer forming step of forming a layer, and a stopper layer forming step of selectively forming a plurality of etching stopper layers on the metal material and in a portion surrounded by the insulating layer to be surfaces of the land electrodes. A land forming step of forming each of the land electrodes on each of the etching stopper layers by plating; and forming an upper portion of each of the land electrodes and an upper portion of the insulating layer so as to partially expose each of the land electrodes. A second insulating layer forming step of applying and curing a liquid resin to form an insulating layer; and a wiring forming step of forming the vias, the wiring regions, and the connection electrodes by plating. A chip connecting step of connecting a semiconductor chip to each of the connection electrodes; a resin sealing step of resin-sealing at least the semiconductor chip and a connection portion to each of the connection electrodes; and removing the metal material by etching. A method of manufacturing a semiconductor device, comprising: an etching step; a stopper layer removing step of removing at least a surface of the etching stopper layer; and a step of individually forming a conductive ball on each of the land electrodes. 5. The method of manufacturing a substrate for a semiconductor device according to claim 1, wherein a plurality of etchings are formed on a sheet-shaped metal material and selectively formed on the surface of each land electrode at a position where the land electrode is formed. A stopper layer forming step of forming a stopper layer, a land forming step of forming the land electrodes on the etching stopper layers by plating, and a step of exposing the land electrodes so as to partially expose the land electrodes. An insulating layer forming step of applying and curing a liquid resin on the upper part and the upper part of the metal material to form an insulating layer; and a wiring forming step of forming the vias, the wiring areas, and the connection electrodes by plating. An etching step of removing the metal material by etching; and a stopper layer removing step of removing at least a surface of the etching stopper layer. A method for manufacturing a substrate for a semiconductor device, comprising: 6. The method of manufacturing a semiconductor device according to claim 2, wherein a plurality of etching stopper layers are formed on a sheet-like metal material and selectively form a surface of each land electrode at a position where each land electrode is formed. A land layer forming step of forming the land electrodes on the etching stopper layers by plating; and forming an upper part of each land electrode so as to partially expose the land electrodes. An insulating layer forming step of applying and curing a liquid resin on the metal material to form an insulating layer; a wiring forming step of forming the vias, the wiring regions, and the connection electrodes by plating; A chip connection step of connecting a semiconductor chip to each connection electrode; and a resin sealing for resin-sealing at least the semiconductor chip and a connection portion to each of the connection electrodes. A method of manufacturing a semiconductor device, comprising: a stopping step; an etching step of removing the metal material by etching; and a stopper layer removing step of removing at least a surface of the etching stopper layer.