JPH10135201A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Problem] From the viewpoint of the number of steps and the reliability of a device, it is optimal to use only an inorganic SOG film without etch-back, but the final firing after coating the inorganic SOG film. Sometimes cracks occur. SOLUTION: An inorganic SOG solution is applied on a semiconductor substrate 1 on which a lower interlayer insulating film 4 is formed. Next, inorganic S
Drying is performed before evaporating the organic solvent contained in the OG solution to form an inorganic SOG film 5. Next, after the upper interlayer insulating film 6 is formed, silanol in the inorganic SOG film 5 is polycondensed to form a silicon oxide film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing an interlayer insulating film in a multilayer wiring.

[0002]

2. Description of the Related Art With the increase in the degree of integration of semiconductor devices, the importance of multilayer wiring technology is increasing. Among the multi-layer wiring techniques, a technique for planarizing an interlayer insulating film is important, and many methods for forming an interlayer insulating film have been developed. However, the forming process is complicated, resulting in an increase in cost.

[0003] As a conventionally used method for obtaining flatness relatively easily, an inorganic SOG solution obtained by dissolving a composition containing silanol as a main component in an organic solvent is spin-coated, and then baked to form a silicon oxide. There is a method of forming a film. In general, the SOG film has a three-layer structure in which the upper and lower portions are sandwiched between insulating films formed by a CVD method.

That is, a lower interlayer insulating film is formed on a lower metal wiring by a low pressure plasma CVD method or the like. In this method, it is necessary to prevent corrosion caused by moisture contained in the SOG film coming into direct contact with the metal wiring. Next, after applying the SOG solution, the substrate is heated on a hot plate at 100 ° C. to 250 ° C. for 1 to 2 minutes to perform pre-drying for evaporating the organic solvent. Then, firing is performed to polycondense the silanol in the SOG film to form a silicon oxide film. Thereafter, an upper interlayer insulating film is formed by a low-pressure plasma CVD method or the like to form a three-layer insulating film.

However, the inorganic SOG film has a problem that cracks are easily generated in the SOG film due to a large volumetric shrinkage due to the polycondensation reaction and the accompanying elimination of water and the like during the firing. In particular, in the case of a metal wiring pattern having a large step, in order to provide sufficient flatness,
Although the SOG film needs to be thicker, the thicker the SOG film is, the more easily cracks occur, and there is a problem that the SOG film cannot be formed to a sufficient thickness.

In general, an organic SOG film is used as a method for suppressing the occurrence of cracks and forming a thick film. The organic SOG film is obtained by introducing an organic group such as an alkyl group into the inorganic SOG film, and the presence of the organic group suppresses the volume shrinkage during firing.
Cracks are less likely to be generated as compared with the film, and the film can be made thicker.

However, as described in the January 1990 issue of "Monthly Semiconductor World" (published by Press Journal Co., Ltd.), the organic SOG film is used when ashing a resist used for forming a via hole with oxygen plasma. , The organic groups in the organic SOG film react,
Replaces hydroxyl group. At this time, it is known that film shrinkage occurs and cracks easily occur. In addition, this reaction produces moisture in the membrane, which causes
It is known that a conduction failure called a "via (Poisoned Via)" is caused.

For this reason, when an organic SOG film is used, it is usual to etch back the organic SOG film so that the organic SOG film is not exposed on the side wall of the via hole.

However, without impairing the flatness, organic SOG
In order to etch back the film, it is necessary to make the etching rate of the SOG film and that of the underlying insulating film the same.
It is difficult to control the etching rate of the G film, and the flatness deteriorates. Furthermore, the thickness of the SOG film depends on the width of the metal wiring and the density of the pattern, and if an attempt is made to completely remove the thick portion of the SOG film, the etching is excessive in the thin portion of the SOG film, and the flatness is deteriorated. To encourage.

[0010] From the characteristics of these SOG films, as a method that has good flatness and does not cause cracks and poor conduction, as disclosed in JP-A-7-122635,
There is a method of using both an inorganic SOG film and an organic SOG film.

That is, as shown in FIG. 2A, a metal layer is formed on a base insulating film 2 formed on a semiconductor substrate 1 made of silicon or the like on which transistors and the like (not shown) are formed. The first layer metal wiring 3 is formed by the photolithography method and the dry etching method. And
A lower interlayer insulating film 4 is formed thereon by a low pressure plasma CVD method. Next, the organic SOG film 9 is formed by applying and firing an organic SOG solution using a spin coater or the like.

Thereafter, as shown in FIG. 2B, etch-back is performed at least until the organic SOG film on the metal wiring disappears. Next, as shown in FIG. 2C, an inorganic SOG solution is applied and fired to polycondense the silanol in the inorganic SOG film 5 to form a silicon oxide film. An upper interlayer insulating film 6 is formed thereon as shown in FIG.

Thereafter, as shown in FIG. 2E, via holes 7 for connecting the first-layer metal wiring and the second-layer metal wiring 8 are formed by photolithography and etching.
To form Then, as shown in FIG. 2F, a second-layer metal wiring 8 is formed. FIG. 2 is a view showing a manufacturing process of a semiconductor device according to the prior art.

In this method, since the organic SOG film 9 in the via hole formation region is etched back, the organic SOG film 9 is not exposed on the side wall of the via hole, and the organic SOG film 9 does not deteriorate due to oxygen plasma during resist ashing. Also,
Deterioration of flatness due to etch back is caused by inorganic SO
Since the step is buried with the G film and the unevenness is reduced and formed, it is not thickened and the generation of cracks is suppressed.

However, in this method, the number of steps such as an etch-back step increases, and the manufacturing cost increases. In addition, the alkyl group of the organic SOG film adversely affects the characteristics of the transistor formed in the lower layer,
It is known that the reliability of the device is reduced, and this method of leaving a thick organic SOG film at a step is also undesirable.

[0016]

As described above, considering the number of steps and the reliability of the device, it is optimal to use only the inorganic SOG film without etch back. However, when the inorganic SOG film is finally baked after being applied, cracks occur as described above.

The present invention uses only an inorganic SOG film,
It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of forming a highly reliable interlayer insulating film without generation of cracks and without affecting transistor characteristics by a simple process at low cost. And

[0018]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first insulating film on a substrate;
An inorganic SOG solution is applied, the solvent is evaporated, and inorganic S
A step of forming an OG film, a step of forming a water-permeable second insulating film on the SOG film, and then polycondensing silanol in the SOG film. .

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device, the substrate temperature at the time of forming the second insulating film is set to 30 degrees.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the temperature is set to 0 ° C. or lower.

Further, in the method of manufacturing a semiconductor device according to the present invention, the second insulating film is formed by a plasma CVD method using tetraethoxysilane and oxygen as raw materials. 3. A method for manufacturing a semiconductor device according to item 2.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.

FIG. 1 is a diagram showing a wiring forming process according to an embodiment of the present invention, and FIG. 3 is a diagram showing a relationship between a firing temperature of an SOG film and a film shrinkage.

In FIG. 1, reference numeral 1 denotes a semiconductor substrate;
Is a base insulating film, 3 is a first-layer metal wiring, 4 is a lower interlayer insulating film, 5 is an inorganic SOG film, 6 is an upper interlayer insulating film, 7
Denotes a via hole, and 8 denotes a second layer metal wiring.

A process for forming a semiconductor device according to an embodiment of the present invention will be described below with reference to FIG.

First, as shown in FIG. 1A, an aluminum alloy is formed on a base insulating film 2 formed on a semiconductor substrate 1 made of silicon or the like on which transistors and the like (not shown) are formed by sputtering. Alternatively, a metal layer composed of a laminated film of a refractory metal such as titanium tungsten and an aluminum alloy is formed so as to have a total thickness of about 1 μm, and the first layer is formed by a known photolithography method and a dry etching method.
The layer metal wiring 3 is formed. Then, a silicon oxide film having a thickness of about 3000 ° is formed thereon as a lower interlayer insulating film 4 by a low pressure plasma CVD method.

The lower interlayer insulating film 4 may use another film such as a silicon nitride film or a SiON film. Also, the formation method may be another method such as a PVD method (physical vapor deposition method) such as a normal pressure CVD method or a sputtering method.

Next, an inorganic SOG solution is applied on a flat substrate to a thickness of about 4000 ° by a spin coater. And on the hot plate 100 ~
Heating at 250 ° C. for 1 to 2 minutes to dry before evaporating the organic solvent contained in the inorganic SOG solution,
A film 5 is formed. At this time, the inorganic SOG film 5 having a thickness of 1 μm or more is accumulated in the space portion of the metal wiring.

In order to polycondense the silanol in the inorganic SOG film 5 to form a silicon oxide film, it is necessary to perform a heat treatment. At this time, the temperature of the inorganic SOG film 5
In order to sufficiently remove moisture in the inorganic SOG film 5 so that a defect such as swelling due to degassing from the inorganic SOG film 5 does not occur in a heat treatment process after the formation, the maximum after the inorganic SOG film 5 is formed. Generally, the temperature is set to 400 to 450 ° C.

However, the inorganic SOG film 5 is formed by the conventional SOG film forming process shown in FIG.
Before the upper interlayer insulating film 6 was formed thereon, a final baking was performed at 420 ° C. for 30 minutes in a furnace in a nitrogen atmosphere, and cracks occurred.

Therefore, as shown in the SOG film forming process of the present invention shown in FIG. 1, the upper interlayer insulating film is formed before the final baking, and the baking is performed thereafter to prevent the occurrence of cracks. Was.

That is, as shown in FIG.
And oxygen as raw materials, the RF frequency is 13.56 MHz,
An RF power of 470 W, a pressure of 9 Torr, and a silicon oxide film of about 4000 ° are formed as an upper interlayer insulating film by a low pressure plasma CVD method. At this time, the temperature of the semiconductor substrate 1 needs to be 300 ° C. or less. This is because if the film is formed at a higher temperature, the upper interlayer insulating film 6
This is because cracks are generated in the inorganic SOG film 5 during the film formation.

As can be seen from FIG. 5, the film shrinkage causing cracks increases as the temperature increases, and at 400 ° C., the film shrinks by 10% or more. In contrast, at 300 ° C, 3
%, The film shrinks only about 300%. Therefore, if the upper interlayer insulating film is formed at about 300 ° C. or less, the inorganic SOG
No cracks occur in the film.

In this case, since unreacted silanol remains in the inorganic SOG film 5, it is necessary to perform final baking at 400 to 450 ° C., but after forming the upper interlayer insulating film 6, it is required to be 400 ° C. or more. Inorganic SO
Desorption of water and the like generated by the polycondensation reaction from the G film 5
Since the process is performed through the upper interlayer insulating film, the upper interlayer insulating film 6 is formed.
It is performed more slowly than when there is no membrane, and rapid membrane shrinkage is suppressed. Further, since the upper interlayer insulating film 6 physically fixes the inorganic SOG film 5, no crack occurs.

The upper interlayer insulating film 6 is not limited to the silicon oxide film as long as it is a film having water permeability. Also,
The formation method may be another method as long as it can be formed at about 300 ° C. Further, the heat treatment for the final baking of the inorganic SOG film 5 does not necessarily need to be performed immediately after the formation of the upper interlayer insulating film 6, and may be performed, for example, after a later via hole forming step.

Immediately after the application of the inorganic SOG solution,
At the time of final baking at 0 ° C., occurrence of defects due to stress migration was observed in the first-layer metal wiring. This is considered to be caused by a large stress applied to the first-layer metal wiring when the inorganic SOG film shrinks. However, when formed by the method of the present invention, the stress at the time of firing is reduced, and the occurrence of defects in the first-layer metal wiring such as aluminum wiring can be prevented.

Thereafter, via holes 7 for connecting the first-layer metal wiring and the second-layer metal wiring are formed by known photolithography and etching. Then, a metal layer composed of a laminated film of a refractory metal such as titanium tungsten and an aluminum alloy is formed by a sputtering method, and a second-layer metal wiring 8 is formed by a known photolithography method and an etching method.

Although the present embodiment is an example in which an interlayer insulating film is formed between the first-layer metal wiring and the second-layer metal wiring, the present invention comprises more multilayer wirings. Needless to say, it can be used as an interlayer insulating film between the second-layer metal wiring and the third-layer metal wiring of the semiconductor device or between higher-level wirings.

[0038]

As described above in detail, by using the present invention, the inorganic SOG which is liable to crack is produced.
When the film is subjected to final baking after forming an upper interlayer insulating film having water permeability, the release of moisture and the like from the inorganic SOG film is performed through the upper interlayer insulating film, so that the film becomes gentler. Is suppressed, and the upper interlayer insulating film is physically and mechanically made of inorganic S
There is also an effect of fixing the OG film, and the occurrence of cracks can be suppressed.

Further, since the film shrinkage is suppressed, the stress on the wiring of aluminum alloy or the like can be reduced, and the stress migration of the wiring of aluminum alloy or the like can be prevented.

Further, by forming the substrate temperature at 300 ° C. or less during the formation of the upper interlayer insulating film formed on the SOG film, the occurrence of cracks in the SOG film is prevented.

Therefore, according to the present invention, an interlayer insulating film having high reliability and good flatness can be formed by a simple method.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of a conventional semiconductor device.

FIG. 3 is a diagram showing a relationship between a firing temperature of an inorganic SOG film and a film shrinkage.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor substrate 2 base insulating film 3 first layer metal wiring 4 lower interlayer insulating film 5 inorganic SOG film 6 upper interlayer insulating film 7 via hole 8 second layer metal wiring

Claims (3)

[Claims] After forming a first insulating film on a substrate, an inorganic SOG solution is applied, a solvent is evaporated, and an inorganic SOG solution is evaporated.
A semiconductor device comprising: forming a G film; forming a second insulating film having water permeability on the SOG film; and then polycondensing silanol in the SOG film. Manufacturing method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a substrate temperature at the time of forming said second insulating film is set to 300 ° C. or less. 3. The method according to claim 2, wherein said second insulating film is formed by a plasma CVD method using tetraethoxysilane and oxygen as raw materials.