JPH10149149A - Image processing device - Google Patents

Abstract

(57) [Summary] To provide an image processing device capable of displaying graphic data and video data in full color at high speed. SOLUTION: The present invention relates to a graphic accelerator 1 for converting 8-bit graphic data stored in a memory into graphic data in a bitmap format.
6, a full-color conversion circuit 17 for converting the converted graphic data into full-color data, a separating unit 23 for separating audio data and video data from the bit stream data stored in the memory, A 24-bit frame buffer 19 for storing data and full-color data, a frame buffer control circuit 18 for controlling storage of full-color data and video data in the frame buffer, and converting video data and full-color data into video signals. D / A conversion means 20 is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an image processing apparatus.

[0002]

2. Description of the Related Art At present, computers such as workstations generally process 24-bit video data with pseudo-color data (for example, 8-bit palette data).

[0003] Also, 24-bit graphic data is rapidly converted to a bitmap format by a graphic accelerator. Here, the graphic data is data indicating a figure or the like, and the video data is data indicating a character or the like.

FIG. 3 is a diagram for explaining a method of processing video data and graphic data by such a conventional image processing apparatus. The main memory 3 connected to the system bus 1 stores 8-bit graphic data and
Bit image data is stored.

[0005] The 8-bit graphic data stored in the main memory 3 is transferred to the graphic accelerator 4 via the system bus 1. Then, the graphic data is converted into a bitmap format by the graphic accelerator 4 and then stored in the 8-bit frame buffer 5.

On the other hand, the 24-bit video data is converted into 8-bit data by software processing by the CPU 2 connected to the system bus 1 and then stored in the frame buffer 5.

The graphic data and video data stored in the 8-bit frame buffer 5 are converted into 24-bit graphic data and video data by a full-color conversion circuit 6.

[0008] The 24-bit graphic data and video data converted by the full color conversion circuit 6 are converted into video signals by a video D / A conversion circuit 7.

That is, in such a computer,
In order to display 24-bit video data, it was necessary to convert the video data to 8-bit pseudo-color data by software to reduce the number of colors.

FIG. 4 is a diagram for explaining a method of processing video data and graphic data in an image processing apparatus using a 24-bit frame buffer. In an image processing apparatus using such a 24-bit frame buffer, it is not necessary to reduce the number of colors as in an image processing apparatus using an 8-bit frame buffer.
After converting the 8-bit graphic data into 24 bits by software processing, it is stored in the frame buffer 5.

The graphic data and video data stored in the 24-bit frame buffer 8 are converted into video signals by a video D / A conversion circuit 7.

[0012]

However, in the image processing apparatus using the above-described 8-bit frame buffer, it is necessary to convert 24-bit video data into 8-bit video data by software processing to reduce the number of colors. Therefore, there is a problem that the display speed is reduced.

Further, since 24-bit video data is converted into 8-bit (256 colors) video data by software using a reduced number of colors, there is a problem that image quality is reduced.

On the other hand, in an image processing apparatus using a 24-bit frame buffer, video data
Although it can be displayed in full color of bits, but this time there is no graphic accelerator, the conversion of 8-bit graphic data to the bitmap format into the 24-bit frame buffer 8 is performed by software processing. There was a problem that it took time to display.

The present invention has been made in view of the above circumstances, and has as its object to provide an image processing apparatus capable of displaying graphic data and video data in full color at high speed.

[0016]

Therefore, first, in order to achieve the above object, a first invention is to provide a graphic accelerator for converting 8-bit graphic data stored in a memory into graphic data in a bitmap format. A full-color conversion circuit for converting 8-bit graphic data in a bitmap format converted by the graphic accelerator into 24-bit full-color data; and audio data and 24-bit video among bit stream data stored in a memory. Separation means for separating the full-color data, 24-bit video data separated by the separation means, and 24-bit frame buffer for storing 24-bit full-color data output from the full-color conversion circuit; And the movie An image processing apparatus comprising: a frame buffer control circuit for storing data in the frame buffer; and D / A conversion means for converting video data and full color data stored in the frame buffer into video signals. It is.

According to a second aspect, in the image processing apparatus according to the first aspect, the storing of the full-color data and the video data in the frame buffer by the frame buffer control circuit is performed based on a predetermined write priority. It is characterized by being performed.

Further, a third invention is the image processing apparatus according to the first invention, further comprising an address conversion means for performing an address conversion of the video data written in the frame buffer and enlarging / reducing the video data. It is characterized by doing.

Further, a fourth invention is the image processing apparatus according to the first invention, further comprising an audio signal output means for outputting the audio data separated by the separation means as audio. is there.

According to a fifth aspect of the present invention, in the image processing apparatus of the first aspect, a television signal separating unit for separating a television signal into a television video signal and a television audio signal, and the television signal separating unit separates the television signal. It further comprises a TV video writing unit for writing a TV video signal into the frame buffer, and a TV audio signal output unit for outputting the TV audio signal separated by the TV signal separation unit as audio. .

Further, a sixth invention is the image processing apparatus according to the first invention, wherein the transfer of the 8-bit graphic data to the graphic accelerator is performed by DMA transfer.

Further, a seventh invention is the image processing apparatus according to the first invention, wherein the transfer of the bit stream data to the frame buffer is performed by DMA transfer.

Next, the operation of the first to seventh inventions will be described. That is, the first invention converts 8-bit graphic data stored in a memory into graphic data in a bitmap format by a graphic accelerator, and converts the graphic data in a bitmap format converted by a graphic accelerator into a full-color conversion circuit. 2 bit graphic data
Convert to 4-bit full color data.

[0024] Also, by the separating means, of the bit stream data stored in the memory, audio data and 2
The full color data and the video data are stored in the frame buffer by a frame buffer control circuit, and the video data and the full color data stored in the frame buffer are converted into a video signal by a D / A converter. , Graphic data and video data can be displayed in full color at high speed.

According to a second aspect of the present invention, in the image processing apparatus of the first aspect, the storing of the full color data and the video data in the frame buffer by the frame buffer control circuit is performed based on a predetermined write priority. Even when video data and full-color data are written to the frame buffer in contention, data can be normally stored in the frame buffer.

According to a third aspect of the present invention, in the image processing apparatus according to the first aspect of the present invention, the address conversion means performs an address conversion of the video data written in the frame buffer to enlarge or reduce the video data.

According to a fourth aspect of the present invention, in the image processing apparatus of the first aspect, since the audio signal output means outputs the audio data separated by the separation means as audio, the audio can be heard together with the video. .

In a fifth aspect of the present invention, a television signal separating unit separates a television signal into a television video signal and a television audio signal, and the television video writing unit converts the television video signal separated by the television signal separating unit. Write to the frame buffer. Then, since the television audio signal output unit outputs the television audio signal separated by the television signal separation unit as audio, the audio can be heard in synchronization with the television video.

According to a sixth aspect of the invention, in the image processing apparatus of the first aspect, since the transfer of the 8-bit graphic data to the graphic accelerator is performed by DMA transfer, the graphic data can be transferred without burdening the CPU. Transfer can be performed at high speed.

According to a seventh aspect, in the image processing apparatus according to the first aspect, the transfer of the bit stream data to the frame buffer is performed by DMA transfer.
Bit stream data can be transferred at a high speed without burdening the CPU.

[0031]

Embodiments of the present invention will be described below with reference to the drawings. <First Embodiment> FIG. 1 is a diagram showing a configuration of an image processing apparatus according to a first embodiment of the present invention. The dashed arrow in FIG. 1 indicates the direction of control.

As shown in FIG. 1, an image processing apparatus according to this embodiment comprises a CPU 11, a main memory 12, a system bus 1
3, graphic data FIFO 14, DMA control circuit 15, graphic accelerator 16, full color conversion circuit 17, frame buffer control circuit 18, frame buffer 19, video D / A conversion circuit 20, bit stream FIFO 21, DMA control circuit 22, video / audio Separation circuit 23, video stream FIFO 24, video decoder 25, video decode control circuit 26, video FIFO 2
7, an enlargement / reduction calculation circuit 28, a write control circuit 29, a display control circuit 30, an audio decode control circuit 31, an audio stream FIFO 32, an audio decoder 33, and an audio D / A conversion circuit 34.

The CPU 11 controls the entire apparatus such as accessing data on the main memory 12 and setting parameters of each control circuit. The main memory 12 stores an operating system (OS), various user programs, and various data, and stores graphic data and video data.

The system bus 13 is a transfer path for instructions of the CPU 11 and various data. Graphic data FIF
O14 is a buffer for temporarily storing graphic data DMA-transferred through the system bus 13.

The DMA control circuit 15 transfers the graphic data generated by the program and stored in the main memory 12 to the graphic data FIFO 14 by DMA. The graphic accelerator 16 converts graphic data temporarily stored in the graphic data FIFO 14 into 8-bit graphic data in a bitmap format.

The full color conversion circuit (LUT) 17 has 8
24 bits of bitmap graphic data
Convert to full bit data. The frame buffer control circuit 18 converts the 24-bit full color data converted by the full color conversion circuit 17 and the video FIFO
The writing of the video data output from 27 and the control of the frame buffer 19 are performed.

The frame buffer 19 is a memory for storing display data composed of 24 bits per pixel.
The full-color conversion circuit 17 stores 24-bit full color data and 24-bit video data output from the video FIFO 27.

The video D / A conversion circuit 20 converts the 24-bit display data stored in the frame buffer 19 into a video signal (analog). The bit stream FIFO 21 is transmitted to the main memory 1 through the system bus 13.
2 bit stream data (video /
(Compressed audio data) temporarily.

The DMA control circuit 22 transfers the bit stream data stored in the main memory 12 to the bit stream FIFO 21 via the system bus 13 by DMA.

The video / audio separation circuit 23 separates the bit stream data temporarily stored in the bit stream FIFO 21 into video bit stream data and audio bit stream data.

The video bit stream FIFO 24 temporarily stores the video bit stream data separated by the video / audio separation circuit 23. Video decoder 25
Decodes (decompresses) video bit stream data stored in the video bit stream FIFO 24.

The video decoding control circuit 26 controls the video bit stream FIFO 24 and the video decoder 25. The video FIFO 27 temporarily stores 24-bit video data decoded by the video decoder 25.

The enlargement / reduction calculation circuit 28 includes a video FIFO.
The address calculation for enlarging / reducing an image displayed by the image data stored in the image buffer 27 is performed, and the transfer of the image data from the image FIFO 27 to the frame buffer control circuit 18 is controlled. The write control circuit 29 controls the timing at which the video data is written to the frame buffer 19, and realizes a smooth display of the video data.

The display control circuit 30 includes the frame buffer 1
9 to read and control the video data and the full-color-converted graphic data stored in the memory 9. The audio decode control circuit 31 controls the audio stream FIFO 32 and the audio decoder 33.

The audio stream FIFO 32 temporarily stores the audio bit stream data separated by the video / audio separation circuit 23. The audio decoder 33 decodes the audio bit stream data stored in the audio stream FIFO 32 and outputs it as audio data. The audio D / A conversion circuit 34 converts the decoded audio data into an audio signal (D / A conversion).

Next, the operation of the image processing apparatus according to the present embodiment configured as described above will be described. First, a method of writing graphic data to the frame buffer 19 will be described.

This graphic data is vector-format data generated by various user programs.
First, graphic data generated by a program and stored in the main memory 12 is DMA-transferred to the graphic data FIFO 14 by the DMA control circuit 15.

As described above, the graphic data stored in the main memory 12 is transferred to the DMA control circuit 15 by the DMA control circuit 15.
By transferring the graphic data, graphic data can be transferred at high speed without imposing a load on the CPU 11.

The graphic accelerator 16 converts 8-bit graphic data temporarily stored in the graphic data FIFO 14 into 8-bit pseudo color data (bitmap data).

By the graphic accelerator 16,
The converted 8-bit bitmap data is converted by the full-color conversion circuit 17 into 24-bit full-color data.

Thus, it is possible to convert 8-bit bitmap data into 24-bit bitmap data at high speed. Then, a full-color conversion circuit (LU
The 24-bit full color data converted by T) 7 is written to the frame buffer 19 by the frame buffer control circuit 18.

Next, a method for processing bit stream data composed of video and audio compressed data will be described. First, the DMA control circuit 22 transfers the bit stream data stored in the main memory 12 to the bit stream FIFO 21 via the system bus 13 in a DMA manner.
Forward.

Thus, the bit stream data can be transferred at a high speed without imposing a burden on the CPU 11. Next, the video / audio separation circuit 23 separates the bit stream data temporarily stored in the bit stream FIFO 21 into video bit stream data and audio bit stream data.

The separation of the video bit stream data and the audio bit stream data of the bit stream data by the video / audio separation circuit 23 is performed by the DMA control circuit 2
2 is performed.

The video bit stream data and the audio bit stream data separated by the video / audio separation circuit 23 are temporarily stored in a video stream FIFO 24 and an audio stream FIFO 32, respectively.

The video bit stream data stored in the video stream FIFO 24 is decoded (expanded) by the video decoder 25 and then temporarily stored in the video FIFO 27.

The reading of the video bit stream data stored in the video stream FIFO 24 and the decoding by the video decoder 25 are performed by the video decoding control circuit 2.
6 is performed.

The 24-bit video data stored in the video FIFO 27 is written into the frame buffer 19 by the frame buffer control circuit 18. The write address of the video data to the frame buffer 19 at this time is calculated by the enlargement / reduction calculation circuit 28, and the write timing is controlled by the write control circuit 19.

The 24-bit full color data and the video FIFO 2 output from the full color conversion circuit 17
When the video data output from 7 is output to the frame buffer control circuit 18 at the same time, the frame buffer control circuit 18 writes to the frame buffer 19 according to a preset write priority.

Here, the frame buffer control circuit 18
When the full color data and the video data are simultaneously output, the writing of the video data to the frame buffer 19 by the frame buffer control circuit 18 is performed with priority.

The full color data and the video data stored in the frame buffer 19 are transferred to the video D / A conversion circuit 2.
By 0, it is converted to a video signal and then displayed on a monitor.

Thus, video data and graphic data can be displayed in full color at high speed and simultaneously. Next, processing of audio bit stream data stored in the audio stream FIFO 32 will be described.

The audio bit stream data stored in the audio stream FIFO 32 is decoded by the audio decoder 33. The audio bit stream data decoded by the audio decoder 33 is further converted to an audio signal by an audio D / A conversion circuit 34.

The converted audio signal is output as audio by a speaker. Thereby, it becomes possible to listen to the audio together with the video. In the above description of the embodiment, the case where the video data and the bit stream data are stored in the same main memory 12 has been described. However, these data may be stored in separate memories. Good.

Further, in the above description of the embodiment, the case where the writing to the frame buffer 19 by the frame buffer control circuit 18 is performed with priority given to the video data has been described, but the priority may be given to full color data. .

Therefore, according to the image processing apparatus of the present embodiment, full-color graphics and images can be displayed simultaneously and at high speed without deteriorating the image quality.
When full-color data and video data are input simultaneously, the frame buffer control circuit 19 writes data to the frame buffer 19 according to a preset priority. Data can be written to the buffer 19.

Further, the address calculation for enlarging or reducing the video data can be performed by the enlarging / reducing calculating circuit 28, so that the video data can be displayed after being expanded or reduced.

Further, the video / audio separation circuit 23 separates the video bit stream data and the audio bit stream data of the bit stream data stored in the bit stream FIFO 21 and outputs the separated audio data as audio. , And an image synchronized with the image can be obtained.

Further, the DMA control circuit 15 converts the graphic data stored in the main memory 12 into DMA data.
Since graphic data can be transferred, graphic data can be transferred at high speed without imposing a load on the CPU 11.

Further, the bit stream data stored in the main memory 12 is
Since MA transfer can be performed, bit stream data can be transferred at high speed without imposing a load on the CPU 11.

Further, in this embodiment, it is not necessary to separately provide a frame buffer for video data and graphic data for graphic data, and a common frame buffer can be used. <Second Embodiment> FIG. 2 is a diagram showing a configuration of an image processing apparatus according to a second embodiment of the present invention. Note that the same parts as those in FIG.

The image processing apparatus according to the first embodiment differs from the image processing apparatus according to the second embodiment in that a television tuner 41, a video FIFO 42, and an audio FIFO 43 are provided.

The TV tuner 41 decodes a TV signal received from the antenna. The video FIFO 42 is
Of the television signals decoded by the television tuner 41, the television video data is temporarily stored and output to the write control circuit 29.

The audio FIFO 43 is a television tuner 41
The TV audio data is temporarily stored in the TV signal decoded by the TV signal and output to the audio D / A conversion circuit 34.

Next, the operation of the image processing apparatus configured as described above will be described. First, a television signal is decoded by the television tuner 41, and among the decoded television signals, the television video data is temporarily stored in the video FIFO.
At the same time as being stored in O42, the television audio data is temporarily stored in the audio FIFO 43.

The video data stored in the video FIFO 42 is output to the write control circuit 29 and written into the frame buffer 19 by the frame buffer control circuit 18.

Then, the television video data written in the frame buffer 19 is converted into a video signal by the video D / A conversion circuit 20 and displayed on a monitor. Thereby, television video, graphic data and video data can be displayed simultaneously.

On the other hand, the television audio data stored in the audio FIFO 43 is converted into an audio signal by the audio D / A conversion circuit 34. Thereby, it is possible to listen to the audio synchronized with the television image.

In the above description of the embodiment, the television signal has been described. However, the present invention is not limited to the television signal, but may be a video signal from a video device. Video image data of the video signal is stored, and control data of the video signal is stored in the audio FIFO 43.

Therefore, according to the image processing apparatus of the present embodiment, in addition to the effects of the image processing apparatus of the above-described first embodiment, it is possible to simultaneously perform video display and audio output of a television.

Further, a common frame buffer can be used without separately providing a frame buffer for video data of a television signal and a frame buffer for video data and graphic data.

[0082]

As described above in detail, according to the present invention,
An image processing apparatus capable of displaying graphic data and video data in full color at high speed can be provided.

Further, according to the present invention, even when video data and full-color data are written to the frame buffer in a conflict, data can be normally stored in the frame buffer.

Further, according to the present invention, the image represented by the image data can be enlarged or reduced. Furthermore, according to the present invention, since the audio data separated by the separating means is output as audio, the audio can be heard together with the video.

Further, according to the present invention, audio can be heard in synchronization with television video. Further, according to the present invention, graphic data can be transferred at high speed without imposing a load on the CPU. Further, according to the present invention, bit stream data can be transferred at high speed without imposing a load on the CPU.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of an image processing apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of an image processing apparatus according to a second embodiment of the present invention.

FIG. 3 is a diagram illustrating a configuration of a conventional image processing apparatus.

FIG. 4 is a diagram illustrating a configuration of a conventional image processing apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... System bus, 2 ... CPU, 3 ... Main memory, 4 ... Graphic accelerator, 5 ... Frame buffer, 6 ... Full color conversion circuit (LUT) 7 ... Video D / A conversion circuit, 8 ... Frame buffer 11 ... CPU, 12 ... Main memory, 13 ... System bus, 14 ... Graphic data FIFO, 15 ... DMA control circuit, 16 ... Graphic accelerator, 17 ... Full color conversion circuit, 18 ... Frame buffer control circuit, 19 ... Frame buffer, 20 ... Video D / A Conversion circuit, 21: bit stream FIFO, 22: DMA control circuit, 23: video / audio separation circuit, 24: video bit stream FIFO, 25: video decoder, 26: video decode control circuit, 27: video FIFO, 28: enlargement・ Reduction calculation circuit, 29… Write Control circuit, 30: display control circuit, 31: audio decode control circuit, 32: audio stream FIFO, 33: audio decoder, 34: audio D / A conversion circuit, 41: television tuner, 42: video FIFO, 43: audio FIFO .

Claims (7)

[Claims] 1. A graphic accelerator for converting 8-bit graphic data stored in a memory into graphic data in a bitmap format, and converting the 8-bit graphic data in the bitmap format converted by the graphic accelerator into 24 bits.
A full-color conversion circuit for converting the data into bit full-color data, a separating unit for separating audio data and 24-bit video data from the bit stream data stored in the memory, and a 24-bit separated by the separating unit. A 24-bit frame buffer that stores video data and 24-bit full color data output from the full color conversion circuit; a frame buffer control circuit that stores the full color data and the video data in the frame buffer; An image processing apparatus comprising: D / A conversion means for converting video data and full color data stored in a buffer into a video signal. 2. The image processing apparatus according to claim 1, wherein the storage of the full-color data and the video data in the frame buffer by the frame buffer control circuit is performed based on a predetermined write priority. . 3. The image processing apparatus according to claim 1, further comprising address conversion means for performing address conversion of video data written to said frame buffer and enlarging / reducing the video data. 4. The image processing apparatus according to claim 1, further comprising an audio signal output unit that outputs the audio data separated by the separation unit as audio. 5. A TV signal separating unit for separating a TV signal into a TV video signal and a TV audio signal, a TV video writing unit for writing the TV video signal separated by the TV signal separating unit into the frame buffer, 2. The image processing apparatus according to claim 1, further comprising a television audio signal output unit that outputs a television audio signal separated by the television signal separation unit as audio. 6. The image processing apparatus according to claim 1, wherein the transfer of the 8-bit graphic data to the graphic accelerator is performed by a DMA transfer. 7. The image processing apparatus according to claim 1, wherein the transfer of the bit stream data to the frame buffer is performed by a DMA transfer.