JPH10161149A - Method of manufacturing array substrate for display device - Google Patents

Abstract

(57) [Problem] To provide an array substrate for a display device which ensures high productivity without lowering the production yield. A scanning line (111) and a first insulating film (1) on the scanning line (111) are provided.
15), (117), the semiconductor film (120) on this, the semiconductor film (120)
A thin film transistor (112) including a source electrode (126b) and a drain electrode (126a) electrically connected to a signal line (110) derived from the drain electrode (126a) and substantially orthogonal to the scanning line (111). And a pixel electrode (131) electrically connected to the source electrode (126b). The pixel electrode (131) is provided at least via a second insulating film (127) disposed on the signal line (110). It is electrically connected to the source electrode (126b), and covers the upper surface of the drain electrode (126a) and the upper surface of the signal line (110) with the same material as the pixel electrode (131).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method of manufacturing an array substrate for a display device used for a flat display device such as a liquid crystal display device.

[0002]

2. Description of the Related Art In recent years, flat display devices replacing CRT displays have been actively developed. Among them, liquid crystal display devices have attracted particular attention because of their advantages such as light weight, thinness, and low power consumption.

[0003] For example, a light-transmitting active-matrix liquid crystal display device in which a switch element is arranged for each display pixel will be described as an example. The active matrix type liquid crystal display device has a configuration in which a liquid crystal layer is held between an array substrate and a counter substrate via an alignment film. In the array substrate, a plurality of signal lines and scanning lines are arranged in a grid on a transparent insulating substrate such as glass or quartz, and amorphous silicon (hereinafter abbreviated as a-Si: H) is provided at each intersection. (Hereinafter abbreviated as TFT) using a semiconductor thin film of the above. The gate electrode of the TFT is electrically connected to the scanning line, the drain electrode is electrically connected to the signal line, and the source electrode is electrically connected to a transparent conductive material constituting the pixel electrode, for example, ITO (Indium-Tin-Oxide). Have been.

[0004] The opposing substrate is configured such that an opposing electrode made of ITO is disposed on a transparent insulating substrate such as glass, and a color filter layer is disposed for realizing color display.

[0005]

In the manufacture of the above array substrate, wet etching has conventionally been used for ITO pattern processing. However, recently, in order to improve pattern processing accuracy and base selectivity, HI (Iodine) has been used. The introduction of dry etching with (hydrogen) gas or the like is being studied.

However, during the dry etching, the wiring made of Al, Mo, or the like is hardly corroded. However, if the leaving time after the dry etching until the resist stripping process is long, the residual HI on the array substrate absorbs moisture and hydrogen iodide is absorbed. It becomes acid and corrodes wiring. Due to this corrosion, in the test after the completion of the array substrate, defective TFT characteristics, open signal lines and short-circuits between lines frequently occur.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a method of manufacturing an array substrate for a display device which ensures high productivity without lowering the manufacturing yield. .

[0008]

According to a first aspect of the present invention, there is provided a method of manufacturing an array substrate for a display device, comprising: a scanning line disposed on a substrate; a first insulating film disposed thereon; A semiconductor film disposed on the film, a thin film transistor including a source electrode and a drain electrode electrically connected to the semiconductor film, a signal line derived from the drain electrode and substantially orthogonal to the scanning line, A method for manufacturing an array substrate for a display device, comprising: a pixel electrode electrically connected to a source electrode; and forming the pixel electrode by patterning an electrode thin film by dry etching. The drain electrode or the signal line is not exposed to an etching gas.

According to the above manufacturing method, the source electrode, the drain electrode and the signal line are not exposed to the etching gas, so that they are not corroded by, for example, hydroiodic acid during dry etching.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A liquid crystal display (1) according to an embodiment of the present invention will be described below with reference to FIGS.

This liquid crystal display device (1) is of a light transmission type capable of displaying a color image. As shown in FIG.
An alignment film (1) made of a polyimide resin between the (100) and the counter substrate (200) and subjected to an alignment process in directions orthogonal to each other.
Twisted nematic (TN) liquid crystal is held via (41) and (241). Polarizing plates (311) and (313) are attached to the outer surfaces of the array substrate (100) and the opposing substrate (200), respectively.

FIG. 1 is a schematic plan view of an array substrate (100), in which the lower side in the figure is located on the upper side of the screen of the liquid crystal display device (1), and the lower side in FIG. , The scanning lines are sequentially selected.

The array substrate (100) has 480 scanning lines (1) made of an Al--Y alloy disposed on a glass substrate (101).
11), and one end of each scanning line (111) is connected to a glass substrate (10).
1) is pulled out to one end side (101a) side, and the oblique wiring part (150)
And is electrically connected to the scanning line pad (152). Here, the scanning line (111) is made of an Al-Y alloy,
-Ta alloy, Mo-W alloy, Al, or an alloy thereof may be used.

The array substrate (100) includes, on a glass substrate (101), 1920 signal lines (110) made of an Al-Y alloy which are substantially orthogonal to the scanning lines (111), and each signal line (110) is The glass substrate (101) is drawn out to the other end (101b) side, and is electrically connected to the signal line pad (162) through the oblique wiring portion (160). Here, the signal line (110) is made of an Al-Y alloy, but the Mo-Ta alloy, the Mo-W alloy, Al, or
It may be made of the alloy or the like.

A TFT (112) is arranged near the intersection of the scanning line (111) and the signal line (110). Also,
Pixel electrode made of ITO connected to this TFT (112)
(131) is arranged on the scanning line (111) and the signal line (110) via an interlayer insulating film (127). This interlayer insulating film (12
7) can be composed of an inorganic insulating film such as a silicon nitride film or a silicon oxide film, or an organic resin film such as an acrylic resin.By forming a multilayer film of these inorganic insulating films and an organic resin film, In addition, the surface smoothness and interlayer insulation are further improved.

The signal line pad (162) and the oblique wiring portion (1)
60), the upper surface of the signal line (110), the scanning line pad (152), the oblique wiring portion (150), and the upper surface of the drain electrode (126a) provided continuously from the signal line (110). Interlayer insulating film
Protective films (131a) (131b) (131c) made of the same material as the pixel electrode (131) are formed via (127). This protective film
FIG. 2 is a plan view showing a state where (131) is formed. In this figure, the hatched portions indicate the portions where the protective film (131) is formed.

(Structure of TFT Region) The structure of the TFT (112) region will be described.

Each scanning line (111) is connected to an adjacent pixel electrode (13).
1) includes an extension region (113) extended in a thin line shape so as to overlap with the edges (131a) and (131b) along the signal line (110). The pixel electrode (131) and the scanning line (11
As shown in FIG. 7, the first gate insulating film (115) and the second gate insulating film overlap with the extended region (113) from the scanning line (111) in the previous stage. (117) and interlayer insulating film
(127), and the overlapping area (OS)
Form an auxiliary capacitance (Cs). Further, in this embodiment, the pixel electrode (131) and the previous scanning line (111) are mutually connected via the first gate insulating film (115), the second gate insulating film (117) and the interlayer insulating film (127). The storage capacity (Cs) is also formed in the overlapping area.

Then, as shown in FIG. 3, the signal line (110)
On the upper surface of the drain electrode (126a) provided continuously with
A protective film (131c) made of the same material as the pixel electrode (131) is provided via an interlayer insulating film (127).

An opposing substrate opposing the array substrate (100)
(200) is placed on a glass substrate (201) and a TFT (12
1) Region, signal line (110) and scanning line (111) and pixel electrode (13
1) Matrix-shaped resinous light-shielding film that shields the gap with
(211). Also, red (R), green (G), and blue (B) color filters (221) are disposed in regions corresponding to the pixel electrodes (131), respectively, and a counter electrode (transparent electrode material) is formed thereon. 231) are arranged and configured.

As described above, according to the array substrate (100) of the liquid crystal display device (1), the signal lines (110) and the scanning lines (11) are provided.
1) and the pixel electrode (131), an interlayer insulating film (127),
Alternatively, since the first and second gate insulating films (115) and (117) and the interlayer insulating film (127) are respectively disposed, the pixel electrode (131) is sufficiently connected to the wirings (110) and (111). Can be arranged close to or superimposed on the device, thereby realizing a high aperture ratio.

According to this embodiment, the auxiliary capacitance (C
s) is formed between the pixel electrode (131) and the extension region (113) extending from the scanning line (111) adjacent to the pixel electrode (131). There is no need to arrange them, and a higher aperture ratio can be achieved. In particular, in this embodiment, the TFT (112) is connected from the scanning line (111) to the signal line (110).
Is formed as a gate electrode, the pixel electrode (131) can also be superimposed on the previous scanning line (111) itself. As a result, a sufficient auxiliary capacitance (Cs) is secured and the aperture ratio is increased.

Between the pixel electrode (131) and the scanning line (111) and the extension region (113), three types of insulating films (115), (1)
Since the layers (17) and (127) are stacked, the occurrence of interlayer short-circuiting and the like due to the structure of the present embodiment is extremely reduced.

In this embodiment, the pixel area is
The scanning line (111) and its extended area (113) on the array substrate (100), not the light-shielding film (211) arranged on the opposite substrate (200)
Defined by Therefore, regardless of the alignment accuracy between the array substrate (100) and the counter substrate (200), the first mask pattern for patterning the scanning lines (111) and the pixel electrodes (131) are used.
Is determined only by the accuracy of alignment with the fifth mask pattern for patterning the light-shielding film (211) in consideration of misalignment between the array substrate (100) and the counter substrate (200).
Since there is no need to provide a margin for the width, it is possible to achieve a higher aperture ratio.

Further, a scanning line is used to define a pixel area.
The extension region (113) of (111) is connected to the signal line (11) of the pixel electrode (131).
0), the pixel electrode (131) and the scanning line (11) can be extended sufficiently along the edges (132) and (133).
A first gate insulating film (115) is provided between the first gate insulating film (115) and the extension region (113) of (1).
And an interlayer insulating film (127) in addition to the second gate insulating film (117)
Are arranged, it is possible to suppress a large increase in the auxiliary capacity (Cs) without impairing productivity.

As shown in FIG. 6, the outline of the signal line (110) matches the outline of the low-resistance semiconductor film (124a) and the semiconductor film (120). More specifically, at the intersection of the signal line (110) and the scanning line (111), in addition to the first and second gate insulating films (115) and (117), a low-resistance semiconductor film (124a) and a semiconductor A membrane (120) is laminated. Therefore, even if a mask shift occurs during each patterning, the signal line (110) and the scanning line
There is no variation in capacitance between the product and (111), so that variation in scanning line capacitance or signal line capacitance between products is reduced. Also,
Static electricity at the intersection of the signal line (110) and the scanning line (111), dust during the process, or each insulating film (115), (11
7) Inter-layer shorts caused by pinholes are also suppressed,
As a result, a high production yield can be secured.

Further, as shown in FIG. 7, the signal line (110)
Since the contour of the low-resistance semiconductor film (124a) and the contour of the semiconductor film (120) coincide with each other, even if a mask shift occurs in each patterning, a signal Capacitance fluctuation occurring between the line (110) and the extension area (113) of the scanning line (111) can be sufficiently suppressed.

Further, the signal line (110) and the extension region (113) of the scanning line (111) are superposed, that is, in FIG. 7, the extension region (113) disposed adjacent to the signal line (111) via the signal line (111). ) To the signal line (11
1) Even when the structure is connected below, each insulating film (11) is provided between the signal line (110) and the extension region (113) of the scanning line (111).
Since the semiconductor film (120) is always arranged in addition to (5) and (117), static electricity, dust during the process, or each insulating film (1
Interlayer shorts caused by the pinholes of (15) and (117) are also suppressed, and a high production yield can be secured. And the pixel electrode (131) adjacent to the signal line (111) is thus
With the configuration in which the extension region (113) is arranged below, the signal line (111)
The capacitive coupling between the pixel electrode (131) and the pixel electrode (131) is shielded by the extension region (113), and the potential of the pixel electrode (131) is changed to the signal line (1).
11) can reduce the effect of the potential. Moreover,
The outline of the semiconductor film (120) and the low-resistance semiconductor film (124a) disposed between the signal line (111) and the insulating films (115) and (117) match the outline of the signal line (111). ing. For these reasons, the signal line (111) and the pixel electrode (131) can be arranged sufficiently close to each other, thereby achieving a higher aperture ratio.

(Structure near the outer periphery of the scanning line)
The structure near the outer periphery of 1) will be described with reference to FIGS.

The scanning line (111) made of an Al-Y alloy is drawn out to one end side (101a) of the glass substrate (101), and the lower layer wiring (150) and the lower layer wiring (152) guided to the scanning line pad (152). A part (111a) is formed.

In the oblique wiring section (150), the scanning lines (11
Two layers of insulating films (115) and (117) are laminated on the lower wiring portion (111a) extending from (1). Further, on the two insulating films (115) and (117), Al-Y, which is the same material as the semiconductor film (119), the low-resistance semiconductor film (123) and the signal line (110) in the same process, is used. Upper layer wiring section made of alloy film (125a)
Are stacked, and an interlayer insulating film is formed on the upper wiring portion (125a).
(127) are arranged. On the upper surface of this interlayer insulating film (127), a protective film (131) made of the same material as the pixel electrode (131) is formed.
a) is provided.

At the base of the oblique wiring portion (150), a pair of first contact holes (153) and second
The contact holes (154) are arranged close to each other along the wiring direction, and the scanning lines (1) are formed by the protective film (131a) made of ITO of the same material in the same process as the pixel electrodes (131).
11) and the upper wiring section (125a) extending from the lower wiring section (111a).
a) are electrically connected via a first contact hole (153) and a second contact hole (154). This protective film (131a) is provided continuously with the protective film provided on the upper surface of the oblique wiring portion (150).

The second contact hole (154) is formed of a two-layer insulating film so as to expose a part of the main surface of the lower wiring portion (111a).
(115), (117), semiconductor coating (119), low-resistance semiconductor coating (1
23) and an opening penetrating the upper wiring portion (125a), and the first contact hole (153) penetrates the interlayer insulating film (127) so as to expose a part of the main surface of the upper wiring portion (125a). Opening.

Further, in the scanning line pad (152), a pair of first contact holes (155) and second contact holes (156) are also arranged close to each other along the wiring direction, and a pixel electrode (152) is formed. The scanning line (111) is formed by the protective film (131a) made of ITO of the same material in the same process as 131).
The lower wiring portion (111a) and the upper wiring portion (125a) are electrically connected via a first contact hole (155) and a second contact hole (156). This protective film (131a) is provided continuously with the protective film (131a) provided on the oblique wiring portion (150).

The second contact hole (156) is formed in the lower wiring portion (111) in the same manner as the above-described second contact hole (154).
a) a two-layer insulating film (115), exposing a part of the main surface of
(117), an opening penetrating the semiconductor film (119), the low-resistance semiconductor film (123), and the upper wiring portion (125a), wherein the first contact hole (155) is the first contact hole (15).
Similarly to 3), the opening penetrates the interlayer insulating film (127) so as to expose a part of the main surface of the upper wiring portion (125a).

Thus, the oblique wiring portion (1) of the scanning line (111) is
50) are signal lines (11
0) and an upper wiring portion (125a) made of the same material and formed in the same step as the Al-Y alloy film, and a lower wiring portion (111a) extending from the scanning line (111) made of the Al-Y alloy film. These two layers electrically connect the base of the oblique wiring portion (150) and the scanning line pad (152).

For this reason, in the oblique wiring section (150), even if one of the upper wiring section (125a) or the lower wiring section (111a) is disconnected, the other is connected. Disconnection failure is greatly reduced.

Further, the oblique wiring portion (150),
The base of (150) and the upper surface of the scanning line pad (152) are the protective film (1).
31a), even if the interlayer insulating film (12
7) Even if a pinhole or the like is present, the upper wiring portion (125a) below it is not corroded in the manufacturing process.

In this embodiment, in the region of the second contact hole (156), ie, the lower wiring portion (111a) and the protective film (131).
The laminated region with a) mainly functions as a connection region for the scanning line pad (152).

(Structure near the outer periphery of the signal line)
0) will be described with reference to FIGS. 1 and 5.

A lower wiring portion (111b) made of an Al-Y alloy film made of the same material and in the same step as the scanning line (111) is provided on one side of the glass substrate (101) corresponding to each signal line (110). 101b) side signal line (110) diagonal wiring part (160) and signal line pad (1
62).

In the oblique wiring portion (160), the lower wiring portion
On the (111b), two insulating films (115) and (117) are arranged. In addition, on these two insulating films (115) and (117),
Semiconductor coating (119), low resistance semiconductor coating (123) and signal line
An upper wiring portion (125b) (signal line (110)) made of an Al-Y alloy film extending from (110) is laminated, and the upper wiring portion is formed.
An interlayer insulating film (127) is disposed on (125b). Further, a protective film (131b) made of the same material as that of the pixel electrode (131) is formed on the interlayer insulating film (127).

At the base of the oblique wiring portion (160), a pair of the first contact hole (163) and the second
The contact holes (164) are arranged close to each other along the wiring direction, and the signal lines (1b) are formed by the protective film (131b) made of ITO of the same material in the same process as the pixel electrodes (131).
10) and the lower wiring section (111b) extending from the upper wiring section (125b).
b) are electrically connected. Then, this protective film (1
31b) is a protective film (1) provided on the upper surface of the oblique wiring portion (160).
31b).

The second contact hole (164) has two layers of insulating films (115) and (117), a semiconductor film (119) and a semiconductor film (119) so as to expose a part of the main surface of the lower wiring portion (111b). An opening penetrating the low-resistance semiconductor film (123) and the upper wiring portion (125b), the first contact hole (163) is an interlayer insulating film so as to expose a part of the main surface of the upper wiring portion (125b). (127).

In the signal line pad (162), a pair of first contact holes (165) and second contact holes (166) are also arranged in the wiring direction, respectively, and a pair of pixel electrodes (131) is formed. I, which is the same material in the same process as
The upper wiring portion (125b) extending from the signal line (110) and the lower wiring portion (111b) are electrically connected by a protective film (131b) made of TO. The protective film (131b) is provided continuously with the protective film (131b) provided on the upper surface of the oblique wiring portion (160).

The second contact hole (166) is, like the second contact hole (164) described above, a two-layer insulating film so as to expose a part of the main surface of the lower wiring portion (111b).
(115), (117), semiconductor coating (119), low-resistance semiconductor coating (1
23) and an opening penetrating the upper wiring portion (125b), and the first contact hole (165) forms a part of the main surface of the upper wiring portion (125b) similarly to the above-mentioned second contact hole (163). The opening penetrates the interlayer insulating film (127) so as to be exposed.

Thus, in the oblique wiring portion (160), the same material as the upper wiring portion (125b) extending from the signal line (110) made of an Al—Y alloy film and the scanning line (111) in the same step. And a lower wiring portion (111b) made of an Al—Y alloy film. The two layers electrically connect the base of the oblique wiring portion (160) and the signal line pad (162).

Therefore, in the oblique wiring portion (160), A
Upper wiring portion (125b) made of l-Y alloy film or Al-Y
Even if one of the lower wiring portions (111b) made of an alloy film is disconnected,
Since the other is connected, the occurrence of disconnection failure in the oblique wiring portion (160) is reduced.

Further, the oblique wiring portion (160), the base of the oblique wiring portion (160) and the upper surface of the signal line pad (162) are covered with a protective film (131b) made of the same material as the pixel electrode (131). Therefore, even if a pinhole or the like exists in the interlayer insulating film (127), the upper layer wiring portion (125b)
Is not corroded in the manufacturing process.

As shown in FIG. 3, on the upper surface of the drain electrode (126a) provided continuously with the signal line (110), the same as the pixel electrode (131) via the interlayer insulating film (127). A protective film (131c) made of a material is provided.

In this embodiment, in the region of the second contact hole (166), that is, the lower wiring portion (111b) and the protective film (131)
The laminated region with b) mainly functions as a connection region for the signal line pad (162).

According to the above-described structure, the bumps of the drive IC, the electrodes of the FPC (flexible print circuit) and the TCP (tape carrier package) are connected to the signal line pad (162) and the scanning line pad (152). When electrically connected via a connection layer such as an ACF (anisotropic conductive film), the signal line pad (162) and the scanning line pad (152) have substantially the same configuration. Even when the connection conditions of the (162) and the scanning line pad (152) are made equal, the heat, pressure and the like applied to the connection layer can be made substantially equal, thereby enabling manufacture under the same conditions. That is, in this embodiment, the connection region of the scanning line pad (152) is mainly formed by the lower wiring portion (111a) made of an Al-Y alloy film derived from the scanning line (111).
And a protective film (131b) made of the same material as the pixel electrode (131). The connection region of the signal line connection pad (162) is formed mainly at the same time as the scanning line (111). Protective film made of ITO which is the same material as the lower wiring portion (111b) made of Al-Y alloy film and the pixel electrode (131)
(131b), and the structure is substantially the same.

(Manufacturing Process of Array Substrate) Next, the manufacturing process of the array substrate (100) will be described in detail with reference to FIGS.

(1) First Step As shown in FIG. 8, an Al—Y alloy film and a Mo film each having a thickness of 200 nm were formed on a glass substrate (101) by sputtering.
Deposited continuously with a thickness of 30 nm, exposed using a first mask pattern, developed and patterned (first patterning).

As a result, 480 pieces are placed on the glass substrate (101).
A scan line (111) is made and one end (101a)
On the side, the oblique wiring part (150) of the scanning line (111) and the lower wiring part (111a) forming the scanning line pad (152), one end side (101
In b), the oblique wiring portion (160) of the signal line (110) and the lower wiring portion (111b) constituting the signal line pad (162) are simultaneously produced.

Further, in the TFT region, a gate electrode is formed which is integrated with the scanning line (111) and is led out in a direction orthogonal to the scanning line (111). In addition, an extension region (113), which is derived in a direction perpendicular to the scanning line (111) when patterning the scanning line (111) and forms an auxiliary capacitance (Cs), is also prepared at the same time (FIG. 1). reference).

(2) Second Step After the first step, as shown in FIG. 8, a first gate insulating film (115) made of a silicon oxide film having a thickness of 150 nm is deposited by a plasma CVD method, and then a further 150 nm thickness is formed. Gate insulating film (117) made of a silicon nitride film of
Thick a-Si: H semiconductor coating (119) and 200
channel protective film (12 nm thick silicon nitride film)
1) is deposited without continuously exposing it to the atmosphere.

(3) Third Step After the second step, as shown in FIG. 10, the channel protective film (121) is self-aligned with the scanning line (111) by the backside exposure technique using the scanning line (111) as a mask. Is patterned using a second mask pattern so as to correspond to the TFT region, developed, and patterned (second patterning) to form an island-shaped channel protective film (122).

(4) Fourth Step After the third step, as shown in FIG. 11, a semiconductor film (119) exposed so as to obtain a good ohmic contact.
The surface is treated with a hydrofluoric acid (HF) -based solution, and a 30 nm-thick n + a-S
A low resistance semiconductor film (123) made of i: H is deposited, and a 300 nm thick Mo-W alloy film (125) is further deposited by sputtering.

(5) Fifth Step After the fourth step, as shown in FIG. 12, exposure and development are performed using a third mask pattern to form an Al—Y alloy film (125) and a low-resistance semiconductor film (123). ) And the semiconductor film (119) are collectively controlled by controlling the etching selectivity between the first gate insulating film (115) or the second gate insulating film (117) made of a silicon nitride film and the channel protective film (122). To perform patterning by plasma etching (third patterning).

Thus, in the TFT region, the resistive semiconductor film (124a) and the source electrode (126b) are integrally formed,
A drain electrode (126a) is formed integrally with the low resistance semiconductor film (124b) and the signal line (110).

Scan line pad (152) and diagonal wiring part (150)
At the base of the lower layer wiring portion (111a),
Y-alloy film (125) is patterned and the upper wiring (125a)
And the low-resistance semiconductor film (123) and the semiconductor film (119) are collectively patterned along the upper wiring portion (125a). At the same time, an opening penetrating the upper wiring portion (125a), the low-resistance semiconductor film (123), and the semiconductor film (119) corresponding to the above-mentioned second contact holes (154) and (156).
(154a) and (156a) are prepared.

Similarly, at the base of the signal line pad (162) and the oblique wiring portion (160), the Al-Y alloy film (125) is patterned along the lower wiring portion (111b) to form the signal line (11).
0), and a low-resistance semiconductor film (123) is formed along the upper wiring portion (125b).
Then, the semiconductor film (119) is collectively patterned. At the same time, the second contact holes (164), (16)
6), an opening (164) penetrating through the upper wiring portion (125b), the low-resistance semiconductor film (123), and the semiconductor film (119).
a) and (166a) are prepared.

Here, the Al-Y alloy film (125), the low-resistance semiconductor film (123) and the semiconductor film (119) are patterned by dry etching, but may be wet-etched.

(6) Sixth Step After the fifth step, an interlayer insulating film (127) made of a silicon nitride film having a thickness of 200 nm is deposited thereon by thermal CVD.

Then, as shown in FIG. 13, exposure and development are performed using a fourth mask pattern, and a part of the interlayer insulating film (127) corresponding to the source electrode (126b) is removed and dry etching is performed. Thereby, a contact hole (129a) is formed.

The scanning line pad (152) and the oblique wiring portion (150)
At the base of the first (154a), (156a)
At the same time as removing the interlayer insulating film (127) together with the second gate insulating film (117) to form the second contact holes (154) and (156) (fourth patterning), the second contact hole is formed. By removing the interlayer insulating film (127) near (154) and (156), first contact holes (153) and (155) forming a pair with the second contact holes (154) and (156) are formed.

At the same time, at the base of the signal line pad (162) and the oblique wiring portion (160), the interlayer insulating film is formed together with the first and second gate insulating films (117) corresponding to the openings (164a) and (166a).
(127) are collectively removed to form a second contact hole (164),
At the same time as forming (166), the second contact hole (16
4), the interlayer insulating film (127) in the vicinity of (166) is removed to form first contact holes (163) and (165), which make a pair with the second contact holes (164) and (166), respectively.

(7) Seventh Step After the sixth step, as shown in FIG.
An m-thick ITO film is deposited by sputtering, and is exposed and developed using a fifth mask pattern, and an etching gas containing hydrogen iodide (HI) as a main component, ie, HI gas or H
Patterning (fifth patterning) is performed by dry etching with an I / Ar gas to produce a pixel electrode (131).

The scanning line pad (152) and the oblique wiring portion (150)
At the base of the first contact holes (153), (155)
And the second contact holes (154) and (156) are formed with a protective film (131a) for electrical connection, whereby the scanning line (111) and the scanning line pad (152) are connected to the lower layer. Wiring section
(111a) and the upper layer wiring section (125a).
0) are electrically connected.

In the signal line pad (162), the base of the oblique wiring portion (160) and the signal line (110), the first contact holes (163) and (165) and the second contact holes (164) and (166) Are simultaneously formed with a protective film (131b) for electrical connection, respectively, whereby the signal line (110) and the signal line connection pad (162) are connected to the lower wiring portion (111b) and the upper wiring portion (131b). It is electrically connected by a diagonal wiring portion (160) having a two-layer structure of 125b).

Further, a protective film (131c) is provided on the upper surface of the drain electrode (126a) so as to cover the drain electrode (126a).

In this step, the signal line pad
(162), diagonal wiring part (160), upper surface of signal line (110) and scanning line pad (152), diagonal wiring part (150) and drain electrode
Since the protective films (131a), (131b), and (131c) made of the same material as the pixel electrode (131) are provided so as to cover the upper surface of (126a), there is no pinhole or the like in the interlayer insulating film (127). Even IT
They are not corroded by residual hydroiodic acid due to dry etching of the O film.

In the case where the protective films (131a), (131b), and (131c) are provided, the number of manufacturing steps does not need to be increased because they can be laminated simultaneously with the pixel electrode (131).

(Modification) In this embodiment, the semiconductor film is a
Although the description has been given of the case where the semiconductor device is made of -Si: H, it is needless to say that a polysilicon film or the like may be used. Further, the drive circuit portion may be integrally formed in the peripheral region.

Further, when the pixel electrodes are partially overlapped with each other on the signal lines and the scanning lines, a shield electrode is arranged between at least the pixel electrodes and the signal lines with a metal film or the like via an insulating layer. Then, the pixel electrode can reduce the influence of the potential from the signal line.

As the liquid crystal layer, various materials such as polymer dispersed liquid crystal, ferroelectric liquid crystal, and antiferroelectric liquid crystal can be applied in addition to the TN liquid crystal.

In this embodiment, the signal line pad (162), the oblique wiring portion (160), the upper surface of the signal line (110) and the scanning line pad
(152) and protective films (131a) (131b) (131c) made of the same material as the pixel electrode (131) are provided so as to cover the upper surfaces of the oblique wiring portion (150) and the drain electrode (126a). It is not necessary to provide protective films (131a), (131b), and (131c) in all areas.For example, diagonal wiring sections (150) and (160) that are susceptible to disconnection, etc. It may be arranged selectively on the upper surface of the pad (152) or the signal line pad (162).

In this embodiment, the protective films (131a) and (131a)
b) Although (131c) is made of ITO, which is the same material as the pixel electrode (131), the present invention is not limited to this ITO, and a sufficiently dense film such as a silicon oxide film or a silicon nitride film may be used. An insulating film can also be used.

In this embodiment, a thin film transistor having an inverted staggered structure is described as an example. However, an array substrate for a display device using a thin film transistor having a staggered structure may be used. In this case, the scanning lines, the scanning line pads, the oblique wiring portions, and the like may be covered with a protective film.

[0081]

As described above, according to the method of manufacturing an array substrate for a display device of the present invention, the source electrode, the drain electrode or the signal line is not exposed to the etching gas.
High productivity can be ensured without being corroded by, for example, hydroiodic acid when dry etching is performed, and without lowering the production yield.

[Brief description of the drawings]

FIG. 1 is a partial schematic plan view of an array substrate according to an embodiment of the present invention.

FIG. 2 is a plan view of a portion covered with the same material as a pixel electrode in FIG.

FIG. 3 is a schematic cross-sectional view of the liquid crystal display device taken along line AA ′ of FIG.

FIG. 4 is a schematic cross-sectional view of the liquid crystal display device taken along the line BB ′ of FIG.

FIG. 5 is a schematic cross-sectional view of the liquid crystal display device taken along line CC ′ of FIG. 1;

FIG. 6 is a schematic cross-sectional view of the liquid crystal display device taken along line DD ′ of FIG. 1;

FIG. 7 is a schematic cross-sectional view of the liquid crystal display device taken along the line EE ′ of FIG. 1;

FIG. 8 is a view illustrating a first step of manufacturing the array substrate of FIG. 1;

FIG. 9 is a view illustrating a second step of manufacturing the array substrate of FIG. 1;

FIG. 10 is a view illustrating a third step of manufacturing the array substrate of FIG. 1;

FIG. 11 is a view illustrating a fourth step of manufacturing the array substrate of FIG. 1;

FIG. 12 is a view illustrating a fifth step of manufacturing the array substrate of FIG. 1;

FIG. 13 is a view illustrating a sixth step of manufacturing the array substrate of FIG. 1;

FIG. 14 is a view illustrating a seventh step of manufacturing the array substrate of FIG. 1;

[Explanation of symbols]

 110 signal line 111 scanning line 112 thin film transistor 113 extension region 115 first insulating film 117 first insulating film 120 semiconductor film 126a drain electrode 126b source electrode 131 pixel electrode

Claims (5)

[Claims] A scanning line disposed on the substrate; a first insulating film disposed thereon; a semiconductor film disposed on the insulating film; and a source electrically connected to the semiconductor film. A thin film transistor including an electrode and a drain electrode; a signal line derived from the drain electrode and substantially orthogonal to the scanning line; and a pixel electrode electrically connected to the source electrode. In the manufacturing method, when the electrode thin film is patterned by dry etching to form the pixel electrode, the source electrode, the drain electrode or the signal line is not exposed to an etching gas. Production method. 2. The method according to claim 1, wherein the source electrode, the drain electrode, or the signal line is covered with the electrode thin film or the protective film during the patterning. . 3. The method according to claim 1, wherein the source electrode, the drain electrode, or the signal line comprises
3. The method of manufacturing an array substrate for a display device according to claim 2, wherein said electrode thin film is made of TO and said etching gas is mainly hydrogen iodide. 4. The method according to claim 2, wherein the wiring covered with the electrode thin film or the protective film is mainly made of aluminum. 5. A thin film transistor disposed on a substrate,
A method for manufacturing an array substrate for a display device, comprising: a signal line electrically connected to a drain electrode of the thin film transistor; a pixel electrode electrically connected to a source electrode; and a scanning line forming a gate electrode. Is formed by patterning an electrode thin film by dry etching, the drain electrode, the source electrode, the signal line or the scanning line are covered with the electrode thin film so as not to be exposed to an etching gas. A method for manufacturing an array substrate for a display device, comprising: