JPH10253669A - Voltage detection circuit and electronic equipment - Google Patents

Abstract

(57) [Problem] To provide a voltage detection circuit and an electronic device capable of reducing a lower limit of an operation voltage and obtaining a stable output even when noise is superimposed on an input voltage. SOLUTION: A voltage detection section 100 changes an output VP from an H level to an L level when an input voltage VDD becomes a detection voltage VDET. The output holding unit 200 is configured by a logic circuit whose operating voltage lower limit is lower than that of the voltage detection unit 100. When the output VP of the voltage detector 100 changes from the H level to the L level, the output VO is set to the H level.
Level to L level and output VO
Hold on level. As a result, the lower limit of the operating voltage can be reduced. A voltage monitoring unit that monitors the output VP and transmits a change in the VP from the H level to the L level to the output holding unit 200 when a predetermined period has elapsed since the output VP became the L level may be provided. In this way, a stable output VO can be obtained even when noise is superimposed on VDD.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a voltage detection circuit and an electronic device using the same.

[0002]

2. Description of the Related Art FIG. 14 shows an example of a conventional voltage detection circuit. In FIG. 14, VREG obtained by dividing the input voltage (power supply voltage) VDD by the resistors R1 and R2 is input to the negative terminal of an operational amplifier (operational amplifier) 900 functioning as a comparator. The positive terminal of the operational amplifier 900 has a reference voltage source 9.
01 is input and the operational amplifier 90
The output of 0 is buffered by an output unit 906 comprising a P-type transistor 902 and an N-type transistor 904.

In this voltage detection circuit, when VDD becomes a detection voltage VDET = VREF × (R1 + R2) / R2, an output VO changes from a high-level voltage (hereinafter abbreviated as H-level) to a low-level voltage (hereinafter L-level). Level). As a result, the input voltage VDD becomes the detection voltage VDE
It can be detected whether or not T has been reached.

However, it has been found that the conventional voltage detection circuit has the following problems.

The first problem is related to the lower limit of the operating voltage of the circuit. The operating voltage lower limit of the circuit in FIG. 14 depends on the operating voltage lower limit of the operational amplifier 900 which is an analog circuit. The maximum values of the absolute values of the threshold voltages of the P-type and N-type transistors are | VTHPmax | and | VT, respectively.
When HNmax |, the lower limit of the operating voltage of the operational amplifier 900 is approximately | VTHPmax | + | VTHNmax |.
Therefore, the operating voltage lower limit VOPmin of the entire circuit of FIG.
VTHPmax | + | VTHNmax | For example |
When VTHPmax | = | VTHNmax | = 0.8 V, the operating voltage lower limit VOPmin is about 1.6 V. In an electronic device such as a mobile phone or a portable information device, a power supply voltage is usually supplied using a storage battery, and the voltage of the storage battery decreases with time. Therefore, the input voltage (power supply voltage) VDD may be lower than the above 1.6 V, and in this case, the normal operation of the circuit cannot be guaranteed by the conventional voltage detection circuit. That is, when VDD becomes lower than the operating voltage lower limit VOPmin = 1.6 V,
The output of the operational amplifier 900 becomes unstable, and the output VO of the voltage detection circuit also becomes unstable. For this reason, the normal operation of the circuit that performs various processes using the output VO of the voltage detection circuit cannot be guaranteed.

The second problem relates to noise superimposed on VDD. In the circuit of FIG. 14, when noise generated inside or outside the device or noise caused by power supply voltage fluctuation due to a load fluctuation inside the device is superimposed on VDD, V
When the voltage of the DD drops below the detection voltage due to the noise for a certain period (a period longer than the response time of the voltage detection circuit), the voltage of the VDD supplied from the storage battery or the like has not actually fallen below the detection voltage yet. Nevertheless, the output V
O changes. As a result, normal operation of a circuit that performs various processes using the output VO is prevented.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a voltage detection circuit capable of reducing the lower limit of the operating voltage and an electronic device using the same. .

It is another object of the present invention to provide a voltage detection circuit capable of obtaining a stable output even when noise is superimposed on an input voltage, and an electronic device using the same.

[0009]

According to the present invention, there is provided a voltage detecting circuit for detecting whether or not an input voltage has reached a given detection voltage. Voltage detection means for changing an output from a first voltage, which is one of a high level voltage and a low level voltage, to a second voltage, which is the other voltage, when the detection voltage is reached, When the output of the voltage detecting means changes from the first voltage to the second voltage,
The output is changed from a third voltage, which is one of the high-level voltage and the low-level voltage, to a fourth voltage, which is the other voltage, and the fourth voltage is held. Output holding means for outputting a voltage.

According to the present invention, when the input voltage becomes the detection voltage, the output of the voltage detection means changes, for example, from H level (high level voltage) to L level (low level voltage) (from L level to H level). Level.) Then, the output of the output holding means changes, for example, from the H level to the L level (or may be changed from the L level to the H level), and the output holding means holds and outputs the changed output level, for example, the L level. Keep doing. Here, the output holding means has an operating voltage lower limit lower than the operating voltage lower limit of the voltage detecting means. Therefore, even when the power supply voltage becomes lower than the lower limit of the operating voltage of the voltage detecting means and the output of the voltage detecting means becomes unstable, the output holding means operates normally and keeps the output level. As a result, the output of the voltage detection circuit does not become unstable, and the lower limit of the operating voltage of the entire voltage detection circuit can be reduced.

Further, according to the present invention, the voltage detecting means includes an operational amplifier having an operating voltage lower limit than a logic circuit,
The output holding unit initializes a holding voltage to the third voltage based on a given initialization signal, and the output holding unit changes the output from the first voltage to the second voltage when the output of the voltage detection unit changes from the first voltage to the second voltage. A flip-flop circuit holding a fourth voltage is included. The operating voltage lower limit of the operational amplifier is generally higher than the operating voltage lower limit of the logic circuit. In the conventional configuration, the lower limit of the operating voltage of the entire voltage detection circuit is equal to the lower limit of the operating voltage of the operational amplifier. On the other hand, according to the present invention, the operating voltage lower limit of the entire voltage detection circuit can be made lower than the operating voltage lower limit of the operational amplifier circuit. Note that various types of flip-flop circuits such as an RS flip-flop circuit and a D flip-flop circuit can be considered as the flip-flop circuit included in the output holding unit. The initialization signal is preferably one that can initialize the flip-flop circuit when the power supply voltage is turned on, for example, but is not limited to this.

Further, the present invention is characterized in that it includes a power-on detecting circuit for detecting that the power is turned on and outputting the initialization signal. By doing so, the voltage held in the flip-flop circuit can be initialized to the third voltage when the power is turned on.

It is preferable that the input voltage is a voltage based on the voltage of the power supply.

Further, the present invention monitors the output of the voltage detecting means, and when the period during which the output of the voltage detecting means is at the second voltage is longer than a given period, the output of the first voltage is detected. A voltage monitoring means for transmitting a change in the output of the voltage detection means to the second voltage to the output holding means is included. With this configuration, if the period during which the output of the voltage detecting means is the second voltage is shorter than the given period, the output change of the voltage detecting means is not transmitted to the output holding means, and If longer, it will be reported. Then, when the output change of the voltage detecting means is transmitted to the output holding means, the output holding means changes the output from the third voltage to the fourth voltage and holds the fourth voltage. As a result, the lower limit of the operating voltage can be reduced, and the noise resistance can be improved.

Further, according to the present invention, when the voltage monitoring means outputs the second voltage, the voltage monitoring means outputs the second voltage.
Changing the count value based on a given clock signal,
A counter circuit is provided for transmitting a change in the output of the voltage detecting means to the output holding means when the count value has reached a given value. When the given period is measured using the counter circuit in this way, the given period can be measured more accurately, and the circuit can be prevented from increasing in scale.

Further, according to the present invention, the voltage monitoring means has a capacitive element and a resistive element for charging and discharging the capacitive element, and a period during which the output of the voltage detecting means is the second voltage is provided. A circuit for transmitting a change in the output of the voltage detection means to the output holding means when the time is longer than a given period is provided. This eliminates the need for a clock signal, which is required when providing a count circuit, for example.

Further, the present invention is a voltage detection circuit for detecting whether or not an input voltage has reached a given detection voltage, wherein when the input voltage has reached the given detection voltage, a high level voltage and a high level voltage are detected. Voltage detecting means for changing the output from the first voltage, which is one of the low-level voltages, to the second voltage, which is the other voltage; and monitoring the output of the voltage detecting means. When the period during which the output becomes the second voltage is longer than a given period, the third voltage, which is one of the high-level voltage and the low-level voltage, to the fourth voltage, which is the other voltage And voltage monitoring means for changing the output.

According to the present invention, the output of the voltage monitoring means (the output of the voltage detection circuit) changes from the third voltage as long as the period during which the output of the voltage detection means is at the second voltage does not exceed a predetermined period. It does not change to the fourth voltage. Therefore, the noise resistance characteristics of the voltage detection circuit can be remarkably improved.

Further, according to the present invention, when the voltage monitoring means outputs the second voltage, the voltage monitoring means outputs the second voltage.
Changing the count value based on a given clock signal,
A counter circuit for changing the output from the third voltage to the fourth voltage when the count value reaches a given value is included. In this way, accurate measurement in a given period and downsizing of the circuit can be achieved.

Further, according to the present invention, when the output of the voltage detecting means is the first voltage,
It is characterized in that the count value is initialized. With this configuration, for example, when the output of the voltage detecting means changes to the first voltage while the output of the voltage detecting means changes to the second voltage and the count value changes, the count value is initialized. . Thus, the count value can be changed again from the initial value.

Further, according to the present invention, the voltage monitoring means has a capacitive element and a resistive element for charging and discharging the capacitive element, and a period in which the output of the voltage detecting means is the second voltage is provided. A circuit for changing an output from the third voltage to the fourth voltage when the time is longer than a given period is included. This eliminates the need for a clock signal, which is required when providing a count circuit, for example.

The electronic apparatus according to the present invention, further comprising: a power supply unit for supplying a power supply voltage; a voltage detection circuit for detecting a power supply voltage from the power supply unit; A display unit for displaying a detection result of the circuit. In this way, in electronic devices such as a mobile phone, a personal computer, a pager, and an electronic device, for example, it is possible to detect a drop in the power supply voltage and display the detection result on the display unit, and to reduce the lower limit of the operating voltage of the electronic device. And noise resistance can be improved.

The present invention also provides a power supply unit for supplying a power supply voltage, a clock generation unit for generating a clock signal, a timer unit for performing a timer process based on the clock signal from the clock generation unit, and a timer unit. And a processing unit that performs a given process based on the output of the electronic device. The power supply voltage from the power supply unit is detected, and a clock signal from the clock generation unit is input as the given clock signal. And a voltage detection circuit according to any one of items 6, 9 and 10. With this configuration, it is possible to detect whether or not the period during which the output of the voltage detection unit is at the second voltage is longer than a given period, using the clock signal that the electronic device originally has,
Effective use of clock signals can be achieved

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 shows an example of a circuit diagram of a voltage detection circuit of Embodiment 1. This voltage detection circuit includes a voltage detection unit 100 and an output holding unit 200.

When the input voltage VDD becomes the detection voltage VDET, the voltage detection unit 100 outputs the output VP to H, for example.
The level is changed from the level (first voltage) to the L level (second voltage) (the level may be changed from the L level to the H level). The output holding unit 200 is configured by a logic circuit having an operation voltage lower limit lower than the operation voltage lower limit of the voltage detection unit 100. Then, when the output of the voltage detection unit 100 changes from the H level to the L level, the output VO is changed from the H level (third voltage) to the L level (fourth voltage) (from the L level to the H level). May be changed). Then, the L level (fourth voltage) after this change is held,
Regardless of the subsequent change in the output VP of the voltage detection unit 100, the held L level is continuously output as VO.

Next, a specific configuration example of this embodiment will be described.

The voltage detector 100 includes resistors R1 and R2, an operational amplifier 110, and a reference voltage source 112. Then, VREG obtained by dividing the input voltage (power supply voltage) VDD by the resistors R1 and R2 is input to the positive terminal of the operational amplifier 110 functioning as a comparator, and the reference voltage VRE
F is input to the negative terminal of the operational amplifier 110.

The output holding section 200 includes a flip-flop circuit 210 and an output section 220 including a P-type transistor 216 and an N-type transistor 218. In FIG.
The flip-flop circuit 210 includes NANDs 212 and 21
4 is included in the RS flip-flop circuit.

A power-on reset circuit (power-on detection circuit) 90 is connected to the R terminal of the flip-flop circuit 210.
Is input. The power-on reset circuit 90 detects that the power has been turned on, and outputs a PWR signal as an initialization signal. That is, the power-on reset circuit 90 includes a resistor R3 and a capacitor C, and becomes a PWR which becomes L level only for a given period after power-on.
Output a signal. On the other hand, the output VP of the voltage detector 100 is input to the S terminal of the flip-flop circuit 210.
When the PWR signal (R terminal) goes low, VF2 goes high. At this time, if VP is at H level, VF1 is at L level.
Become a level. That is, the flip-flop circuit 210 is reset. When VP (S terminal) goes low in this state, VF1 goes high. That is, the flip-flop circuit 210 is set. Once in the set state, VF1 is held at H level and VO is held at L level regardless of the level of VP, unless the PWR signal goes to L level.

FIG. 2 shows a circuit example of the operational amplifier 110.
The operational amplifier 110 includes a differential unit 120 and an output unit 130
including. The differential section 120 includes P-type transistors 122, 1
24, N-type transistors 126 and 128, and an N-type transistor 129 functioning as a constant current source. The output unit 130 includes a driving P-type transistor 132 and an N-type transistor 134 functioning as a constant current source. Including.

Here, the gate and the drain of the P-type transistor 122 are connected. Therefore, P-type transistor 1
In order to turn on normally the P-type transistor 1
22 needs to operate in the saturation region, and the drain-source voltage VDS1 needs to be equal to or higher than the threshold voltage of the P-type transistor 122. P-type transistor 124
The same applies to VDS2. N-type transistor 129
In order for the N-type transistor 129 to function properly as a constant current source, the N-type transistor 129 needs to operate in the saturation region, and the drain-source voltage VDS3 is
Above the threshold voltage.

Therefore, in order for the operational amplifier 110 of FIG. 2 to operate normally, the maximum value of the absolute value of the threshold voltage of the P-type and N-type transistors must be | VTHPmax, respectively.
│, │VTHNmax│, VDD ≧ │VTH
Pmax | + | VTHNmax |. For this reason, the lower limit of the operating voltage of the voltage detection unit 100 is | VTHPmax
| + | VTHNmax |. On the other hand, the output holding unit 2
Reference numeral 00 denotes a MOS logic circuit including a P-type transistor and an N-type transistor. Therefore, the lower limit of the operating voltage of the output holding unit 200 is | VTHmax |
(Maximum threshold voltage of P-type or N-type transistor)
About. In the logic circuit, if either the P-type or N-type transistor is on, the output is determined,
This is because normal operation can be guaranteed.

In the conventional voltage detecting circuit, the lower limit of the operating voltage VOPmin of the entire circuit is equal to the lower limit of the operating voltage of the operational amplifier, and is about | VTHPmax | + | VTHNmax |. On the other hand, in the present embodiment, by providing the output holding unit 200 as shown in FIG. 1, the operating voltage lower limit VOPmin of the entire circuit is reduced to about | VTHmax |, which is the operating voltage lower limit of the output holding unit 200. can do. The above is described in more detail with reference to the timing chart of FIG.

As shown in FIG. 3, the PWR signal goes low for a given period after power-on. As a result, VF2 becomes H level as is apparent from FIG. At this time, since the output VP of the voltage detection unit 100 is at the H level, VF1 is at the L level and VO is at the H level.

Next, as shown in FIG. 3, when the input voltage (power supply voltage) VDD decreases and reaches the detection voltage VDET, the output VP of the voltage detection unit 100 changes from H level to L level. As a result, the flip-flop circuit 210 enters the set state, and VF1 changes to H level and is held at H level. Therefore, the output VO of the voltage detection circuit is also L
It changes to level and is held at L level.

Thereafter, VDD continues to fall, and VDD
Is approximately | VTHPmax | + | VTHNmax |, the normal operation of the operational amplifier 110 cannot be guaranteed as described above. That is, the output VP becomes unstable as shown in FIG.

However, in this embodiment, VF1 and VO are controlled by the voltage holding function of the flip-flop circuit 210.
Are held at the H level and the L level, respectively. Since the flip-flop circuit 210 is constituted by a logic circuit, its voltage holding function is such that VDD is | VTHPmax |
+ │VTHNmax│ or less. Therefore, the operating voltage lower limit VOPmin of the entire circuit is set to | VTHmax
|

That is, conventionally, as shown in FIG.
The operating voltage lower limit VOPmin of the entire circuit is | VTHPmax | +
| VTHNmax |, but in the present embodiment, VOPmin is | VTHmax | as shown in FIG.
It becomes possible to lower to the extent. In electronic devices such as mobile phones and portable information devices, VDD is often supplied using a storage battery. Therefore, in this case, VDD is | VTHPmax | + | VTHNm due to consumption of the storage battery.
ax | According to the present embodiment, even in such a case, it is possible to guarantee that the output VO of the voltage detection circuit is normal. Therefore, normal operation of a circuit or the like that performs various processes using the VO can be guaranteed, and the lower limit of the operating voltage of the entire electronic device can be reduced.

The configuration of the voltage detecting section 100 is not limited to that shown in FIG. 1, and various modifications can be made as long as the output changes at least when the input voltage becomes the detected voltage. For example, FIG. 5A shows a circuit example of a voltage detection unit of a type in which a detection voltage has a hysteresis characteristic.
This circuit includes three resistors R4, R5, R6, an operational amplifier 140, a reference voltage source 142, and T gates (transmission gates) 144, 146. According to this circuit, if the output of the operational amplifier 140 is at the H level, the T gate 144 is turned on.
46 turns on. As a result, the voltage division ratio of VDD changes, and the value of VREG changes. As a result, the detection voltage can have a hysteresis characteristic. That is, it is possible to make the detection voltage when VDD falls and the detection voltage when VDD rises different. According to the circuit in FIG. 5A, even when noise is superimposed on VDD, the voltage detection unit can be operated to some extent normally.

The configuration of the output holding unit 200 is not limited to the one shown in FIG. 1, but is at least constituted by a logic circuit. The output of the output holding unit is changed by the change of the output of the voltage detection unit, and the output after the change is output. Various modifications are possible as long as they can be held. For example, the flip-flop circuit 210 in FIG. 1 can be formed using a circuit as illustrated in FIG. In FIG. 5B, the D flip-flop circuit 150 is reset by the PWR signal. As a result, the output VF1 is set to the L level. Here, the D terminal of the D flip-flop 150 is connected to a resistor R
7, which is pulled up to the H level. Therefore, the output VP of the voltage detector changes from H level to L level,
When the clock terminal of the flip-flop circuit 150 changes from L level to H level, the output VF1 changes from L level to H level. (Embodiment 2) FIG. 6 shows an example of a circuit diagram of a voltage detection circuit of Embodiment 2. This voltage detection circuit includes a voltage detection unit 100 and a voltage monitoring unit 300.

The voltage detecting section 100 is, as in the first embodiment,
When the input voltage VDD becomes the detection voltage VDET, the output VP is changed from, for example, H level (first voltage) to L level (second voltage) (or may be changed from L level to H level). ). The voltage monitoring unit 300 monitors the output VP of the voltage detection unit 100, and if the period during which the output of the voltage detection unit 100 is at the L level (the second voltage) is longer than a given period, changes the output VO to H. Level (third voltage) to L
Level (fourth voltage) (may be changed from L level to H level).

Next, a specific configuration example of this embodiment will be described.

The configuration of the voltage detecting section 100 is the same as that of the first embodiment, and the description is omitted. However, for the voltage detection unit 100, various modifications can be made, for example, as shown in FIG.

The voltage monitoring unit 300 includes a counter circuit 310
And an output unit 312. When VDD is higher than the detection voltage VDET and the output VP of the voltage detection unit 100 is at the H level, the counter circuit 310 is in the reset state, and the output VO is at the H level. On the other hand, V
When P changes from H level to L level, the reset state of the counter circuit 310 is released. Then, the counter circuit 310 increments (or may decrement) the count value based on a given CLK signal (clock signal). And before the count value reaches a given value, V
When P returns to the H level, the counter circuit 310 is reset again, and the count value is also initialized. On the other hand, if VP remains at L level until the count value reaches a given value, that is, if the period during which VP is at L level is longer than the given period, the output VC of counter circuit 310
Changes to H level, and VO changes to L level. As a result, the fact that VDD has become VDDET is transmitted to a processing circuit and the like at the subsequent stage.

When noise is superimposed on VDD, FIG.
The following problems occur in the conventional voltage detection circuit shown in FIG. That is, as shown in FIG. 7, noise generated inside and outside the device or noise caused by power supply voltage fluctuation due to load fluctuation inside the device is superimposed on VDD, and the voltage of VDD is maintained for a certain period (the response time of the voltage detection circuit). If the voltage drops below the detection voltage for a longer period of time, the output VO changes even though the VDD voltage supplied from the storage battery or the like has not actually dropped below the detection voltage. There is a problem that the detection operation cannot be performed.

Although a certain degree of improvement can be achieved by providing the voltage detection circuit with hysteresis characteristics, if a voltage fluctuation exceeding the hysteresis voltage occurs, the output VO changes as shown in FIG. There is a problem that the normal operation of a circuit that performs various processes using the output VO is hindered.

According to the present embodiment, as shown in FIG. 8, VO does not change to the L level unless the period of the L level of the output VP of the voltage detector 100 is longer than the given period TC. . That is, the period when the VP is at the L level is T1,
When T2 (T1, T2 <TC), the output VO does not change to the L level. Therefore, even when noise is superimposed on VDD, the output VO does not change, and normal operation of the subsequent processing circuit and the like can be guaranteed. In addition, since it is not always necessary to provide the detection voltage with the hysteresis characteristic, highly accurate voltage detection can be performed.

The configuration of the voltage monitor 300 is such that at least the output of the voltage detector is monitored, and when the period during which the output of the voltage detector becomes the second voltage is longer than the given period, Various modifications can be made as long as the output is changed.

For example, FIG.
The following shows an example of a specific circuit. This circuit includes D flip-flop circuits 320, 322, 324, NAND 32
6, including an inverter 328. The D flip-flop circuit 320 is reset when VP is at the H level,
The count value is initialized to (000). When VP goes to L level, the reset is released, and the count value is incremented by the CLK signal. When the count value reaches (111), the output VC changes from the L level to the H level.

FIG. 9 shows an alternative to the counter circuit 310.
It is also possible to provide a circuit as shown in FIG. This circuit includes inverters 330, 332, 334 and a capacitor Cd. However, the inverter 332 has a hysteresis characteristic in the threshold voltage. In this circuit, the period TC shown in FIG. 8 is determined by the on-resistance of the inverter 330, the capacitor Cd, the threshold voltage of the inverter 332, and the like. VC changes from L level to H level only when the period during which VP is at L level is longer than TC.

Comparing the case where the circuit shown in FIG. 9A is adopted with the case where the circuit shown in FIG. 9B is adopted, the circuit shown in FIG. It has the advantage of keeping it accurate. That is, in the circuit shown in FIG. 9B, the ON resistance value of the inverter 330 and the capacitor C
The variation in the accuracy of the period TC increases due to the variation in the capacitance value of d and the variation in the threshold value of the inverter 332.
In the circuit shown in (A), the period TC is digitally determined, so that the accuracy can be kept accurate. Further, when there is a circuit that generates a clock signal in an integrated circuit or an electronic device including a voltage detection circuit, a clock signal is newly generated by using the clock signal of the circuit as a clock of a counter circuit. The circuit illustrated in FIG. 9A can be employed without adding a circuit.

On the other hand, the circuit shown in FIG. 9B has an advantage that it is not necessary to provide a circuit for generating a clock signal. (Embodiment 3) Embodiment 3 is an embodiment relating to a combination of Embodiments 1 and 2, and FIG. 10 shows a configuration example thereof.

As shown in FIG. 10, the voltage detection circuit of the third embodiment includes the voltage detection unit 100, the voltage monitoring unit 300, and the output holding unit 200 described in the first and second embodiments. Then, the voltage monitoring unit 300 monitors the output VP of the voltage detection unit 100. When the period during which the output VP of the voltage detection unit 100 is at the L level (or at the H level) is longer than a given period, for example, the output holding unit 200 is notified that the VP has changed from the H level to the L level. . Specifically, the output VM of the voltage monitoring unit 300 is changed from H level to L level.

In the circuit of the first embodiment shown in FIG. 1, when noise is superimposed on VDD, the following problem may occur. That is, as shown in FIG. 11A, when VDD falls below VDET due to noise, VP changes to the L level. Then, in the circuit of FIG.
10 is set, and the output VO is held at the L level. The flip-flop circuit 210
Once in the set state, even if VP returns to the H level thereafter, the set state is not released unless the PWR signal goes to the L level. Therefore, VDD becomes V
If it is less than DET, erroneous voltage detection may be performed.

On the other hand, in the third embodiment, as shown in FIG. 10, the voltage monitoring unit 300 monitors VP. Then, as shown in FIG. 11B, unless the period in which VP is at the L level becomes longer than the given period TC, the voltage monitoring unit 30
The output VM of 0 does not change from H level to L level. Therefore, the flip-flop circuit 210 enters the set state for the first time at the point F in FIG. 11B, and the output VO is held at the L level. As a result, erroneous voltage detection caused by VDD noise can be prevented. That is, according to the present embodiment, the lower limit of the operating voltage of the entire circuit can be reduced,
In addition, malfunction due to noise can be effectively prevented.

The voltage detector 100 and the voltage monitor 30
0, the configuration of the output holding unit 200 can be variously modified as described in the first and second embodiments. (Fourth Embodiment) A fourth embodiment relates to an electronic apparatus including the voltage detection circuit described in the first to third embodiments.

The voltage detection circuits described in Embodiments 1 to 3
For example, as shown in FIG.
S) 1100, a personal computer (information processing device) 1200 as shown in FIG. 12 (B), or a pager, electronic organizer, printer, television, electronic desk calculator, P
OS terminal, device with touch panel, projector,
The present invention can be applied to various electronic devices such as a word processor, a viewfinder type or a monitor direct-view type video tape recorder, and a car navigation device.

For example, a mobile phone 110 shown in FIG.
0 includes a display unit 1102, a dial button 1104, and the like. In addition, a personal computer 1200 illustrated in FIG.
4 and display units 1206 and 1208. For example, when a drop in the power supply voltage is detected by the voltage detection circuit, a display warning the drop in the power supply voltage is displayed on the display unit 1102.
1206 and 1208.

In particular, the voltage detection circuits described in the first to third embodiments are applied to electronic equipment to which a power supply voltage is supplied by using a storage battery in order to reduce the lower limit of the operating voltage and reduce the influence of noise. In this case, there is an advantage that the lower limit of the operating voltage of the entire electronic device can be reduced, noise resistance can be improved, and the like.

FIG. 13 shows an example of a functional block diagram of an electronic apparatus according to the fourth embodiment. This electronic device includes a voltage detection circuit 1500 described in the first to third embodiments and a power supply unit 1510.
, A clock generation unit 1520, and a timer unit 1530
, A display unit 1540, and a processing unit 1550.

Here, the power supply section 1510 supplies the power supply voltage VDD to be detected by the voltage detection circuit 1500 using a given storage battery.

The clock generator 1520 generates a given clock signal CLK. When measuring the period in which the output of the voltage detection unit is at the L level using a counter circuit, the clock signal CLK from the clock generation unit 1520 is used. The clock signal CLK is used, for example, by a timer unit 1530 that performs a timer process. Therefore, according to the configuration in which the voltage monitoring unit includes the counter circuit, the clock signal CLK can be effectively used.

The display section 1540 is connected to the voltage detection circuit 15.
The display unit 1540 performs a given display based on the output VO of 00, such as a liquid crystal or an LED.
Can be considered. For example, the display unit 15
On 40, a warning display of a drop in the power supply voltage VDD and the like are displayed.

The processing section 1550 includes the voltage detection circuit 15
A given process is performed based on the output VO of 00, and is constituted by a dedicated semiconductor integrated circuit or hardware such as a CPU. As the given process in this case, a process for displaying a warning when the VDD drops, a memory backup process, a reset process for the CPU and other circuits, and the like can be considered.

The present invention is not limited to the first to fourth embodiments, and various modifications can be made within the scope of the present invention.

For example, the configurations of the voltage detection unit, the output holding unit, and the voltage monitoring unit are not limited to those described in the above embodiments. Also, the configuration of the electronic device described in FIG. 13 is particularly desirable, but is not limited thereto. For example, power supply unit 1
510, clock generation unit 1520, timer unit 153
0, and may not have at least one of the display unit 1540 and the processing unit 1550.

The configuration of the operational amplifier, the flip-flip, the counter circuit, the method of generating the initialization signal PWR, and the like are not limited to those described in this embodiment, and various modifications can be made.

[0068]

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration example of a first embodiment.

FIG. 2 is a circuit diagram illustrating a configuration example of an operational amplifier.

FIG. 3 is a timing chart for explaining the operation of the first embodiment.

FIGS. 4A and 4B are diagrams for explaining improvement of an operating voltage lower limit.

FIGS. 5A and 5B are diagrams illustrating a modification example of the voltage detection unit and the flip-flop circuit.

FIG. 6 is a circuit diagram illustrating a configuration example of a second embodiment;

FIG. 7 is a diagram for explaining a problem caused by VDD noise;

FIG. 8 is a timing chart for explaining the operation of the second embodiment.

FIGS. 9A and 9B are diagrams illustrating a specific example of a counter circuit and an example of a circuit that substitutes for the counter circuit.

FIG. 10 is a circuit diagram showing a configuration example of a third embodiment.

FIGS. 11A and 11B are timing charts for explaining the operation of the third embodiment.

FIGS. 12A and 12B are diagrams each illustrating an example of a mobile phone or a personal computer, which is one of electronic devices.

FIG. 13 is a diagram illustrating a configuration example of an electronic device.

FIG. 14 is a diagram illustrating a configuration example of a conventional voltage detection circuit.

[Description of Signs] 90 power-on reset circuit 100 voltage detection unit 110 operational amplifier (comparator) 112 reference voltage source 200 output holding unit 210 flip-flop circuit 212, 214 NAND 216 P-type transistor 218 N-type transistor 220 output unit 300 voltage monitoring unit 310 counter circuit 312 output unit

Claims (13)

[Claims] 1. A voltage detection circuit for detecting whether an input voltage has reached a given detection voltage, comprising: a high-level voltage and a low-level voltage when the input voltage has reached the given detection voltage. A voltage detecting means for changing an output from a first voltage which is one of the voltages to a second voltage which is the other voltage; and a logic circuit having an operating voltage lower limit lower than the voltage detecting means. The output of the voltage detecting means is the first
When the voltage changes from the third voltage to the second voltage, the output is changed from the third voltage, which is one of the high-level voltage and the low-level voltage, to the fourth voltage, which is the other voltage. Holding the fourth voltage and holding the fourth voltage
And a voltage holding circuit for outputting a voltage of the voltage detection circuit. 2. The voltage detection means according to claim 1, wherein said voltage detection means includes an operational amplifier having an operation voltage lower limit higher than a logic circuit, and said output holding means detects said third voltage based on a given initialization signal. A voltage detection circuit including a flip-flop circuit for initializing a holding voltage and holding the fourth voltage when an output of the voltage detecting means changes from the first voltage to the second voltage. . 3. The voltage detection circuit according to claim 2, further comprising a power-on detection circuit for detecting that the power is turned on and outputting the initialization signal. 4. The voltage detection circuit according to claim 3, wherein the input voltage is a voltage based on a voltage of the power supply. 5. The method according to claim 1, wherein an output of the voltage detecting means is monitored, and when a period during which the output of the voltage detecting means is the second voltage is longer than a given period. And a voltage monitoring means for transmitting a change in the output of the voltage detecting means from the first voltage to the second voltage to the output holding means. 6. The voltage monitor according to claim 5, wherein the voltage monitor changes a count value based on a given clock signal when the voltage detector outputs the second voltage. A counter circuit for transmitting a change in the output of the voltage detecting means to the output holding means when a predetermined value is obtained. 7. The voltage monitoring unit according to claim 5, wherein the voltage monitoring unit includes a capacitive element and a resistive element that charges and discharges the capacitive element, and an output of the voltage detecting unit is the second voltage. A voltage detection circuit, comprising: a circuit for transmitting a change in the output of the voltage detection means to the output holding means when the period is longer than a given period. 8. A voltage detection circuit for detecting whether or not an input voltage has reached a given detection voltage, wherein when the input voltage has reached the given detection voltage, a high-level voltage and a low-level voltage Voltage detecting means for changing an output from a first voltage which is one of the voltages to a second voltage which is the other voltage; monitoring an output of the voltage detecting means, wherein an output of the voltage detecting means is When the period of the second voltage is longer than the given period, the output is changed from the third voltage which is one of the high level voltage and the low level voltage to the fourth voltage which is the other voltage. And a voltage monitoring means for changing the voltage. 9. The method according to claim 8, wherein the voltage monitor changes a count value based on a given clock signal when the voltage detector outputs the second voltage. A counter circuit that changes the output from the third voltage to the fourth voltage when the value of the second voltage becomes a given value. 10. The voltage detection circuit according to claim 6, wherein the counter circuit initializes the count value when an output of the voltage detection means is the first voltage. . 11. The voltage monitoring unit according to claim 8, wherein the voltage monitoring unit includes a capacitive element and a resistive element that charges and discharges the capacitive element, and an output of the voltage detecting unit is the second voltage. A voltage detection circuit, comprising: a circuit that changes an output from the third voltage to the fourth voltage when a period is longer than a given period. 12. A power supply unit for supplying a power supply voltage, a voltage detection circuit for detecting a power supply voltage from the power supply unit, and a detection result of the voltage detection circuit is displayed. An electronic device, comprising: a display unit. 13. A power supply unit for supplying a power supply voltage, a clock generation unit for generating a clock signal, a timer unit for performing a timer process based on the clock signal from the clock generation unit, and an output of the timer unit. And a processing unit for performing a predetermined process based on the power supply voltage. 7. The electronic device according to claim 6, wherein a power supply voltage from the power supply unit is detected, and a clock signal from the clock generation unit is input as the given clock signal. An electronic device comprising: the voltage detection circuit according to any one of 9 and 10.