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JPH10284812A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH10284812A
JPH10284812A JP9089333A JP8933397A JPH10284812A JP H10284812 A JPH10284812 A JP H10284812A JP 9089333 A JP9089333 A JP 9089333A JP 8933397 A JP8933397 A JP 8933397A JP H10284812 A JPH10284812 A JP H10284812A
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
mark
chip
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9089333A
Other languages
Japanese (ja)
Inventor
Yoshiaki Isobe
善朗 礒部
Kohei Sato
耕平 佐藤
Takahiro Nagamine
高宏 長嶺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9089333A priority Critical patent/JPH10284812A/en
Publication of JPH10284812A publication Critical patent/JPH10284812A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/06179—Corner adaptations, i.e. disposition of the bonding areas at the corners of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601—Structure
    • H01L2224/16012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/16013—Structure relative to the bonding area, e.g. bond pad the bump connector being larger than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/8113—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/81132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structure Of Printed Boards (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

(57)【要約】 【課題】 プリント配線板に半導体チップを実装した時
の位置ずれ量や位置ずれ方向を短時間で確認できる半導
体デバイスを得る。 【解決手段】 電極パッド２４有する半導体チップ３と
パッド２を有するプリント配線板１とを備え、電極パッ
ドをパッドに接続して半導体チップをプリント配線板に
実装する半導体デバイスにおいて、半導体チップをプリ
ント配線板の正常位置に実装した状態で半導体チップの
電極パッドの形状およびプリント配線板のパッドの形状
が相互にはみだして対称形状を示すように形成されたも
のである。 (57) [Problem] To provide a semiconductor device capable of confirming a displacement amount and a displacement direction in a short time when a semiconductor chip is mounted on a printed wiring board. SOLUTION: In a semiconductor device comprising a semiconductor chip 3 having electrode pads 24 and a printed wiring board 1 having pads 2, a semiconductor chip is mounted on a printed wiring board by connecting the electrode pads to the pads. The semiconductor device is formed so that the shape of the electrode pads of the semiconductor chip and the shape of the pads of the printed wiring board protrude from each other and show a symmetric shape in a state where the semiconductor device is mounted on a normal position of the board.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】この発明は、半導体チップを
プリント配線板に実装する半導体デバイスの検査方式に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inspecting a semiconductor device in which a semiconductor chip is mounted on a printed wiring board.

【０００２】[0002]

【従来の技術】半導体チップをプリント配線板に実装す
る半導体デバイスについて、ベアチップ実装プリント配
線板を例にして説明する。図１５は、従来のベアチップ
実装プリント配線板のＬＳＩチップ搭載部の上面透視
図、図１６は図１５のＦ−Ｆ’断面図であり、図におい
て、１はプリント配線板、２はプリント配線板１上に形
成されたパッド、３はプリント配線板１に実装されたＬ
ＳＩチップ、４はＬＳＩチップ３に形成された電極パッ
ド、５はＬＳＩチップ３の電極パッド４上に形成された
突起電極である。2. Description of the Related Art A semiconductor device in which a semiconductor chip is mounted on a printed wiring board will be described with reference to a printed circuit board mounted on a bare chip. FIG. 15 is a top perspective view of an LSI chip mounting portion of a conventional bare chip mounting printed wiring board. FIG. 16 is a cross-sectional view taken along line FF ′ of FIG. 15, where 1 is a printed wiring board and 2 is a printed wiring board. Pads 3 formed on the printed wiring board 1 are mounted on the printed wiring board 1.
The SI chip 4 is an electrode pad formed on the LSI chip 3, and 5 is a protruding electrode formed on the electrode pad 4 of the LSI chip 3.

【０００３】次に動作について説明する。図において、
ＬＳＩチップ３の電極パッド４に形成された突起電極５
がプリント配線板１に形成されたパッド２に接続されて
おり、ＬＳＩチップ３の搭載位置をＸ線検査装置にてチ
ェックする場合、プリント配線板１上のパッド２とＬＳ
Ｉチップ３上の電極パッド４または突起電極５が重なっ
ていることを確認する。Next, the operation will be described. In the figure,
Protruding electrode 5 formed on electrode pad 4 of LSI chip 3
Are connected to the pads 2 formed on the printed wiring board 1, and when the mounting position of the LSI chip 3 is checked by the X-ray inspection device, the pads 2 and LS on the printed wiring board 1
It is confirmed that the electrode pads 4 or the protruding electrodes 5 on the I chip 3 overlap.

【０００４】また、図１７は、例えば、実開平２−５４
２２６号公報に示された従来の多層プリント配線板の平
面図であり、図において、１はプリント配線板、６ａは
プリント配線板１の表層に設けられた認識マーク、６ｂ
は認識マーク６ａの位置に対応する内層部分に設けられ
た内層銅箔であり、内層銅箔６ｂと認識マーク６ａとの
間に絶縁層が介在している。FIG. 17 shows, for example, Japanese Utility Model Laid-Open No. 2-54.
FIG. 1 is a plan view of a conventional multilayer printed wiring board disclosed in Japanese Patent Publication No. 226, where 1 is a printed wiring board, 6a is a recognition mark provided on the surface layer of the printed wiring board 1, 6b
Is an inner layer copper foil provided in an inner layer portion corresponding to the position of the recognition mark 6a, and an insulating layer is interposed between the inner layer copper foil 6b and the recognition mark 6a.

【０００５】次に動作について説明する。図１７におい
て、認識マーク６ａの位置に対応する内層部に銅箔部６
ｂを設けるため、認識マークの背景が暗色となりマーク
の認識が容易になる。Next, the operation will be described. In FIG. 17, a copper foil portion 6 is provided on the inner layer portion corresponding to the position of the recognition mark 6a.
Since b is provided, the background of the recognition mark becomes dark and the recognition of the mark becomes easy.

【０００６】[0006]

【発明が解決しようとする課題】従来のベアチップ実装
プリント配線板では、Ｘ線検査装置でＬＳＩチップ３の
搭載位置をチェックする場合、プリント配線板１のパッ
ド幅がＬＳＩチップ３の電極幅より太く構成されてお
り、プリント配線板１のパッド２とＬＳＩチップ３の電
極パッド４の両方が黒く映るため、プリント配線板１の
パッド２とＬＳＩチップ３の電極パッド４の位置ずれ量
や位置ずれ方向の確認が困難である。In a conventional bare chip mounted printed wiring board, when the mounting position of the LSI chip 3 is checked by an X-ray inspection apparatus, the pad width of the printed wiring board 1 is larger than the electrode width of the LSI chip 3. Since both the pad 2 of the printed wiring board 1 and the electrode pad 4 of the LSI chip 3 appear black, the amount of displacement and the direction of the displacement between the pad 2 of the printed wiring board 1 and the electrode pad 4 of the LSI chip 3 Is difficult to confirm.

【０００７】また、位置ずれ量や位置ずれ方向を確認す
るためには、ＬＳＩチップ３の４隅の電極パッド４につ
いて検査する必要があり、検査時間が増える等の問題点
があった。Further, in order to confirm the amount of displacement and the direction of displacement, it is necessary to inspect the electrode pads 4 at the four corners of the LSI chip 3, and there is a problem that the inspection time is increased.

【０００８】また、実開平２−５４２２６号公報に示さ
れた従来の多層プリント配線板での構成を本ベアチップ
実装プリント配線板に応用し、図１７において、 内層
銅箔６ｂの形状をＬＳＩチップに認識マークとして設
け、Ｘ線検査装置でＬＳＩチップの搭載位置をチェック
する場合、プリント配線板の認識マークよりＬＳＩチッ
プの認識マークが大きく構成されているため、ＬＳＩの
認識マークのみ映り、位置ずれ量や位置ずれ方向を確認
することが困難である。In addition, the configuration of the conventional multilayer printed wiring board disclosed in Japanese Utility Model Laid-Open No. 2-54226 is applied to this bare chip mounted printed wiring board, and in FIG. 17, the shape of the inner layer copper foil 6b is changed to an LSI chip. When provided as a recognition mark and the mounting position of the LSI chip is checked by an X-ray inspection apparatus, the recognition mark of the LSI chip is configured to be larger than the recognition mark of the printed wiring board. And it is difficult to confirm the direction of displacement.

【０００９】この発明は、上記のような問題点を解決す
るためになされたもので、プリント配線板に半導体チッ
プを実装した時の位置ずれ量や位置ずれ方向を短時間で
確認できる半導体デバイスを得ることを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device capable of confirming a position shift amount and a position shift direction when a semiconductor chip is mounted on a printed wiring board in a short time. The purpose is to gain.

【００１０】[0010]

【課題を解決するための手段】この発明に係る半導体デ
バイスは、電極パッドを有する半導体チップとパッドを
有するプリント配線板とを備え、前記電極パッドを前記
パッドに接続して前記半導体チップを前記プリント配線
板に実装する半導体デバイスにおいて、前記半導体チッ
プを前記プリント配線板の正常位置に実装した状態で前
記半導体チップの電極パッドの形状および前記プリント
配線板のパッドの形状が相互にはみだして対称形状を示
すように形成されたものである。A semiconductor device according to the present invention includes a semiconductor chip having electrode pads and a printed wiring board having pads. The semiconductor chip is connected to the pads by connecting the electrode pads to the pads. In a semiconductor device mounted on a wiring board, in a state where the semiconductor chip is mounted at a normal position on the printed wiring board, the shape of the electrode pad of the semiconductor chip and the shape of the pad of the printed wiring board are mutually symmetrical. It was formed as shown.

【００１１】また、パッドの一方向の寸法を電極パッド
のそれより短くし、パッドの他方向の寸法を電極パッド
のそれより長くしたものである。Further, the dimension of the pad in one direction is shorter than that of the electrode pad, and the dimension of the pad in the other direction is longer than that of the electrode pad.

【００１２】また、電極パッドを有する半導体チップと
パッドを有するプリント配線板とを備え、前記電極パッ
ドを前記パッドに接続して前記半導体チップを前記プリ
ント配線板に実装する半導体デバイスにおいて、前記半
導体チップに任意の形状の第１のマークをＸ線を透過し
ない材料で形成するとともに、前記プリント配線板に任
意の形状の第２のマークをＸ線を透過しない材料で形成
し、前記半導体チップを前記プリント配線板に実装した
状態で半導体チップのプリント配線板に対する位置関係
が正常な場合とずれている場合とで前記第１マークの第
２のマークに対する相対的位置関係を認識可能にしたも
のである。In a semiconductor device comprising a semiconductor chip having electrode pads and a printed wiring board having pads, the semiconductor chip is mounted on the printed wiring board by connecting the electrode pads to the pads. A first mark of an arbitrary shape is formed of a material that does not transmit X-rays; a second mark of an arbitrary shape is formed on the printed wiring board using a material that does not transmit X-rays; The relative position of the first mark with respect to the second mark can be recognized when the semiconductor chip is mounted on the printed circuit board and the positional relationship between the semiconductor chip and the printed circuit board is normal and shifted. .

【００１３】また、第１のマークおよび第２のマーク
は、半導体チップをプリント配線板に実装した状態で一
方のマークが中心部を形成し、他のマークが中心部のマ
ークを囲う周辺部を形成してなるものである。Further, the first mark and the second mark are formed in such a manner that one of the marks forms a central portion in a state where the semiconductor chip is mounted on the printed wiring board and the other mark surrounds the central portion of the mark. It is formed.

【００１４】[0014]

【発明の実施の形態】以下、この発明の実施の形態を図
について説明する。 実施の形態１．図１はこの発明の実施の形態１によるベ
アチップ実装プリント配線板のＬＳＩチップ搭載部の上
面透視図、図２は図１のＡ−Ａ’断面図である。図にお
いて、１はプリント配線板、２はプリント配線板１上に
形成されたパッド、３はプリント配線板１に実装された
ＬＳＩチップ、４はＬＳＩチップ３に形成された電極パ
ッド、５はＬＳＩチップ３の電極パッド上に形成された
突起電極であリ、パッド２、電極パッド４は各々断面が
方形状に形成されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. FIG. 1 is a top perspective view of an LSI chip mounting portion of a bare chip mounting printed wiring board according to Embodiment 1 of the present invention, and FIG. 2 is a cross-sectional view taken along the line AA 'of FIG. In the figure, 1 is a printed wiring board, 2 is a pad formed on the printed wiring board 1, 3 is an LSI chip mounted on the printed wiring board 1, 4 is an electrode pad formed on the LSI chip 3, 5 is an LSI chip. The protruding electrodes formed on the electrode pads of the chip 3, the pads 2 and the electrode pads 4 are each formed in a square cross section.

【００１５】次に動作について説明する。プリント配線
板１のパッド２がＬＳＩチップ３の電極パッド４の幅方
向が狭く、長さ方向が長いので、ＬＳＩチップ３をプリ
ント配線板１の正常位置に実装した状態では実装後のＸ
線検査時においてＬＳＩチップ３の電極パッド４の形状
およびプリント配線板１のパッド２の形状が相互にはみ
だして左右、上下が対称形状を示し、ずれている場合
は、前記対称形状が崩れておりプリント配線板１のパッ
ド２とＬＳＩチップ３の電極パッド４のそれぞれの位置
関係を認識できる。Next, the operation will be described. Since the width direction of the pad 2 of the printed wiring board 1 is narrow and the length direction of the electrode pad 4 of the LSI chip 3 is narrow, X after mounting in a normal position of the LSI chip 3 in the printed wiring board 1
At the time of line inspection, the shape of the electrode pads 4 of the LSI chip 3 and the shape of the pads 2 of the printed wiring board 1 protrude from each other, and are symmetrical in the left, right, up and down directions. The positional relationship between the pad 2 of the printed wiring board 1 and the electrode pad 4 of the LSI chip 3 can be recognized.

【００１６】実施の形態２．図３は、この発明の実施の
形態２によるベアチップ実装プリント配線板におけるＬ
ＳＩチップ搭載部の上面透視図、図４は図３のＢ−Ｂ’
断面図、図５は図３のＣ部拡大図である。図３、図４、
および図５に示すように、この実施の形態では、プリン
ト配線板１とＬＳＩチップ３のそれぞれに位置ずれ確認
用マークを設けている。図において、６はプリント配線
板１に設けられた位置ずれ確認用マークでリング状の形
状をしており、７はＬＳＩチップ３に設けられた位置ず
れ確認用マークでＬＳＩチップ３をプリント配線板１の
正常位置に実装した状態で、プリント配線板１に設けら
れた位置ずれ確認用マーク６と重ならずかつ中心部に位
置する円状を呈している。８はプリント配線板１の位置
ずれ確認用マーク６とＬＳＩチップ３の位置ずれ確認用
マーク７との間隔である。なお、位置ずれ確認用マーク
６、７は金属等のＸ線を透過しない材質で構成してい
る。Embodiment 2 FIG. 3 is a cross-sectional view of a printed circuit board mounted with bare chips according to a second embodiment of the present invention.
FIG. 4 is a top perspective view of the SI chip mounting portion, and FIG.
FIG. 5 is a cross-sectional view of FIG. 3 and 4,
As shown in FIG. 5 and FIG. 5, in this embodiment, the printed wiring board 1 and the LSI chip 3 are each provided with a misalignment confirmation mark. In the figure, reference numeral 6 denotes a mark for positional deviation confirmation provided on the printed wiring board 1 and has a ring shape, and reference numeral 7 denotes a positional deviation confirmation mark provided on the LSI chip 3 for connecting the LSI chip 3 to the printed wiring board. In a state where it is mounted at the normal position of No. 1, it has a circular shape that does not overlap with the misalignment confirmation mark 6 provided on the printed wiring board 1 and is located at the center. Numeral 8 denotes the distance between the mark 6 for confirming the displacement of the printed wiring board 1 and the mark 7 for confirming the displacement of the LSI chip 3. Note that the misalignment confirmation marks 6, 7 are made of a material that does not transmit X-rays, such as a metal.

【００１７】次に動作について説明する。ＬＳＩチップ
３の位置ずれ確認用マークはプ リント配線板１の位置
ずれ確認用マーク６の内側になるよう配置され、ＬＳＩ
チップ３の位置ずれ確認用マーク７とプリント配線板１
の位置ずれ確認用マーク６との間隔８は位置ずれ許容限
界値以内となるよう配置されており、Ｘ線検査時にＬＳ
Ｉチップの位置ずれ確認用マークとプリント配線板の位
置ずれ確認用マークを別々に認識でき、位置ずれ量と位
置ずれ方向を確認できる。Next, the operation will be described. The misalignment confirmation mark of the LSI chip 3 is arranged inside the misalignment confirmation mark 6 of the printed wiring board 1, and the LSI
Mark 3 for confirming displacement of chip 3 and printed wiring board 1
Are arranged so as to be within the allowable limit value of the positional deviation, and the LS is set at the time of X-ray inspection.
It is possible to separately recognize the misalignment confirmation mark of the I chip and the misalignment confirmation mark of the printed wiring board, and confirm the misalignment amount and misalignment direction.

【００１８】また、図３ではプリント配線板の位置ずれ
確認用マークの内側にＬＳＩチップの位置ずれ確認用マ
ークが入るように構成しているが、図６に示すようにＬ
ＳＩチップの位置ずれ確認用マークの内側にプリント配
線板の位置ずれ確認用マークが入る構成でもよく、同様
の効果を奏する。In FIG. 3, the mark for confirming the displacement of the LSI chip is arranged inside the mark for confirming the displacement of the printed wiring board, but as shown in FIG.
A configuration in which the misalignment confirmation mark of the printed wiring board is inserted inside the misalignment confirmation mark of the SI chip may be used, and the same effect can be obtained.

【００１９】また、図３ではＬＳＩチップとプリント配
線板の位置ずれ確認用マークが円形のものを示したが、
図７に示すように四角形でもよく、この場合、ＬＳＩチ
ップの位置ずれ確認用マークとして、配線を必要としな
い空き電極を用いることができる。FIG. 3 shows a circular mark for confirming the displacement between the LSI chip and the printed wiring board.
As shown in FIG. 7, a square may be used. In this case, an empty electrode which does not require wiring can be used as a mark for confirming the displacement of the LSI chip.

【００２０】また、図３ではＬＳＩチップとプリント配
線板の位置ずれ確認用マークが円形のものを示したが、
図８、図９に示すように直線形状でもよく、この場合、
位置ずれの方向をＸ方向、Ｙ方向ごとに認識できる。FIG. 3 shows a circular mark for confirming the displacement between the LSI chip and the printed wiring board.
As shown in FIGS. 8 and 9, a linear shape may be used.
The direction of the displacement can be recognized for each of the X direction and the Y direction.

【００２１】また、図８、図９ではＬＳＩチップおよび
プリント配線板のＸＹ方向に直線形状の位置ずれ確認用
マークを設けたものを示したが、図１０に示すようにＬ
ＳＩチップ搭載位置およびＬＳＩチップ３の中心からの
放射直線上に位置ずれ確認用マークを設けてよく、この
場合、ＬＳＩチップの回転ずれを認識できる。FIGS. 8 and 9 show the LSI chip and the printed wiring board provided with a linear misalignment confirmation mark in the XY directions. As shown in FIG.
A mark for confirming the displacement may be provided on the SI chip mounting position and on the radiation straight line from the center of the LSI chip 3, and in this case, the rotational displacement of the LSI chip can be recognized.

【００２２】また、図３ではＬＳＩチップとプリント配
線板のそれぞれに位置ずれ確認用マークを設けたものを
示したが、図１１、図１２に示すように、ＬＳＩチップ
３の位置ずれ確認用マークとして、配線を必要としない
電極パッド４に設けられた突起電極５を用い、突起電極
５とプリント配線板１の位置ずれ確認用マークの内径を
突起電極径の最大許容値としてもよく、この場合、ＬＳ
Ｉチップ３の突起電極５のつぶれ方により、ＬＳＩチッ
プとプリント配線板の間隔を確認することができる。FIG. 3 shows the LSI chip and the printed wiring board provided with misalignment confirmation marks respectively. However, as shown in FIGS. 11 and 12, the misalignment confirmation mark of the LSI chip 3 is provided. As an example, the protrusion electrode 5 provided on the electrode pad 4 that does not require wiring may be used, and the inner diameter of the mark for confirming the displacement between the protrusion electrode 5 and the printed wiring board 1 may be set as the maximum allowable value of the protrusion electrode diameter. , LS
The distance between the LSI chip and the printed wiring board can be confirmed by how the protruding electrode 5 of the I chip 3 is crushed.

【００２３】また、上記実施の形態では、プリント配線
板が両面基板の場合を示したが、図１３、図１４に示す
ように多層基板とし、ＬＳＩチップ３の位置ずれ確認用
マーク７およびプリント配線板１の位置ずれ確認用マー
ク６の位置の内層銅箔９および裏面銅箔を除去してもよ
く、この場合、Ｘ線検査時にＬＳＩチップ３とプリント
配線板１の位置ずれ確認用マーク６、７とプリント配線
板１の内層銅箔９が重ならないため、それぞれの位置ず
れ確認用マークを鮮明に認識できる。Further, in the above embodiment, the case where the printed wiring board is a double-sided board is shown. However, as shown in FIGS. The inner copper foil 9 and the backside copper foil at the position of the misalignment confirmation mark 6 on the board 1 may be removed. In this case, the misalignment confirmation mark 6 between the LSI chip 3 and the printed wiring board 1 during the X-ray inspection, 7 and the inner layer copper foil 9 of the printed wiring board 1 do not overlap each other, so that the respective misalignment confirmation marks can be clearly recognized.

【００２４】[0024]

【発明の効果】以上のように、この発明によれば、電極
パッドを有する半導体チップとパッドを有するプリント
配線板とを備え、電極パッドをパッドに接続して半導体
チップをプリント配線板に実装する半導体デバイスにお
いて、半導体チップをプリント配線板の正常位置に実装
した状態で半導体チップの電極パッドの形状およびプリ
ント配線板のパッドの形状が相互にはみだして対称形状
を示すように形成されたことにより、Ｘ線検査装置によ
り半導体チップの位置ずれ確認を行う場合、半導体チッ
プの位置ずれ量と位置ずれ方向が確認でき、良否判定お
よび半導体チップ搭載装置の搭載位置調整が容易になる
効果がある。As described above, according to the present invention, a semiconductor chip having electrode pads and a printed wiring board having pads are provided, and the semiconductor chips are mounted on the printed wiring board by connecting the electrode pads to the pads. In the semiconductor device, the shape of the electrode pads of the semiconductor chip and the shape of the pads of the printed wiring board are formed so as to protrude from each other and show a symmetrical shape in a state where the semiconductor chip is mounted on a normal position of the printed wiring board. When the position shift of the semiconductor chip is confirmed by the X-ray inspection device, the position shift amount and the direction of the position shift of the semiconductor chip can be confirmed, and there is an effect that the quality judgment and the adjustment of the mounting position of the semiconductor chip mounting device are facilitated.

【００２５】また、パッドの一方向の寸法を電極パッド
のそれより短くし、パッドの他方向の寸法を電極パッド
のそれより長くしたことにより、Ｘ線検査時のＸ線像が
単純になり、位置ずれ量と位置ずれ方向を更に容易に認
識できる。Further, by making the dimension of the pad in one direction shorter than that of the electrode pad and making the dimension of the pad in the other direction longer than that of the electrode pad, the X-ray image at the time of X-ray inspection is simplified. The displacement amount and the displacement direction can be more easily recognized.

【００２６】また、電極パッドを有する半導体チップと
パッドを有するプリント配線板とを備え、電極パッドを
パッドに接続して半導体チップをプリント配線板に実装
する半導体デバイスにおいて、半導体チップに任意の形
状の第１のマークをＸ線を透過しない材料で形成すると
ともに、プリント配線板に任意の形状の第２のマークを
Ｘ線を透過しない材料で形成し、半導体チップをプリン
ト配線板に実装した状態で半導体チップのプリント配線
板に対する位置関係が正常な場合とずれている場合とで
第１マークの第２のマークに対する相対的位置関係を認
識可能にしたことにより、半導体チップの電極パッドの
形状およびプリント配線板のパッドの形状を考慮するこ
と無く、Ｘ線検査装置により半導体チップの位置ずれ確
認を行う場合、半導体チップの位置ずれ量と位置ずれ方
向が確認でき、良否判定および半導体チップ搭載装置の
搭載位置調整が容易になる効果がある。In a semiconductor device having a semiconductor chip having electrode pads and a printed wiring board having pads, the semiconductor chip is mounted on the printed wiring board by connecting the electrode pads to the pads. The first mark is formed of a material that does not transmit X-rays, the second mark of an arbitrary shape is formed on the printed wiring board using a material that does not transmit X-rays, and the semiconductor chip is mounted on the printed wiring board. The relative position of the first mark with respect to the second mark can be recognized when the position of the semiconductor chip with respect to the printed wiring board is normal and when the position of the semiconductor chip is misaligned. When confirming the misalignment of a semiconductor chip with an X-ray inspection device without considering the shape of the pads on the wiring board, Body can positional displacement amount and confirmation positional deviation direction of the chip, the effect of the mounting position adjustment is facilitated the quality determination and the semiconductor chip mounting device.

【００２７】また、第１のマークおよび第２のマーク
は、半導体チップをプリント配線板に実装した状態で一
方のマークが中心部を形成し、他のマークが中心部のマ
ークを囲う周辺部を形成してなるので、Ｘ線検査時のＸ
線像が単純になり、位置ずれ量と位置ずれ方向を更に容
易に認識できる。The first mark and the second mark are formed in such a manner that one of the marks forms a central portion while the semiconductor chip is mounted on a printed wiring board, and the other mark forms a peripheral portion surrounding the central mark. Formed at the time of X-ray inspection.
The line image is simplified, and the amount of displacement and the direction of displacement can be more easily recognized.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 この発明の実施の形態１によるベアチップ実
装プリント配線板のＬＳＩチップ搭載部を示す上面透視
図である。FIG. 1 is a top perspective view showing an LSI chip mounting portion of a printed circuit board mounted with bare chips according to a first embodiment of the present invention.

【図２】 図１のベアチップ実装プリント配線板のＡ−
Ａ’断面図である。FIG. 2 is a cross-sectional view of a printed circuit board mounted with bare chips shown in FIG.
It is A 'sectional drawing.

【図３】 この発明の実施の形態２によるベアチップ実
装プリント配線板におけるＬＳＩチップ搭載部（１）を
示す上面透視図である。FIG. 3 is a top perspective view showing an LSI chip mounting portion (1) in a bare chip mounting printed wiring board according to Embodiment 2 of the present invention;

【図４】 図３のベアチップ実装プリント配線板のＢ−
Ｂ’断面図である。FIG. 4 is a cross-sectional view of a printed circuit board mounted with bare chips shown in FIG.
It is B 'sectional drawing.

【図５】 図３のベアチップ実装プリント配線板のＣ部
拡大図である。5 is an enlarged view of a portion C of the printed circuit board mounted with bare chips of FIG. 3;

【図６】 この発明の実施の形態２によるベアチップ実
装プリント配線板におけるＬＳＩチップ搭載部（２）を
示す上面透視拡大図である。FIG. 6 is an enlarged top perspective view showing an LSI chip mounting portion (2) in a bare chip mounting printed wiring board according to Embodiment 2 of the present invention;

【図７】 この発明の実施の形態２によるベアチップ実
装プリント配線板におけるＬＳＩチップ搭載部（３）を
示す上面透視拡大図である。FIG. 7 is an enlarged top perspective view showing an LSI chip mounting portion (3) in a bare chip mounted printed wiring board according to Embodiment 2 of the present invention;

【図８】 この発明の実施の形態２によるベアチップ実
装プリント配線板におけるＬＳＩチップ搭載部（４）を
示す上面透視拡大図である。FIG. 8 is an enlarged top perspective view showing an LSI chip mounting portion (4) in a bare chip mounted printed wiring board according to Embodiment 2 of the present invention;

【図９】 この発明の実施の形態２によるベアチップ実
装プリント配線板におけるＬＳＩチップ搭載部（５）を
示す上面透視拡大図である。FIG. 9 is an enlarged top perspective view showing an LSI chip mounting portion (5) in a bare chip mounting printed wiring board according to Embodiment 2 of the present invention;

【図１０】 この発明の実施の形態２によるベアチップ
実装プリント配線板におけるＬＳＩチップ搭載部（６）
を示す上面透視図である。FIG. 10 shows an LSI chip mounting portion (6) in a printed circuit board mounted with bare chips according to a second embodiment of the present invention.
FIG.

【図１１】 この発明の実施の形態２によるベアチップ
実装プリント配線板におけるＬＳＩチップ搭載部（７）
を示す上面透視図である。FIG. 11 is an LSI chip mounting part (7) in a bare chip mounted printed wiring board according to Embodiment 2 of the present invention;
FIG.

【図１２】 図１１のベアチップ実装プリント配線板の
Ｄ−Ｄ’断面図である。12 is a cross-sectional view of the bare chip-mounted printed wiring board taken along the line DD ′ of FIG. 11;

【図１３】 この発明の実施の形態２によるベアチップ
実装プリント配線板におけるＬＳＩチップ搭載部（８）
を示す上面透視拡大図である。FIG. 13 is an LSI chip mounting portion (8) in a bare chip mounted printed wiring board according to Embodiment 2 of the present invention;
FIG.

【図１４】 図１３のベアチップ実装プリント配線板の
Ｅ−Ｅ’断面図である。FIG. 14 is a cross-sectional view taken along line EE ′ of the bare-chip mounted printed wiring board of FIG. 13;

【図１５】 従来のベアチップ実装プリント配線板のＬ
ＳＩチップ搭載部を示す上面透視図である。FIG. 15 shows a conventional bare chip mounted printed wiring board L
FIG. 3 is a top perspective view showing an SI chip mounting portion.

【図１６】 図１５のベアチップ実装プリント配線板の
Ｆ−Ｆ’断面図である。FIG. 16 is a cross-sectional view taken along line FF ′ of the bare-chip mounted printed wiring board of FIG. 15;

【図１７】 従来の他の多層プリント配線板の平面図で
ある。FIG. 17 is a plan view of another conventional multilayer printed wiring board.

【符号の説明】[Explanation of symbols]

１ プリント配線板、２ パッド、３ ＬＳＩチップ、
４ 電極パッド５ 突起電極、６ プリント配線板の位
置ずれ確認用マーク、６ａ，６ｂ 認識マーク、７ Ｌ
ＳＩチップの位置ずれ確認用マーク、９ 銅箔。1 printed wiring board, 2 pads, 3 LSI chips,
4 electrode pad 5 protruding electrode, 6 mark for confirming displacement of printed wiring board, 6a, 6b recognition mark, 7L
Mark for confirming displacement of SI chip, 9 copper foil.

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 電極パッドを有する半導体チップとパッ
ドを有するプリント配線板とを備え、前記電極パッドを
前記パッドに接続して前記半導体チップを前記プリント
配線板に実装する半導体デバイスにおいて、前記半導体
チップを前記プリント配線板の正常位置に実装した状態
で前記半導体チップの電極パッドの形状および前記プリ
ント配線板のパッドの形状が相互にはみだして対称形状
を示すように形成されたことを特徴とする半導体デバイ
ス。1. A semiconductor device comprising: a semiconductor chip having an electrode pad; and a printed wiring board having a pad, wherein the semiconductor chip is mounted on the printed wiring board by connecting the electrode pad to the pad. Wherein the semiconductor device is formed in such a manner that the shape of the electrode pads of the semiconductor chip and the shape of the pads of the printed wiring board protrude from each other to show a symmetrical shape in a state where the semiconductor device is mounted on a normal position of the printed wiring board. device. 【請求項２】 パッドの一方向の寸法を電極パッドのそ
れより短くし、パッドの他方向の寸法を電極パッドのそ
れより長くしたことを特徴とする請求項１に記載の半導
体デバイス。2. The semiconductor device according to claim 1, wherein the dimension of the pad in one direction is shorter than that of the electrode pad, and the dimension of the pad in the other direction is longer than that of the electrode pad. 【請求項３】 電極パッドを有する半導体チップとパッ
ドを有するプリント配線板とを備え、前記電極パッドを
前記パッドに接続して前記半導体チップを前記プリント
配線板に実装する半導体デバイスにおいて、前記半導体
チップに任意の形状の第１のマークをＸ線を透過しない
材料で形成するとともに、前記プリント配線板に任意の
形状の第２のマークをＸ線を透過しない材料で形成し、
前記半導体チップを前記プリント配線板に実装した状態
で半導体チップのプリント配線板に対する位置関係が正
常な場合とずれている場合とで前記第１マークの第２の
マークに対する相対的位置関係を認識可能にしたことを
特徴とする半導体デバイス。3. A semiconductor device comprising: a semiconductor chip having an electrode pad; and a printed wiring board having a pad, wherein the semiconductor chip is mounted on the printed wiring board by connecting the electrode pad to the pad. Forming a first mark of any shape with a material that does not transmit X-rays, and forming a second mark of any shape on the printed wiring board with a material that does not transmit X-rays;
With the semiconductor chip mounted on the printed wiring board, the relative position of the first mark with respect to the second mark can be recognized depending on whether the positional relationship between the semiconductor chip and the printed wiring board is normal or not. A semiconductor device characterized in that: 【請求項４】 第１のマークおよび第２のマークは、半
導体チップをプリント配線板に実装した状態で一方のマ
ークが中心部を形成し、他のマークが中心部のマークを
囲う周辺部を形成してなることを特徴とする請求項３に
記載の半導体デバイス。4. A first mark and a second mark are formed in such a manner that one mark forms a central portion while the semiconductor chip is mounted on a printed wiring board, and the other mark surrounds the central portion. The semiconductor device according to claim 3, wherein the semiconductor device is formed.
JP9089333A 1997-04-08 1997-04-08 Semiconductor device Pending JPH10284812A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9089333A JPH10284812A (en) 1997-04-08 1997-04-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9089333A JPH10284812A (en) 1997-04-08 1997-04-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH10284812A true JPH10284812A (en) 1998-10-23

Family

ID=13967769

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9089333A Pending JPH10284812A (en) 1997-04-08 1997-04-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH10284812A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006502557A (en) * 2001-10-30 2006-01-19 クゥアルコム・インコーポレイテッド Ball-shaped grid array X-ray orientation mark
JP2007234872A (en) * 2006-03-01 2007-09-13 Fujikura Ltd Method and apparatus for positioning printed circuit board
WO2008072551A1 (en) * 2006-12-08 2008-06-19 Sharp Kabushiki Kaisha Ic chip-mounted package and image display device using the same
JP2008187202A (en) * 2008-04-24 2008-08-14 Sharp Corp IC chip mounting package and image display device having the same
US7999400B2 (en) * 2005-03-25 2011-08-16 Sharp Kabushiki Kaisha Semiconductor device with recessed registration marks partially covered and partially uncovered
WO2014002478A1 (en) * 2012-06-29 2014-01-03 オリンパス株式会社 Printed wiring board connection structure
US10720365B2 (en) 2016-07-20 2020-07-21 Samsung Electronics Co., Ltd. Method of measuring misalignment of chips, a method of fabricating a fan-out panel level package using the same, and a fan-out panel level package fabricated thereby
JP2021145041A (en) * 2020-03-12 2021-09-24 日本電気株式会社 Mounting structure and electronic apparatus

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006502557A (en) * 2001-10-30 2006-01-19 クゥアルコム・インコーポレイテッド Ball-shaped grid array X-ray orientation mark
JP2010103543A (en) * 2001-10-30 2010-05-06 Qualcomm Inc Ball-grid-array x-ray azimuthal mark
US7999400B2 (en) * 2005-03-25 2011-08-16 Sharp Kabushiki Kaisha Semiconductor device with recessed registration marks partially covered and partially uncovered
JP2007234872A (en) * 2006-03-01 2007-09-13 Fujikura Ltd Method and apparatus for positioning printed circuit board
WO2008072551A1 (en) * 2006-12-08 2008-06-19 Sharp Kabushiki Kaisha Ic chip-mounted package and image display device using the same
US8080823B2 (en) 2006-12-08 2011-12-20 Sharp Kabushiki Kaisha IC chip package and image display device incorporating same
CN101548372B (en) 2006-12-08 2012-04-18 夏普株式会社 IC chip-mounted package and image display device using the same
JP2008187202A (en) * 2008-04-24 2008-08-14 Sharp Corp IC chip mounting package and image display device having the same
WO2014002478A1 (en) * 2012-06-29 2014-01-03 オリンパス株式会社 Printed wiring board connection structure
JP2014011330A (en) * 2012-06-29 2014-01-20 Olympus Corp Connection structure for printed wiring boards
US10720365B2 (en) 2016-07-20 2020-07-21 Samsung Electronics Co., Ltd. Method of measuring misalignment of chips, a method of fabricating a fan-out panel level package using the same, and a fan-out panel level package fabricated thereby
JP2021145041A (en) * 2020-03-12 2021-09-24 日本電気株式会社 Mounting structure and electronic apparatus

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