JPH11110286A - Communication terminal device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communication terminal device that operates at high speed and with low cost. SOLUTION: Memories 24 and 25 that can be accessed to at low speed are provided outside a reduced instruction set computer 1 incorporating high speed memories 21 and 22 that can access at high speed, a program area and a work area requiring a high speed processing area allocated to the high speed memories 21 and 22 and the program area and the work area that do not require high speed processing are allocated to the low speed memories 24 and 25.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication terminal device using software processing, and more particularly to a communication terminal device which can operate at low cost and at high speed.

[0002]

2. Description of the Related Art A communication terminal such as a facsimile apparatus reads an original, encodes / decodes image data to code data, transmits / receives code data, modulates / demodulates code data to a signal for a line, and transmits / receives a signal. A variety of processing means are required to connect to the server, record received documents, process panel operations and displays, register and call telephone numbers, and control mechanical parts such as paper feeding. This is realized by dedicated hardware and software executed by a microcomputer. Conventionally, since the processing speed of the microcomputer was low, dedicated hardware was used for processing means requiring high-speed processing.

However, in recent years, as the processing speed of microcomputers has been improved, dedicated hardware has been abolished and replaced with software. Among microcomputers, a reduced instruction set computer (hereinafter referred to as RISC) has simplified instructions, can execute one instruction in one clock, and has a read-only memory (hereinafter referred to as ROM) and a readable / writable memory (hereinafter referred to as ROM). , RAM), and these memories can be accessed at high speed. By realizing processing means requiring high-speed processing by software using this RISC, it is possible to reduce the cost of parts and diversify the function of the apparatus by eliminating the restriction by hardware.

On the other hand, increasing the reading speed, communication speed, recording speed, and the like is a demand that does not stop. In a recent facsimile apparatus, the read image data is encoded into a storage code, and the storage code data is temporarily written in a memory, and the MH, MR, MMR
The data is converted to coded data and transmitted. Therefore,
To increase the reading speed, it is necessary to increase the encoding speed. To increase the recording speed, it is necessary not only to increase the operation speed of a mechanism such as a printer, but also to increase the speed of decoding encoded data into image data. The communication speed is required to be as high as 28.8 kbps or 33.6 kbps, but the transmission / reception process must be able to follow the communication speed.

Further, a facsimile machine is required to perform a plurality of processes at the same time. For example, it is required to transmit another document already stored in the memory while reading and storing the document in the memory. in this case,
Since encoding and decoding are performed in parallel, a plurality of hardware dedicated to encoding and decoding is required. In this regard, if software is used, the encoding process and the decoding process can be performed in parallel.

[0006]

By the way, RISC
Has a CPU, ROM, and RAM in an integrated chip, and thus has a limited memory capacity. On the other hand, if various types of processing are implemented as software as described above, many program areas and work areas are required, and cannot be accommodated in the memory in the RISC. Further, since the distribution of the ROM and the RAM in the chip is fixed, the capacity of the RAM cannot cover the data capacity of the facsimile.

In the prior art, in such a case, the RISC
External memory was added to compensate for the lack of memory capacity. However, an externally added memory cannot be accessed at a high speed like a built-in memory. For this reason,
The processing speed of software by RISC has become substantially slow, and it has been difficult to substitute for dedicated hardware. In addition, there is a memory that can be accessed at a high speed even if it does not reach the memory in the RISC. However, such a high-speed memory is expensive, and if a high-speed memory with a memory capacity that satisfies all program areas and work areas is increased. , The costs will rise.

[0008] Therefore, an object of the present invention is to solve the above problems and to provide a communication terminal device which operates at high speed at low cost.

[0009]

In order to achieve the above object, the present invention provides a low-speed memory which is accessed at a low speed outside a reduced instruction set computer having a high-speed memory which can be accessed at a high speed. A required program area and a work area are allocated to the high-speed memory, and a program area and a work area that do not require high-speed processing are allocated to the low-speed memory.

[0010] A program area and a work area for reading and writing communication data may be allocated to the high-speed memory.

A second high-speed memory is provided outside the reduced instruction computer, an encoding / decoding processing program area for image data is allocated to the built-in high-speed memory, and an encoding / decoding process is assigned to the second high-speed memory. May be allocated.

[0012]

An embodiment of the present invention will be described below in detail with reference to the accompanying drawings. In this embodiment, the communication terminal device is a facsimile device having a G3, G4 facsimile communication function. FIG. 1 shows a memory map of the facsimile apparatus. FIG. 2 shows a circuit configuration of the facsimile apparatus.

As shown in FIG. 2, the facsimile apparatus includes a main control unit 1, a display unit 2, an operation unit 3, a reading unit 4, a recording unit 5, an external memory 6, a modem 7, and a network control unit (NCU) 8.
It is composed of

The main control unit 1 is configured using RISC. RISC is capable of executing reduced instructions and high-speed RO
It has a built-in M and high-speed RAM, can access an externally added memory, and has a DMA function.
The main control unit 1 is connected to various hardware units described below via a bus. The main control unit 1 includes a soft codec (encoding and decoding from image data to encoded data), a monitor, a modem interrupt, an auto dialer, a communication procedure control (handshake with a partner facsimile machine, etc.), a printer control, a panel operation. It executes software for display processing, registration and calling of telephone numbers, and the like. The modem interrupt program reads and writes communication data transmitted to and received from the modem. The monitor program executes a program (task) for processing each of the above functions. Further, data can be directly transferred between an image processing circuit described later and a run-length buffer by the DMA function.

The display unit 2 includes a display such as an LCD, and can display the operation state of the facsimile apparatus, image data, operation instructions, and the like.

The operation unit 3 includes numeric keys for inputting numbers, speed dial keys for speed dial operation, one touch keys for one touch operation, various function keys, start keys, and the like. Registered contents such as abbreviated dialing and one touch are stored in a memory.

The reading section 4 comprises a CCD and an image processing circuit. The CCD reads an original, outputs an analog image signal, and performs image processing such as shading correction, edge enhancement, and γ correction. , And binarized into black and white binary image data. This image data can be converted to run length and output to the bus.

The recording section 5 includes a thermal head and a thermal head driver, and can perform print output by printer control software. Fonts for printing characters are stored in memory.

The external memory 6 will be described later together with the built-in memory.

The modem 7 modulates and demodulates the code data into a line signal. The function of this modem is converted into software, and a D / A converter for transmission and an A / D converter for reception are used.
An analog interface 7 'including a / D converter may be provided.

The NCU 8 performs connection / release of a line, detection of a call signal, and the like.

Next, the memory configuration will be described with reference to FIG.

As shown, the memory is a built-in high-speed ROM 21 of 64 Kbytes, a built-in high-speed RAM of 2 Kbytes,
External high-speed RAM consisting of 22, 64 Kbytes of SRAM
23, external low-speed ROM 24, 138K byte SRAM
And an external low-speed RAM 25.
The RISC executes one instruction of the reduced instruction in one clock. For one instruction cycle, the built-in high-speed ROM 21 and the built-in high-speed RAM 22 wait one cycle.
Can be accessed without. External high-speed RAM 23
Is accessed for two cycles without wait, and part 2
For 3a, the data cache is turned on, and one cycle can be made without wait. External low-speed ROM
24 can be accessed in two cycles and one wait. The external low-speed RAM 25 can be accessed with two cycles and one wait. These memories have D
It can also be used by the MA function.

In the area allocation to these memories, the program areas of the soft codec program, the modem interrupt program and the monitor program are allocated to the built-in high-speed ROM 21, and the program areas of the other programs are allocated to the external normal speed ROM 24. . The modem transmission / reception buffer in the work area used by the modem interrupt program has a built-in high-speed RAM 22.
The work area used by the soft codec program is assigned to the external high-speed RAM 23, and a run length buffer is assigned to the portion 23a in which the data cache is turned on. The other work areas are allocated to the external low-speed RAM 25. The soft codec program is obtained by optimizing a module described in the C language so as to be independent of the CPU model by a compiler for high-speed processing.

The operation of the facsimile apparatus shown in FIG. 2 will be described for the case of original transmission.

First, when a document is set on the reading section 4 and the start key of the operation section 3 is turned on, the main control section 1 controls a mechanism section (not shown) of the reading section 4 to read the document. To start. The CCD of the reading unit 4 outputs an analog image signal, and the image processing circuit binarizes the image data and converts the image data into a run length. When the run length for one line is formed in the image processing circuit, the main control unit 1 transfers the run length data of the image processing circuit to the run length buffer by the DMA function. The main control unit 1 encodes the run length into a code for accumulation by a soft codec program, and writes the code data for accumulation into a work area of the external high-speed RAM 23.

When the reading of the original is completed, the main controller 1
Sends a command to the NCU 8 to connect to the line, and dials a telephone number specified in advance from the operation unit 3. When the incoming call to the other party's facsimile apparatus and the handshake are completed, transmission of code data by the code system of the other party's facsimile apparatus is started.

The main control unit 1 decodes the storage code into a run length by a soft codec program, converts the run length into code data, and converts the run length into code data.
Write to the modem transmit / receive buffer. In addition, the monitor program reads out the code data in the modem transmission / reception buffer and transmits it to the modem.

Next, the case of receiving a document will be described.

When the NCU 8 detects the calling signal, the main control unit 1 performs a handshake with the other party's facsimile machine and starts the receiving process. The main control unit 1 writes the code data received by the modem into the modem transmission / reception buffer using the monitor program. In addition, the code data in the modem transmission / reception buffer is converted into a code for storage by a soft codec program and written into a work area of the external high-speed RAM 23. Further, the storage code is decoded into image data by the soft codec program, and the image data is transmitted to the recording unit 5. The main control unit 1 controls a mechanical unit (not shown) of the recording unit 5 to start recording a received document.

In the above document transmission / reception operation, since the program area and the work area of the modem interrupt and the monitor program requiring the highest speed processing are allocated to the built-in high-speed ROM 21 and the built-in high-speed RAM 22, the modem interrupt and the monitor program are Operates at the highest processing speed of RISC. Therefore, 28.8 kbps, 33.6 k
High speed communication such as bps can be performed without any trouble.
In addition, a soft codec program which requires high-speed processing after these programs has a program area allocated to the built-in high-speed ROM 21 and a work area allocated to the external high-speed RAM 23, so that the soft codec program operates at high speed. Other programs can operate without problems even if a low-speed memory is used.

[0032]

The present invention exhibits the following excellent effects.

(1) The shortage of memory capacity can be compensated for by using an inexpensive low-speed memory while effectively utilizing the high-speed processing capability of the RISC.

(2) Since a program area and a work area for communication processing that cannot be waited are accommodated in the RISC, high-speed communication can be performed.

(3) A program area for encoding / decoding processing requiring high-speed processing after communication processing is accommodated in the RISC, and only the work area is supplemented by an external high-speed memory, so that high-speed processing is achieved. The cost performance of the memory can be improved.

[Brief description of the drawings]

FIG. 1 is a memory map configuration diagram of a facsimile apparatus showing an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a facsimile apparatus showing one embodiment of the present invention.

[Explanation of symbols]

 21 Built-in high-speed ROM 22 Built-in high-speed RAM 23 External high-speed RAM (second high-speed memory) 24 External low-speed ROM 25 External low-speed RAM

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04N 1/41 G06F 15/64 450A

Claims (3)

[Claims] A low-speed memory which is accessed at a low speed is provided outside a reduced instruction set computer incorporating a high-speed memory which can be accessed at a high speed, and a program area and a work area requiring high-speed processing are allocated to the high-speed memory. A communication terminal device, wherein a program area and a work area that do not require a program are allocated to the low-speed memory. 2. The communication terminal device according to claim 1, wherein a program area and a work area for reading and writing communication data are allocated to the high-speed memory. 3. A second instruction external to the reduced instruction computer.
A high-speed memory, and allocates an image data encoding / decoding processing program area to the built-in high-speed memory,
3. The communication terminal device according to claim 1, wherein a work area for encoding / decoding processing is allocated to the second high-speed memory.