JPH11111890A - High frequency wiring board - Google Patents
High frequency wiring boardInfo
- Publication number
- JPH11111890A JPH11111890A JP9267581A JP26758197A JPH11111890A JP H11111890 A JPH11111890 A JP H11111890A JP 9267581 A JP9267581 A JP 9267581A JP 26758197 A JP26758197 A JP 26758197A JP H11111890 A JPH11111890 A JP H11111890A
- Authority
- JP
- Japan
- Prior art keywords
- signal transmission
- dielectric waveguide
- wiring board
- dielectric
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
Landscapes
- Structure Of Printed Boards (AREA)
- Waveguides (AREA)
Abstract
(57)【要約】
【課題】製造コストを低減させる。また、各種製品仕様
に適用できる高周波配線基板を提供する。
【解決手段】導体層が形成された誘電体基板内に信号波
長の1/2以下の間隔で多数のビアホール導体13、1
6を並べたビアホール導体群14、17を複数個配列
し、隣接するビアホール導体群14、17間を信号伝送
用線路15、18となす誘電体導波路体8、9を、隣接
する誘電体導波路体8、9間での信号伝送用線路15、
18の方向がほぼ直交されるように積み重ねて、上記導
体層内の孔に貫通させた給電体20、23、24により
双方の信号伝送用線路15、18間を接続せしめた高周
波配線基板7。
(57) [Summary] [PROBLEMS] To reduce manufacturing cost. Also, a high-frequency wiring board applicable to various product specifications is provided. A plurality of via-hole conductors (13, 1) are provided in a dielectric substrate on which a conductor layer is formed at an interval of 1/2 or less of a signal wavelength.
6, a plurality of via-hole conductor groups 14 and 17 in which the dielectric waveguides 8 and 9 forming signal transmission lines 15 and 18 between the adjacent via-hole conductor groups 14 and 17 are arranged. A signal transmission line 15 between the waveguides 8 and 9;
A high-frequency wiring board 7 stacked so that the directions of the signal transmission lines 18 are substantially orthogonal to each other and connected between the two signal transmission lines 15 and 18 by feeders 20, 23 and 24 penetrating through holes in the conductor layer.
Description
【0001】[0001]
【発明の属する技術分野】本発明は主にマイクロ波およ
びミリ波等の高周波信号を利用する半導体パッケージな
どの高周波配線基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency wiring board such as a semiconductor package utilizing high-frequency signals such as microwaves and millimeter waves.
【0002】[0002]
【従来の技術】従来、配線基板や半導体パッケージに形
成するマイクロ波やミリ波等の高周波信号伝送線路とし
て、マクロストリップ線路、ストリップ線路、コプレー
ナ線路、スロット線路等の平面型線路があるが、これら
平面型線路は簡単な構成であって、製造が容易である
が、その反面、30GHz以上になると伝送特性が劣化
するという問題点がある。2. Description of the Related Art Conventionally, as a high-frequency signal transmission line for microwaves or millimeter waves formed on a wiring board or a semiconductor package, there is a planar line such as a macrostrip line, a strip line, a coplanar line, and a slot line. The flat type line has a simple configuration and is easy to manufacture, but on the other hand, there is a problem that the transmission characteristics are degraded at 30 GHz or more.
【0003】かかる問題点を解決して、ミリ波領域でも
優れた伝送特性を達成するために、図5や図6に示すよ
うな誘電体導波路構造が提案されている。図5の誘電体
導波路構造Aによれば、誘電体層1の両主面に導体層
2、3を形成し、これら導体層2、3間を接続する二列
の複数のビアホール導体4によって側壁を形成し、これ
ら側壁によって囲まれる誘電体層1の領域を信号伝送用
線路5としている(特開平6−53711号参照)。In order to solve such a problem and achieve excellent transmission characteristics even in the millimeter wave region, a dielectric waveguide structure as shown in FIGS. 5 and 6 has been proposed. According to the dielectric waveguide structure A of FIG. 5, the conductor layers 2 and 3 are formed on both main surfaces of the dielectric layer 1, and the two rows of via-hole conductors 4 connecting the conductor layers 2 and 3 form the conductor layers. Side walls are formed, and a region of the dielectric layer 1 surrounded by the side walls is used as a signal transmission line 5 (see JP-A-6-53711).
【0004】また、本発明者等が提案した図6に示す誘
電体導波路構造Bにおいては、上記誘電体導波路構造A
の誘電体層1を複数の誘電体層6で形成し、各誘電体層
6を副導体層7を介して積層している。そして、この副
導体層7によってビアホール導体4が配列された側壁に
対し、電気的な壁として強化され、伝送特性が向上する
(特願平8−15723号参照)。Further, in the dielectric waveguide structure B shown in FIG. 6 proposed by the present inventors, the dielectric waveguide structure A
Is formed of a plurality of dielectric layers 6, and the respective dielectric layers 6 are stacked via a sub-conductor layer 7. The side wall on which the via-hole conductors 4 are arranged is reinforced by the sub-conductor layer 7 as an electric wall, and the transmission characteristics are improved (see Japanese Patent Application No. 8-15723).
【0005】かくして上記構成の誘電体導波路構造A、
Bによれば、ミリ波領域においても優れた伝送特性が得
られ、しかも、平面内での線路の引き回しを任意におこ
なうことができ、さらに従来の誘電体シート積層化技術
を用いて容易に作製でき、これにより、配線基板または
半導体パッケージに用いる高周波信号に適した誘電体導
波路が得られた。Thus, the dielectric waveguide structure A having the above structure,
According to B, excellent transmission characteristics can be obtained even in the millimeter-wave region, and the line can be routed arbitrarily in the plane, and can be easily manufactured using the conventional dielectric sheet lamination technology. As a result, a dielectric waveguide suitable for a high-frequency signal used for a wiring board or a semiconductor package was obtained.
【0006】[0006]
【発明が解決しようとする課題】しかしながら、上記誘
電体導波路構造A、Bにおいては、信号伝送用線路5を
引き回す場合、その側面に多数のビアホール導体、たと
えば数千個から数万個のビアホール導体4を配列するの
で、下記のような問題点がある。However, in the dielectric waveguide structures A and B, when the signal transmission line 5 is routed, a large number of via-hole conductors, for example, thousands to tens of thousands of via-holes are provided on the side surface. Since the conductors 4 are arranged, there are the following problems.
【0007】ビアホール導体は、誘電体シートにマイク
ロドリル、レーザ、打ち抜きにより加工して、ビアホー
ルをつくり、ついで印刷技術によりビアホールに導体ペ
ーストを埋め込んで形成する。これら加工方法にうち、
マイクロドリルを用いた場合では、ある程度の厚みの誘
電体層でも加工できるが、順次形成するので生産効率が
低いという問題がある。これに対して、レーザによる穴
加工では、高速でおこなうことができるが、その反面、
レーザ照射のための装置が非常に高価である。そこで、
通常、金属ピンによる打ち抜き加工が用いられている。The via hole conductor is formed by forming a via hole by processing a dielectric sheet by microdrilling, laser, or punching, and then embedding a conductive paste in the via hole by a printing technique. Among these processing methods,
In the case of using a micro drill, a dielectric layer having a certain thickness can be processed, but there is a problem in that the production efficiency is low because the layers are formed sequentially. In contrast, laser drilling can be performed at high speed, but on the other hand,
Equipment for laser irradiation is very expensive. Therefore,
Usually, a punching process using a metal pin is used.
【0008】この打ち抜き加工には2とおりあり、一つ
のピンでもって穴を一つずつ順次空けていくという方法
と、所定の位置に多数のピンを予め取り付けた治具を作
製し、一つのシートに対し、同時にすべての穴を空ける
という方法とがある。前者の方法では、入力された数値
データによって穴加工位置が決められるので、どのよう
な配列加工でも可能となるが、加工の所要時間が長いと
いう問題点がある。後者の方法では、非常に効率よく打
ち抜き加工ができるが、ピンが一本でも折れると治具を
交換する必要があり、製造コスト上問題である。さら
に、双方の加工方法を組み合わせた方法も考えられ、一
シート内のビアホールを数ブロックに分割し、各ブロッ
ク毎に多数のピンを備えた治具を用意すれば、一つの治
具のコストが低減でき、さらに加工時間も短縮できる。
しかしながら、さまざまなパターンで伝送回路を引き回
し、製品毎にパターンが異なれば、非常に多数の治具が
必要となり、その結果、製造コストが増大する。There are two types of punching. One method is to make holes one by one with one pin, and another method is to make a jig in which a number of pins are attached at predetermined positions in advance, and to make one sheet. On the other hand, there is a method of making all holes at the same time. In the former method, since the hole processing position is determined by the input numerical data, any arrangement processing is possible, but there is a problem that the processing time is long. In the latter method, punching can be performed very efficiently, but if even one pin is broken, the jig needs to be replaced, which is a problem in terms of manufacturing cost. Furthermore, a method combining both processing methods is also conceivable. If a via hole in one sheet is divided into several blocks and a jig having a large number of pins is prepared for each block, the cost of one jig is reduced. The processing time can be reduced.
However, when the transmission circuit is routed in various patterns and the pattern is different for each product, a very large number of jigs are required, and as a result, the manufacturing cost increases.
【0009】本発明者は上記事情に鑑みて鋭意研究に努
めた結果、多数のビアホール導体を所定の方向に並べた
ビアホール導体群を複数個配列し、隣接するビアホール
導体群間を信号伝送用線路となす誘電体導波路体を打ち
抜き加工で複数個作製し、信号伝送用線路間を接続する
ように、それらを積み重ねた高周波配線基板であれば、
個々の誘電体導波路体に対し信号伝送用線路を規定する
だけで、さまざまな製品仕様に適用でき、製造コストが
低減されることを見出した。The inventor of the present invention has made intensive studies in view of the above circumstances. As a result, a plurality of via-hole conductor groups in which a large number of via-hole conductors are arranged in a predetermined direction are arranged, and a signal transmission line is provided between adjacent via-hole conductor groups. A plurality of dielectric waveguides to be formed by punching, and a high-frequency wiring board in which they are stacked so as to connect between signal transmission lines,
It has been found that simply by defining a signal transmission line for each dielectric waveguide body, it can be applied to various product specifications and the manufacturing cost can be reduced.
【0010】したがって、本発明は上記知見により完成
されたものであって、その目的は製造コストを低減させ
るとともに、各種製品仕様に適用できる高周波配線基板
を提供することにある。Accordingly, the present invention has been completed based on the above findings, and an object of the present invention is to provide a high-frequency wiring board that can be applied to various product specifications while reducing manufacturing costs.
【0011】[0011]
【課題を解決するための手段】本発明の高周波配線基板
は、両主面に導体層が形成された誘電体基板の厚み方向
に信号波長の1/2未満の間隔で多数のビアホール導体
を一定方向に並べたビアホール導体群を3列以上配設
し、隣接するビアホール導体群間が信号伝送用線路とな
る第1の誘電体導波路体と同様の第2の誘電体導波路体
とを、双方の信号伝送用線路の方向がほぼ直交するよう
に積層した誘電体導波路体間の導体層に開口部を設け、
この開口部に給電体を貫通させて双方の信号伝送用線路
を接続せしめたことを特徴とする。According to the high-frequency wiring board of the present invention, a large number of via-hole conductors are fixed at intervals of less than 1/2 of a signal wavelength in a thickness direction of a dielectric board having conductor layers formed on both main surfaces. A second dielectric waveguide similar to the first dielectric waveguide, in which three or more rows of via-hole conductor groups arranged in the same direction are arranged and adjacent via-hole conductor groups serve as signal transmission lines; An opening is provided in the conductor layer between the dielectric waveguides stacked so that the directions of both signal transmission lines are substantially orthogonal to each other,
The present invention is characterized in that both of the signal transmission lines are connected by penetrating a feeder through the opening.
【0012】[0012]
【発明の実施の形態】以下、本発明を図1〜図4により
詳述する。図1は本発明の高周波配線基板7の破断面分
解図であり、図2は図1中の切断面線X−Xによる断面
図である。また、図3は本発明の高周波配線基板を構成
する個々の誘電体導波路体の平面図、図4は本発明の高
周波配線基板をアレーアンテナの給電回路に用いた場合
の個々の誘電体導波路体の平面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to FIGS. FIG. 1 is an exploded cross-sectional view of the high-frequency wiring board 7 of the present invention, and FIG. 2 is a cross-sectional view taken along the line XX in FIG. FIG. 3 is a plan view of each dielectric waveguide constituting the high-frequency wiring board of the present invention. FIG. 4 is a plan view of each dielectric waveguide when the high-frequency wiring board of the present invention is used for a feed circuit of an array antenna. It is a top view of a wave body.
【0013】図1と図2に示す高周波配線基板7によれ
ば、2種類の誘電体導波路体8、9を積み重ねたもので
あって、それぞれの両主面には通常、グランド層と呼ば
れる導体層10、11、12が形成されている。なお、
導体層11は双方の誘電体導波路体8、9の共通の導体
層である。According to the high-frequency wiring board 7 shown in FIGS. 1 and 2, two types of dielectric waveguides 8 and 9 are stacked, and both main surfaces are usually called ground layers. Conductive layers 10, 11, and 12 are formed. In addition,
The conductor layer 11 is a common conductor layer of both the dielectric waveguide bodies 8 and 9.
【0014】誘電体導波路体8においては、信号波長の
1/2未満の間隔で多数のビアホール導体13をx方向
に並べられ、これによってビアホール導体群14とな
し、これらビアホール導体群14もx方向に複数個配列
されている。そして、これら隣接するビアホール導体群
14間を信号伝送用線路15となす。In the dielectric waveguide 8, a large number of via-hole conductors 13 are arranged in the x-direction at intervals of less than 1 / of the signal wavelength, whereby a via-hole conductor group 14 is formed. A plurality are arranged in the direction. A signal transmission line 15 is formed between the adjacent via-hole conductor groups 14.
【0015】他方の誘電体導波路体9においても、信号
波長の1/2未満の間隔で多数のビアホール導体16を
y方向に、すなわちx方向と直交するように並べられ、
これによってビアホール導体群17となし、これらビア
ホール導体群17もy方向に複数個配列され、隣接する
ビアホール導体群17間を信号伝送用線路18となす。Also in the other dielectric waveguide 9, a large number of via-hole conductors 16 are arranged in the y-direction, that is, orthogonal to the x-direction at intervals of less than half the signal wavelength.
As a result, the via-hole conductor group 17 is formed, and a plurality of the via-hole conductor groups 17 are arranged in the y-direction. A signal transmission line 18 is formed between the adjacent via-hole conductor groups 17.
【0016】上記導体層10には前記開口部としての穴
19が形成され、この穴19にはそれと非接触となるよ
うに給電体20を貫通させている。同様に導体層11、
12にも穴21、22が貫通され、それぞれ非接触のま
まで給電体23、24を貫通させている。これら給電体
20、23、24はたとえばピン形状にする。A hole 19 is formed in the conductor layer 10 as the opening, and a power supply 20 is passed through the hole 19 so as not to be in contact therewith. Similarly, the conductor layer 11,
Holes 21 and 22 are also penetrated through 12, and the power supply bodies 23 and 24 are penetrated without contact. These power supply bodies 20, 23, 24 are, for example, pin-shaped.
【0017】上記構成の高周波配線基板7においては、
給電体24に高周波信号を入力すると、誘電体導波路体
9の信号伝送用線路18を伝播し、給電体23を通じて
誘電体導波路体8の信号伝送用線路15を伝播し、給電
体20より出力される。In the high-frequency wiring board 7 having the above structure,
When a high-frequency signal is input to the feeder 24, the signal propagates through the signal transmission line 18 of the dielectric waveguide 9, propagates through the feeder 23 through the signal transmission line 15 of the dielectric waveguide 8, and Is output.
【0018】この高周波配線基板7によれば、ビアホー
ル導体13、16を信号波長の1/2未満の間隔で、好
適には1/4程度の間隔で並べるとよく、これによっ
て、信号の伝送方向に対して垂直方向に電気的な壁が形
成され、その結果、信号(電磁波)が信号伝送用線路1
5、18の方向にのみ良好に伝播される疑似的な導波管
となる。According to the high-frequency wiring board 7, the via-hole conductors 13 and 16 may be arranged at intervals of less than 1/2 of the signal wavelength, preferably at intervals of about 1/4. An electric wall is formed in a direction perpendicular to the transmission line 1 so that a signal (electromagnetic wave) is
It becomes a pseudo waveguide that propagates well only in directions 5 and 18.
【0019】そして、このような構成の高周波配線基板
7には、導体層12の上に誘電体層を形成し、その上部
にマイクロストリップ線路、コプレーナ線路またはプリ
ント型のアンテナ素子を形成してもよい。また、上記信
号伝送用線路15、18においては、それぞれ給電体2
4から左右双方向に伝播されるので、一方の伝播に対し
ては反射機能をもたせたビアホール導体は配して、それ
によって反射した高周波信号と、他方に伝播される高周
波信号とを組み合わせている。その場合、両者の電磁波
の位相が合うように給電体から管内波長の1/4程度の
位置に、かかる反射機能のビアホール導体を配するとよ
い。In the high-frequency wiring board 7 having such a configuration, a dielectric layer is formed on the conductor layer 12, and a microstrip line, a coplanar line, or a printed antenna element is formed thereon. Good. In the signal transmission lines 15 and 18, the feeder 2
Since the light is propagated from left to right in both directions, via-hole conductors having a reflection function for one propagation are arranged, and the high-frequency signal reflected thereby and the high-frequency signal propagated to the other are combined. . In this case, a via-hole conductor having such a reflection function may be arranged at a position about one-fourth of the guide wavelength from the power supply so that the phases of the electromagnetic waves are the same.
【0020】図3に示す回路接続例によれば、Aは誘電
体導波路体8の平面図、Bは誘電体導波路体9の平面図
である。また、白丸および黒丸はいずれも導体層10、
11、12に設けた孔19、21、22を示し、白丸は
誘電体導波路体8や誘電体導波路体9のそれぞれの線路
と下層の誘電体導波路体の線路とを接続する給電部、黒
丸は誘電体導波路体8や誘電体導波路体9のそれぞれの
線路と上層の誘電体導波路とを接続する給電部を示す。According to the circuit connection example shown in FIG. 3, A is a plan view of the dielectric waveguide 8 and B is a plan view of the dielectric waveguide 9. In addition, both open circles and black circles represent the conductor layer 10,
Holes 19, 21 and 22 provided in 11 and 12 are shown, and white circles indicate feed portions for connecting the respective lines of the dielectric waveguide body 8 and the dielectric waveguide body 9 to the lines of the lower dielectric waveguide body. , Black circles indicate feed sections that connect the respective lines of the dielectric waveguide body 8 and the dielectric waveguide body 9 to the upper dielectric waveguide.
【0021】まず、誘電体導波路体8の裏面から誘電体
導波路体9の上面への給電経路を示すと、誘電体導波路
体8の裏面より給電体20aを通して信号伝送用線路1
5aに信号として給電される。この信号は信号伝送用線
路15aをy方向に伝播され、給電体23aを通して誘
電体導波路体9の信号伝送用線路18bに給電され、x
方向に伝播して給電体24aより誘電体導波路体9の上
面まで接続される。First, a power supply path from the back surface of the dielectric waveguide body 8 to the upper surface of the dielectric waveguide body 9 will be described. The signal transmission line 1 from the back surface of the dielectric waveguide body 8 through the power supply body 20a is shown.
5a is supplied as a signal. This signal is propagated in the signal transmission line 15a in the y-direction, fed to the signal transmission line 18b of the dielectric waveguide body 9 through the feeder 23a, and
It propagates in the direction and is connected from the feeder 24 a to the upper surface of the dielectric waveguide 9.
【0022】また、誘電体導波路体9の上面から誘電体
導波路体9の上面の他の位置への給電経路を示すと、誘
電体導波路体9の上面において、給電体24bを通して
x方向の信号伝送用線路18cに信号として給電され
る。つぎに給電体23bを通してy方向の信号伝送用線
路15bに伝播され、給電体23cを通してx方向の信
号伝送用線路18dに信号として給電される。そして、
給電体24cを通して誘電体導波路体9の上面に給電さ
れる。A power supply path from the upper surface of the dielectric waveguide body 9 to another position on the upper surface of the dielectric waveguide body 9 is shown. Is supplied as a signal to the signal transmission line 18c. Next, the signal is propagated to the signal transmission line 15b in the y direction through the power supply 23b, and supplied as a signal to the signal transmission line 18d in the x direction through the power supply 23c. And
Power is supplied to the upper surface of the dielectric waveguide body 9 through the power supply 24c.
【0023】なお、図3の回路接続例において、さらに
信号伝送用線路15、18の中央部に電源線Kを形成し
てもよく、これにより、同軸タイプの線路となり、電源
線に不要なノイズが乗らなくなる。このような電源線K
の接続も同様にビアホール導体により接続する。In the circuit connection example of FIG. 3, a power supply line K may be further formed at the center of the signal transmission lines 15 and 18, whereby the power supply line becomes a coaxial type line, and unnecessary noises in the power supply line. Will not get on. Such a power line K
Are similarly connected by via-hole conductors.
【0024】つぎに図4にアレーアンテナの給電回路例
を示す。同図によれば、誘電体導波路体8の裏面におい
て給電体20bを通して信号伝送用線路15cに信号と
して給電される。この信号は2分され、一方の信号は給
電体23dに通される。なお、図4において上下対称の
給電関係であるので、下方の給電回路についてのみ説明
する。この給電体23dを経由した信号は2分され、一
方は給電体23eへ、他方は給電体23fへ伝播され
る。それぞれの信号は信号伝送用線路15d、15eへ
通じるが、図4において左右対称の給電関係となるの
で、左側のものは略す。つぎに信号伝送用線路15eを
通る信号は給電体23g、23hを通して2分され、信
号伝送用線路18f、18gにいたる。そして、各信号
伝送用線路18f、18gよりそれぞれ給電体24d、
24e、24f、24gを通して外部に配設したアンテ
ナ素子に接続され、このアンテナ素子に信号が給電され
る。Next, FIG. 4 shows an example of a feed circuit of the array antenna. According to the figure, power is supplied as a signal to the signal transmission line 15c through the feeder 20b on the back surface of the dielectric waveguide body 8. This signal is divided into two, and one signal is passed to the power supply 23d. In addition, since the power supply relationship is vertically symmetric in FIG. 4, only the lower power supply circuit will be described. The signal passing through the power supply 23d is divided into two, one of which is transmitted to the power supply 23e and the other is transmitted to the power supply 23f. The respective signals pass through the signal transmission lines 15d and 15e, but since they have a symmetrical power supply relationship in FIG. 4, those on the left side are omitted. Next, the signal passing through the signal transmission line 15e is divided into two by the feeders 23g and 23h, and reaches the signal transmission lines 18f and 18g. Then, the feeders 24d, 24d, from the signal transmission lines 18f, 18g, respectively.
The antenna element is connected to an externally arranged antenna element through 24e, 24f, and 24g, and a signal is supplied to the antenna element.
【0025】つぎに本発明の高周波配線基板7の製造方
法を述べる。誘電体導波路体8、9はアルミナセラミッ
クスやガラスセラミックス、窒化アルミニウムセラミッ
クス等の誘電体材料からなるが、アルミナセラミックス
からなる場合、アルミナ、シリカ、マグネシア等のセラ
ミックス原料粉末に適当な有機溶剤、溶媒を添加混合
し、ドクターブレード法や圧延法によってシート状成形
体(グリーンシート)を作製し、このセラミックグリー
ンシートの表面に、導体層10、11、12としてタン
グステン、モリブデン等の金属粉末を含む導電べ一スト
を従来周知の厚膜印刷法等を採用することによって5〜
25μmの厚みをもって印刷・塗布する。同時にセラミ
ックグリーンシートに予め開けておいたビアホール導体
13、16用の穴に導電ペーストを埋め込み、セラミツ
クグリーンシートと同時に焼成(約1600℃)するこ
とによって誘電体導波路体8と誘電体導波路体9との積
層構造である高周波配線基板7をなす。Next, a method for manufacturing the high-frequency wiring board 7 of the present invention will be described. The dielectric waveguides 8 and 9 are made of a dielectric material such as alumina ceramics, glass ceramics, or aluminum nitride ceramics. When the dielectric waveguides 8 and 9 are made of alumina ceramics, an organic solvent or solvent suitable for a ceramic raw material powder such as alumina, silica, and magnesia is used. , And a sheet-shaped formed body (green sheet) is produced by a doctor blade method or a rolling method, and conductive layers containing metal powders such as tungsten and molybdenum as conductor layers 10, 11, and 12 on the surface of the ceramic green sheet. By adopting a conventionally well-known thick film printing method or the like,
Print and apply with a thickness of 25 μm. At the same time, a conductive paste is buried in the holes for the via-hole conductors 13 and 16 previously opened in the ceramic green sheet, and baked (about 1600 ° C.) simultaneously with the ceramic green sheet to form the dielectric waveguides 8 and 8. 9 to form a high-frequency wiring board 7 having a laminated structure.
【0026】上記のようにグリーンシートに多数の孔を
配列形成するには、所要とおりのビアホール導体配列を
得るために、その配列に対応する所定の位置に多数のピ
ンを予め取り付けた治具を作製し、この治具を用いた打
ち抜き加工でもって複数個作製すると、いずれも誘電体
導波路体8、9の双方に使用することができる。そし
て、各誘電体導波路体8、9に応じた仕様にするために
は、さらに給電体20、23、24などのように所定に
位置に設けるために別の仕様で穴を設ける。たとえば、
各誘電体導波路体8、9をそれぞれ3層のグリーンシー
トにより構成して、個々の層の積層にともなって適宜ビ
アホール導体を形成することで、所要とおりの給電体2
0、23、24を設けることができる。In order to form a large number of holes in the green sheet as described above, in order to obtain a required via-hole conductor arrangement, a jig in which a large number of pins are previously mounted at predetermined positions corresponding to the arrangement is required. When a plurality of the waveguides are manufactured and punched using this jig, a plurality of them can be manufactured for both of the dielectric waveguides 8 and 9. Then, in order to obtain specifications corresponding to the respective dielectric waveguides 8 and 9, holes are provided according to different specifications so as to be provided at predetermined positions such as feeders 20, 23 and 24. For example,
Each of the dielectric waveguides 8 and 9 is formed of a three-layer green sheet, and a via-hole conductor is appropriately formed in accordance with the lamination of the individual layers.
0, 23, 24 can be provided.
【0027】かくして上記のように製造することで、ビ
アホール導体配列を形成するまでは、各誘電体導波路体
に対して共通のものを使用することができ、さらに用途
に応じて給電体用の穴を形成するので、さまざまな製品
仕様に適用でき、製造コストが低減される。By manufacturing as described above, a common one can be used for each dielectric waveguide until the via-hole conductor array is formed. Since the hole is formed, it can be applied to various product specifications, and the manufacturing cost is reduced.
【0028】なお、本発明は上記実施形態例に限定され
るものではなく、本発明の要旨を逸脱しない範囲内で種
々の変更や改良等は何ら差し支えない。たとえばこの実
施形態例では、二つの誘電体導波路体を積層したが、3
個もしくはそれ以上の誘電体導波路体を重ねてもよい。
また、給電体としてピン形状のビアホール導体で構成し
たが、これに代えて積層構造の上層と下層において、双
方の間に共有して配した導体層の一部にスロットや孔を
空けて給電体となし、これによって接続してもよい。It should be noted that the present invention is not limited to the above embodiment, and various changes and improvements may be made without departing from the spirit of the present invention. For example, in this embodiment, two dielectric waveguides are stacked,
One or more dielectric waveguides may be stacked.
In addition, the feeder is constituted by a pin-shaped via-hole conductor. Instead of this, the feeder is formed by forming a slot or hole in a part of the conductor layer shared between the upper and lower layers of the laminated structure. The connection may be made by this.
【0029】[0029]
【発明の効果】以上のとおり、本発明の高周波配線基板
によれば、多数のビアホール導体を所定の方向に並べた
ビアホール導体群を複数個配列し、隣接するビアホール
導体群間を信号伝送用線路となす誘電体導波路体を、隣
接する誘電体導波路体間での信号伝送用線路の方向がほ
ぼ直交されるように積み重ねて、上記導体層内の開口部
に貫通させた給電体により双方の信号伝送用線路間を接
続させている。このような構成にしたことで、各誘電体
導波路体に対し共通な打ち抜き加工でき、これにより、
製造コストが著しく低減される。さらに従来では一つの
信号伝送用線路に対し2列のビアホール導体群を形成し
なければならなかったが、本発明においては、隣接する
信号伝送用線路間で共通のビアホール導体群を使用する
ので、信号伝送用線路の数に対するビアホール導体群の
数が減少し、これによっても製造コストが低減できた。As described above, according to the high-frequency wiring board of the present invention, a plurality of via-hole conductor groups in which a large number of via-hole conductors are arranged in a predetermined direction are arranged, and a signal transmission line is provided between adjacent via-hole conductor groups. Are stacked so that the directions of the signal transmission lines between adjacent dielectric waveguides are substantially orthogonal to each other, and both are provided by a feeder penetrated through the opening in the conductor layer. Are connected between the signal transmission lines. With such a configuration, a common punching process can be performed for each dielectric waveguide body.
Manufacturing costs are significantly reduced. Furthermore, conventionally, two rows of via-hole conductor groups had to be formed for one signal transmission line, but in the present invention, a common via-hole conductor group is used between adjacent signal transmission lines. The number of via-hole conductor groups with respect to the number of signal transmission lines was reduced, which also reduced the manufacturing cost.
【0030】また、本発明によれば、個々の誘電体導波
路体に対し信号伝送用線路を規定するだけで、さまざま
な製品仕様に適用できる高周波配線基板が提供でき、た
とえばマイクロ波やミリ波等の高周波信号を利用した通
信システム、IDカードシステム、無線LAN、車載レ
ーダー等のシステムの開発に伴って、これらの機器に使
用される高周波素子収納用パッケージなどの高周波配線
基板が提供できた。Further, according to the present invention, it is possible to provide a high-frequency wiring board applicable to various product specifications simply by defining a signal transmission line for each dielectric waveguide body. With the development of communication systems, ID card systems, wireless LANs, vehicle-mounted radars, and the like using high-frequency signals, high-frequency wiring boards such as high-frequency element storage packages used for these devices have been provided.
【図1】本発明の高周波配線基板の分解破断面図であ
る。FIG. 1 is an exploded sectional view of a high-frequency wiring board according to the present invention.
【図2】図1中の切断面線X−Xによる断面図である。FIG. 2 is a cross-sectional view taken along line XX of FIG. 1;
【図3】AおよびBは本発明の高周波配線基板を構成す
る個々の誘電体導波路体の平面図である。FIGS. 3A and 3B are plan views of individual dielectric waveguides constituting the high-frequency wiring board of the present invention.
【図4】AおよびBは本発明の高周波配線基板を構成す
る個々の誘電体導波路体の平面図である。FIGS. 4A and 4B are plan views of individual dielectric waveguides constituting the high-frequency wiring board of the present invention.
【図5】従来の誘電体導波路構造の斜視図である。FIG. 5 is a perspective view of a conventional dielectric waveguide structure.
【図6】従来の誘電体導波路構造の斜視図である。FIG. 6 is a perspective view of a conventional dielectric waveguide structure.
7 高周波配線基板 8、9 誘電体導波路体 10、11、12 導体層 13、16 ビアホール導体 14、17 ビアホール導体群 15、18 信号伝送用線路 19、21、22 穴 20、23、24 給電体 7 High frequency wiring board 8, 9 Dielectric waveguide body 10, 11, 12 Conductive layer 13, 16 Via hole conductor 14, 17 Via hole conductor group 15, 18 Signal transmission line 19, 21, 22 Hole 20, 23, 24 Feeder
Claims (1)
厚み方向に信号波長の1/2未満の間隔で多数のビアホ
ール導体を一定方向に並べたビアホール導体群を3列以
上配設し、隣接するビアホール導体群間が信号伝送用線
路となる第1の誘電体導波路体と同様の第2の誘電体導
波路体とを、双方の信号伝送用線路の方向がほぼ直交す
るように積層した誘電体導波路体間の導体層に開口部を
設け、この開口部に給電体を貫通させて双方の信号伝送
用線路を接続せしめた高周波配線基板。1. A via hole conductor group comprising a plurality of via hole conductors in which a large number of via hole conductors are arranged in a fixed direction at intervals of less than 1/2 of a signal wavelength in a thickness direction of a dielectric substrate having a conductor layer formed on both main surfaces. And a second dielectric waveguide similar to the first dielectric waveguide between adjacent via-hole conductor groups, which is a signal transmission line, in which the directions of both signal transmission lines are substantially orthogonal to each other. A high-frequency wiring board in which an opening is provided in the conductor layer between the dielectric waveguide bodies stacked as described above, and a feeder is penetrated through the opening to connect both signal transmission lines.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26758197A JP3398311B2 (en) | 1997-09-30 | 1997-09-30 | High frequency wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26758197A JP3398311B2 (en) | 1997-09-30 | 1997-09-30 | High frequency wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11111890A true JPH11111890A (en) | 1999-04-23 |
| JP3398311B2 JP3398311B2 (en) | 2003-04-21 |
Family
ID=17446769
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26758197A Expired - Fee Related JP3398311B2 (en) | 1997-09-30 | 1997-09-30 | High frequency wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3398311B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000261215A (en) * | 1999-03-10 | 2000-09-22 | Nippon Telegr & Teleph Corp <Ntt> | Microwave / millimeter wave waveguide and integrated circuit using the same |
| US6968199B2 (en) | 2001-05-22 | 2005-11-22 | Nec Corporation | Schedule notifying system capable of correcting schedule date and time |
| JP2012028498A (en) * | 2010-07-22 | 2012-02-09 | Nec Corp | Circuit substrate having noise suppression structure |
| JP2012209655A (en) * | 2011-03-29 | 2012-10-25 | Mitsubishi Electric Corp | Multi-layer wave guide and manufacturing method of the same |
| JP2015149430A (en) * | 2014-02-07 | 2015-08-20 | 株式会社フジクラ | Microwave / millimeter-wave module and method for manufacturing microwave / millimeter-wave module |
-
1997
- 1997-09-30 JP JP26758197A patent/JP3398311B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000261215A (en) * | 1999-03-10 | 2000-09-22 | Nippon Telegr & Teleph Corp <Ntt> | Microwave / millimeter wave waveguide and integrated circuit using the same |
| US6968199B2 (en) | 2001-05-22 | 2005-11-22 | Nec Corporation | Schedule notifying system capable of correcting schedule date and time |
| JP2012028498A (en) * | 2010-07-22 | 2012-02-09 | Nec Corp | Circuit substrate having noise suppression structure |
| JP2012209655A (en) * | 2011-03-29 | 2012-10-25 | Mitsubishi Electric Corp | Multi-layer wave guide and manufacturing method of the same |
| JP2015149430A (en) * | 2014-02-07 | 2015-08-20 | 株式会社フジクラ | Microwave / millimeter-wave module and method for manufacturing microwave / millimeter-wave module |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3398311B2 (en) | 2003-04-21 |
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