JPH11112887A - Driving circuit for ccd - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent vertical stripe noise in a screen image picked up by a CCD(charge coupled device). SOLUTION: A blanking period detection circuit 8 detects a blanking period, closes a switch 9, impresses a system clock to a pulse signal generation circuit 3 and makes pulse signals be generated. Also, when a non-blanking period is detected, the switch 9 is opened, the system clock is interrupted and the signals of a fixed level are generated instead of the pulse signals. The system clock is supplied only in the blanking period and the system clock is interrupted in the non-blanking period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a CCD driving circuit with improved image quality of a monitor section.

[0002]

2. Description of the Related Art Generally, CCDs are used as charge transfer devices.
(Charge Coupled Dvice) is known, and a CCD is well known as a device for converting an incident light beam into a voltage and taking an image. There are mainly a frame transfer method and an image pickup apparatus using the CCD, and the frame transfer method will be described. The light beam incident on the CCD is converted into a voltage mainly through the following five processes. First, a light beam of a subject incident on an imaging unit of a CCD is converted into an electric charge by a photodiode constituting the CCD (photoelectric conversion process). The charge photoelectrically converted in the process 1 is at a timing of a first predetermined rate (for example, every 60 Hz in the NTSC standard: V rate)
Is stored in the storage section of the CCD (accumulation process). The electric charges accumulated in the accumulation unit are transferred to the horizontal transfer path at a second predetermined rate timing (for example, every 15.75 KHz: H rate) (transfer process). Further, the charge transferred to the horizontal transfer path is FDA (Floati) based on the horizontal transfer pulse.
The voltage is converted by an ng dufusion amp) and output to a subsequent circuit as an electric signal (voltage conversion process). On the other hand, the unnecessary charges after the voltage conversion are swept from the FDA unit to the power supply by the high voltage reset signal at the timing of the first predetermined rate (step 5). FIG. 4 shows that the CC
This is a drive circuit for driving the CCD in order to make D operable and to sweep out electric charges to the power supply.

In FIG. 4, a power supply voltage generated from a power supply 1 is applied to a DC-DC converter 2 and converted into a DC voltage of -10V. The -10V DC voltage is applied to the AC pulse generation circuit 3, and a pulse signal having a frequency of several hundred KHz and an amplitude of -10 to + 5V is generated based on the clock frequency of the system clock oscillator 5. This pulse signal is smoothed by the DC voltage generation circuit 4, level-shifted and boosted in this circuit, and
A DC output voltage of V is generated.

The output DC voltage of the DC-DC converter 2 is applied to a drive signal generation circuit 6 and is converted to a V rate, that is, 60 V, based on a DC voltage of -10 V and a power supply voltage of 5 V.
At a frequency of Hz, a drive signal having an amplitude of -10 to +5 V is generated. These + 20V DC voltage and drive signal are:
The charge of the CCD is transmitted to the CCD camera system 7 during the period of +35 V obtained as a result of the superimposition.

[0005]

In the conventional circuit shown in FIG.
Since the system clock is always supplied to the pulse signal generation circuit 3, harmonic noise caused by the rise or fall of the system clock is superimposed on the output DC voltage of the DC voltage generation circuit 4. The output pulse of the pulse signal generation circuit 3 is synchronized with the system clock, and since the system clock has a frequency of, for example, several hundred KHz, the harmonic noise has a vertical stripe pattern at a fixed position on the monitor. There has been a problem that image quality is reduced.

[0006]

According to the present invention, a driving circuit for driving a CCD based on a system clock stops driving of the CCD based on the system clock in synchronization with a blanking signal in a video signal. It is characterized by the following. In particular, the driving of the CCD is stopped during the non-blanking period.

A system oscillator for generating the system clock, a prohibition signal generation circuit for generating a prohibition signal in synchronization with a blanking signal of the video signal, and prohibition of application of the system clock in response to the prohibition signal And a prohibition circuit for performing the operation. Further, the prohibition signal is generated during a non-blanking period.

A stop signal generating circuit for generating a stop signal in synchronization with a blanking signal of the video signal, wherein a system oscillator is stopped according to the stop signal. Further, the stop circuit generates the stop signal during a non-blanking period.

According to the present invention, the supply of the system clock is stopped during the non-blanking period of the video signal, and the supply of the system clock is performed only during the blanking period. Therefore, since harmonic noise is generated only during the blanking period, the image quality of the CCD is not adversely affected.

[0010]

FIG. 1 is a diagram showing an embodiment of the present invention. Reference numeral 8 denotes a blanking signal for detecting a blanking signal from an NTSC standard video signal and generating a prohibition signal during a non-blanking period. The period detection circuit 9 is a switch for cutting off the supply of the system clock to the pulse signal generation circuit 3 in response to the prohibition signal. In FIG. 1,
The same circuits as those in FIG. 4 are denoted by the same reference numerals as those in FIG. 1, and description thereof will be omitted.

In FIG. 1, +5 V generated from power supply 1
Is converted by the DC-DC converter 2 into a DC voltage of -10V. The -10 V DC voltage is applied to the AC pulse generation circuit 3. Here, the system clock applied to the AC pulse generation circuit 3 is supplied or not supplied by opening and closing the switch 9. When the system clock is supplied, based on the frequency of the system clock,
The frequency is, for example, on the order of several hundred KHz, -10 to +5 V
A pulse signal a having the following amplitude is generated. This pulse signal a
Is smoothed by the DC voltage generation circuit 4 and further level-shifted to generate a DC output voltage b of 20V. When the system clock is not supplied, no pulse signal is generated from the pulse signal generation circuit 3, and a signal a having a constant level of 0 V is generated. In this case, the charge charged in the capacitor C in the DC voltage generation circuit 4 is discharged. However, since the capacitor C is set sufficiently large to smooth the pulse signal a to the DC level, the DC output voltage b Gradually decreases, and the DC voltage generation circuit 4 generates an output voltage of about 20V.

On the other hand, the output DC voltage of the DC-DC converter 2 is applied to a drive signal generating circuit 6, and based on the DC voltage of -10V and the power supply voltage of 5V, further generates a drive signal in accordance with the cycle of the V rate. Circuit 6 has a frequency of 60 Hz
Thus, a drive signal having an amplitude of -10 to +5 V is generated. Next, each signal change when the switch is opened and closed will be described.

The blanking period detecting circuit 8 detects the horizontal blanking period shown in FIG. 3 from the video signal and generates a prohibition signal c. The prohibition signal c becomes “H” level during the blanking period as shown in FIG. 3C, and becomes “L” during the non-blanking period. The prohibition signal c is applied to the switch 9, and the switch 9 opens and closes according to the level of the prohibition signal c. When the prohibition signal c is at the “H” level, the switch 9 is closed, and the system clock is applied to the pulse signal generation circuit 3. Therefore, as shown in period A of FIG. 3, a pulse signal a is generated, and by smoothing this,
Output DC voltage b. When the prohibition signal c is at the "L" level, the switch is opened and the supply of the system clock is cut off. As a result, a pulse is not generated as in the period B in FIG. Thus, the capacitor C of the DC voltage generation circuit 4 starts discharging. The DC voltage b during the period B in FIG. 3 gradually decreases as shown in FIG. 3B, but the discharge time constant of the capacitor C is sufficiently large, so that the DC voltage b during the period B in FIG.

In the period A shown in FIG.
Is supplied again, and the DC voltage b during the period A is obtained by smoothing the capacitor C in the discharged state as described above. Here, since the charging time constant of the capacitor C is set to be smaller than the discharging time constant, the capacitor C is immediately charged, and when the pulse signal a is applied to the DC voltage generating circuit 4, the DC voltage b in the period B immediately changes. To 20V. As described above, regardless of whether the switch 9 is opened or closed, the DC voltage b is always approximately +20 V, and the fluctuation range of the DC voltage b is small.

Therefore, even if the supply of the system clock is stopped during the non-blanking period, a voltage of +20 V can always be applied to the CCD camera system 7. Therefore, application of harmonic noise due to the system clock to the CCD camera system 7 is prevented. Even if a system clock is supplied during the blanking period and harmonic noise is applied to the CCD camera system 7, no specific noise appears on the screen because of the blanking period.

FIG. 2 is a diagram showing another embodiment.
The output c of the blanking period detection circuit 8 as shown in FIG. 3C is applied to the system clock oscillator 5 as a stop signal. The system clock oscillator 5 performs an oscillating operation when an “H” level stop signal c is applied to generate a system clock, and stops the oscillating operation when an “L” level stop signal c is applied. As a result, the pulse signal generating circuit 3 generates the pulse signal a during the blanking period, and generates a signal of a constant level instead of the pulse signal a during the non-blanking period. Therefore, the DC voltage generating circuit 4 generates a DC voltage b as shown in FIG. 3B which varies depending on the blanking period and the non-blanking period. Therefore, the circuit of FIG. 2 can also achieve the same effect as that of FIG.

Although the blanking period detecting circuit 8 detects the horizontal blanking period, the present invention is not limited to this, and the blanking period can be detected by detecting both the vertical blanking period and both the horizontal and vertical blanking periods. become.

[0018]

According to the present invention, the supply of the system clock is stopped or inhibited during the non-blanking period and the system clock is supplied during the blanking period, so that the harmonic noise is applied to the CCD during the non-blanking period. Not done. Further, even if harmonic noise due to the system clock occurs, the harmonic noise is merely superimposed on the video signal during a blanking period that does not appear as an image. Therefore, vertical stripe noise caused by the system clock is prevented from being generated on the screen.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a timing chart illustrating the operation of the present invention.

FIG. 4 is a block diagram showing a conventional example.

[Explanation of symbols]

 Reference Signs List 1 power supply 2 DC-DC converter 3 pulse signal generation circuit 4 DC voltage generation circuit 5 system clock oscillator 6 drive signal generation circuit 7 CCD camera system 8 blanking period detection circuit 9 switch

Claims (6)

[Claims] 1. A driving circuit for driving a CCD based on a system clock, wherein the driving circuit drives the CCD based on the system clock in synchronization with a blanking signal in a video signal.
A driving circuit for a CCD, wherein the driving of the CCD is stopped. 2. The CCD driving circuit according to claim 1, wherein driving of the CCD is stopped during a non-blanking period. 3. A system oscillator for generating the system clock, a prohibition signal generation circuit for generating a prohibition signal in synchronization with a blanking signal of the video signal, and prohibiting application of the system clock in response to the prohibition signal 2. The circuit according to claim 1, further comprising a prohibition circuit for performing the operation.
Drive circuit for CD. 4. The CCD driving circuit according to claim 3, wherein said inhibit signal is generated during a non-blanking period. 5. The system according to claim 1, further comprising: a stop signal generating circuit that generates a stop signal in synchronization with a blanking signal of the video signal, wherein a system oscillator is stopped in response to the stop signal. Driver circuit for CCD. 6. The CCD driving circuit according to claim 5, wherein said stop circuit generates said stop signal during a non-blanking period.