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JPH11121499A - Method and device for manufacture of semiconductor device - Google Patents

Method and device for manufacture of semiconductor device

Info

Publication number
JPH11121499A
JPH11121499A JP9278372A JP27837297A JPH11121499A JP H11121499 A JPH11121499 A JP H11121499A JP 9278372 A JP9278372 A JP 9278372A JP 27837297 A JP27837297 A JP 27837297A JP H11121499 A JPH11121499 A JP H11121499A
Authority
JP
Japan
Prior art keywords
semiconductor chip
lead frame
adhesive
semiconductor
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9278372A
Other languages
Japanese (ja)
Inventor
Keiichi Fujimoto
敬一 藤本
Tamotsu Shibata
保 柴田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP9278372A priority Critical patent/JPH11121499A/en
Publication of JPH11121499A publication Critical patent/JPH11121499A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7865—Means for transporting the components to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/787—Means for aligning
    • H01L2224/78743—Suction holding means
    • H01L2224/78744—Suction holding means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To manufacture a semiconductor device with high performance highly precisely by an efficient method. SOLUTION: A semiconductor chip 1 and a semiconductor chip holding part 2 in a lead frame are spaced at a fixed clearance apart. Then, the clearance is charged with adhesive 5. Then, the semiconductor chip 1 is fixed to a lead frame by curing the adhesive 5 simultaneously with wire bonding of the inner lead 6 and an electrode pad in the semiconductor chip 1.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、集積回路が表面に
形成された半導体チップを樹脂パッケージにする際の半
導体装置の製造方法および半導体装置の製造装置に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for manufacturing a semiconductor device when a semiconductor chip having an integrated circuit formed on a surface is formed into a resin package.

【０００２】[0002]

【従来の技術】近年、電子機器の小型、薄型、高性能化
の傾向は著しく、これに伴い電子部品の高機能化が急速
に進んでいる。特にメモリーをはじめとする半導体チッ
プの分野ではこの傾向が強く、より小型、薄型、低コス
ト、高信頼性で高密度実装に適したパッケージが求めら
れている。2. Description of the Related Art In recent years, there has been a remarkable tendency for electronic devices to be smaller, thinner, and higher in performance. This tendency is particularly strong in the field of semiconductor chips such as memories, and there is a demand for smaller, thinner, lower cost, highly reliable packages suitable for high-density mounting.

【０００３】プラスチックモールド型で小型化、薄型化
する例として、半導体チップとダミーのリード先端部と
の側面同士を接合用樹脂を介して接着したもの（特開平
３-２８９１６３号公報）等が提案されている。また、
半導体チップの側面と折り曲げ加工されたダミーのリー
ドとを樹脂等で接着した例も報告されている。それらの
パッケージの製造方法を、図８（ａ）〜（ｆ）に示す。[0003] As an example of miniaturization and thinning with a plastic mold type, a semiconductor chip and the side surface of a dummy lead tip bonded to each other via a bonding resin (Japanese Patent Application Laid-Open No. 3-289163) are proposed. Have been. Also,
There has also been reported an example in which a side surface of a semiconductor chip and a bent dummy lead are bonded with a resin or the like. 8 (a) to 8 (f) show a method of manufacturing these packages.

【０００４】まず図８（ａ）に示すように、半導体チッ
プ１０１とリードフレーム中の半導体チップ保持部１０
２とを固定ブロック１０３上で位置合わせを行う。次に
図８（ｂ）に示すように、半導体チップ１０１と半導体
チップ保持部１０２との間にディスペンサーノズル１０
４から接着剤１０５を塗布する。次に図８（ｃ）に示す
ように、そのままの状態で接着剤１０５を硬化し、半導
体チップ１０１を半導体チップ保持部１０２に固定す
る。次に図８（ｄ）に示すように、固定ブロック１０３
から半導体チップ１０１とリードフレームとを取り外
す。次に図８（ｅ）に示すように、インナーリード１０
６と半導体チップ１０１中の電極パッドとの間を金線１
０７でワイヤーボンディングを行う。最後に図８（ｆ）
に示すように、封止樹脂１０８で封止を行う。First, as shown in FIG. 8A, a semiconductor chip 101 and a semiconductor chip holding portion 10 in a lead frame are provided.
2 is aligned on the fixed block 103. Next, as shown in FIG. 8B, a dispenser nozzle 10 is provided between the semiconductor chip 101 and the semiconductor chip holding portion 102.
4 to apply the adhesive 105. Next, as shown in FIG. 8C, the adhesive 105 is cured as it is, and the semiconductor chip 101 is fixed to the semiconductor chip holding portion 102. Next, as shown in FIG.
The semiconductor chip 101 and the lead frame are removed from the above. Next, as shown in FIG.
6 and the electrode pad in the semiconductor chip 101
At 07, wire bonding is performed. Finally, FIG.
As shown in the figure, sealing is performed with a sealing resin 108.

【０００５】[0005]

【発明が解決しようとする課題】しかしながら上記従来
の製造方法では、接着剤の硬化時間は非常に長く、また
接着剤が硬化しないうちに半導体チップとリードフレー
ムとを固定ブロックから取り外すと、半導体チップがリ
ードフレームから脱落もしくは位置ズレが起こるため、
半導体チップとリードフレームとを接着固定させる工程
に要する時間が長く、単位時間当たりの加工量が少なく
なる。このため半導体チップを組み立て、封止を行うま
での製造効率が悪く、製造コストが非常に高くなる、と
いう課題があった。However, in the above-mentioned conventional manufacturing method, the curing time of the adhesive is very long, and if the semiconductor chip and the lead frame are detached from the fixing block before the adhesive is cured, the semiconductor chip is hardened. Is dropped or misaligned from the lead frame,
The time required for the step of bonding and fixing the semiconductor chip and the lead frame is long, and the processing amount per unit time is reduced. For this reason, there has been a problem that the manufacturing efficiency until assembling and sealing the semiconductor chip is poor, and the manufacturing cost is extremely high.

【０００６】本発明は上記従来の課題を解決するもので
あり、高い性能を有する半導体装置を高精度に効率のよ
い方法で製造することのできる半導体装置の製造方法お
よび半導体装置の製造装置を提供することを目的とす
る。SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and provides a semiconductor device manufacturing method and a semiconductor device manufacturing apparatus capable of manufacturing a high-performance semiconductor device with high accuracy and high efficiency. The purpose is to do.

【０００７】[0007]

【課題を解決するための手段】この目的を達成するため
に、本発明の半導体装置の製造方法は、半導体チップの
電極パッドと外部回路との電気的接続を行うための複数
のインナーリードとアウターリードと複数の半導体チッ
プ保持部とを備えたリードフレームの中央部に、半導体
チップ保持部と一定の間隙を設けて半導体チップを配置
する工程と、この間隙内に接着剤を充填する工程と、イ
ンナーリードと電極パッドとをワイヤーボンディングす
るのと同時に接着剤を硬化して半導体チップをリードフ
レームに固定する工程とを有するものであり、非常に長
い接着剤硬化時間を利用して、その間にワイヤーボンデ
ィングを行うため、工程削減とコストの低減が可能とな
るとともに搬送時の不良発生もなくすことができる。In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a plurality of inner leads and an outer lead for electrically connecting an electrode pad of a semiconductor chip to an external circuit. In the center of the lead frame including the leads and the plurality of semiconductor chip holders, a step of disposing a semiconductor chip with a certain gap with the semiconductor chip holder, and a step of filling the gap with an adhesive, Curing the adhesive and fixing the semiconductor chip to the lead frame at the same time as the wire bonding between the inner lead and the electrode pad. Since bonding is performed, it is possible to reduce the number of steps and the cost, and it is also possible to eliminate the occurrence of defects during transport.

【０００８】また、本発明の半導体装置の製造方法は、
熱硬化型の接着剤を熱により硬化するものであることが
好ましく、ワイヤーボンディングに必要な熱を接着剤硬
化にも利用することから、接着剤硬化のための特別な機
構を必要としなくなり、コスト低減が可能となる。Further, a method of manufacturing a semiconductor device according to the present invention
It is preferable that the thermosetting adhesive is cured by heat, and the heat required for wire bonding is also used for curing the adhesive, so that a special mechanism for curing the adhesive is not required and the cost is reduced. Reduction is possible.

【０００９】また、本発明の半導体装置の製造方法は、
半導体チップとリードフレームとを一時的に固定可能な
固定ブロックの温度が２００℃以上２４０℃以下であ
り、固定ブロック上で、インナーリードと電極パッドと
をワイヤーボンディングするのと同時に接着剤を硬化し
て半導体チップをリードフレームに固定する工程を有す
るものであることが好ましく、ワイヤー不着の不良を防
止するのが可能な上、接着剤中のボイド発生の不良を防
止することが可能となる。Further, a method for manufacturing a semiconductor device according to the present invention
The temperature of the fixed block that can temporarily fix the semiconductor chip and the lead frame is 200 ° C. or more and 240 ° C. or less, and at the same time as the inner lead and the electrode pad are wire-bonded on the fixed block, the adhesive is cured. It is preferable that the method has a step of fixing the semiconductor chip to the lead frame by using the above method, so that it is possible to prevent a defect of wire non-adhesion and to prevent a defect of void generation in the adhesive.

【００１０】また、本発明の半導体装置の製造方法は、
半導体チップの電極パッドと外部回路との電気的接続を
行うための複数のインナーリードとアウターリードと複
数の半導体チップ保持部とを備えたリードフレームと、
半導体チップとを、半導体チップと半導体チップ保持部
との間に一定の間隙を設けて配置する工程と、この間隙
内に接着剤を充填する工程と、リードフレームと半導体
チップとの位置関係が変化しない状態で搬送させながら
接着剤を硬化して半導体チップをリードフレームに固定
する工程とを有するものであり、半導体チップとリード
フレームとを固定する工程の単位時間当たりの加工量
が、非常に長い接着剤硬化時間に律速されなくなるた
め、単位時間当たりの加工量を増大することができる。Further, the method of manufacturing a semiconductor device according to the present invention comprises:
A lead frame including a plurality of inner leads, an outer lead, and a plurality of semiconductor chip holding portions for performing electrical connection between an electrode pad of the semiconductor chip and an external circuit,
The step of providing a fixed gap between the semiconductor chip and the semiconductor chip holding portion, the step of filling the gap with an adhesive, and the change in the positional relationship between the lead frame and the semiconductor chip. Fixing the semiconductor chip to the lead frame by curing the adhesive while being transported in a state where the semiconductor chip and the lead frame are not conveyed, and the processing amount per unit time of the step of fixing the semiconductor chip and the lead frame is extremely long. Since the rate is not determined by the adhesive curing time, the processing amount per unit time can be increased.

【００１１】また、本発明の半導体装置の製造方法は、
半導体チップの電極パッドと外部回路との電気的接続を
行うための複数のインナーリードとアウターリードと複
数の半導体チップ保持部とを備えた複数個のリードフレ
ームと、複数個の半導体チップとを、半導体チップと半
導体チップ保持部との間に一定の間隙を設けて配置する
工程と、すべての間隙内に接着剤を充填する工程と、す
べての接着剤を硬化してすべての半導体チップをすべて
のリードフレームに固定する工程とを有するものであ
り、複数対の半導体チップとリードフレームとの固定を
一回の半導体チップとリードフレームとの固定に要する
時間で行うことが可能となるため、半導体チップとリー
ドフレームとを固定する工程の単位時間当たりの加工量
を増大することができる。Further, a method of manufacturing a semiconductor device according to the present invention
A plurality of lead frames including a plurality of inner leads, outer leads, and a plurality of semiconductor chip holding portions for performing electrical connection between an electrode pad of the semiconductor chip and an external circuit, and a plurality of semiconductor chips, A step of providing a fixed gap between the semiconductor chip and the semiconductor chip holding section, a step of filling an adhesive in all the gaps, and a step of curing all the adhesives and fixing all the semiconductor chips to all the semiconductor chips. A step of fixing the semiconductor chip to the lead frame, and the fixing of the plurality of pairs of semiconductor chips and the lead frame can be performed in one time required for fixing the semiconductor chip and the lead frame. The amount of processing per unit time in the process of fixing the lead frame and the lead frame can be increased.

【００１２】また、本発明の半導体装置の製造装置は、
半導体チップとリードフレームとを一時的に固定可能な
固定ブロックを有し、半導体チップを固定ブロック上に
供給する機構と、リードフレームを固定ブロック上に搬
送する機構と、リードフレーム中の複数の半導体チップ
保持部と半導体チップとの間隙に接着剤を塗布する機構
と、リードフレーム中の複数のインナーリードと半導体
チップ中の電極パッドとをワイヤーボンディングする機
構と、接着剤を硬化する機構とを有するものであり、半
導体チップとリードフレームとを固定する工程およびワ
イヤーボンド工程を一台の装置で同時に行うことが可能
となるため、工程削減とコストの低減とが可能となると
ともに搬送時の不良発生もなくすことができる。Further, the semiconductor device manufacturing apparatus of the present invention comprises:
A fixing block for temporarily fixing the semiconductor chip and the lead frame, a mechanism for supplying the semiconductor chip onto the fixed block, a mechanism for transporting the lead frame onto the fixed block, and a plurality of semiconductors in the lead frame It has a mechanism for applying an adhesive to the gap between the chip holding portion and the semiconductor chip, a mechanism for wire bonding the plurality of inner leads in the lead frame to the electrode pads in the semiconductor chip, and a mechanism for curing the adhesive. The process of fixing the semiconductor chip and the lead frame and the wire bonding process can be performed simultaneously with one device, so that it is possible to reduce the number of processes and costs, and to generate defects during transportation. Can be lost.

【００１３】また、本発明の半導体装置の製造装置は、
半導体チップとリードフレームとを一時的に固定可能な
固定ブロックを複数個有し、すべての固定ブロックが環
状につながっており、１つの固定ブロック上に半導体チ
ップを供給する機構と、この固定ブロックと半導体チッ
プとの上にリードフレームを搬送する機構と、リードフ
レーム中の複数の半導体チップ保持部と半導体チップと
の間隙に接着剤を塗布する機構と、環状につながった固
定ブロックが周回する機構と、接着剤を硬化する機構と
を有するものであり、半導体チップとリードフレームと
を固定する工程の単位時間当たりの加工量が、非常に長
い接着剤硬化時間に律速されなくなるため、単位時間当
たりの加工量を増大することができる。Further, the apparatus for manufacturing a semiconductor device according to the present invention comprises:
A plurality of fixed blocks capable of temporarily fixing the semiconductor chip and the lead frame, all of the fixed blocks are connected in a ring shape, and a mechanism for supplying the semiconductor chip onto one fixed block; A mechanism for transporting the lead frame onto the semiconductor chip, a mechanism for applying an adhesive to a gap between the plurality of semiconductor chip holding portions in the lead frame and the semiconductor chip, and a mechanism for rotating a fixed block connected in an annular shape; , A mechanism for curing the adhesive, the processing amount per unit time of the step of fixing the semiconductor chip and the lead frame is not limited by a very long adhesive curing time, so the per unit time The amount of processing can be increased.

【００１４】また、本発明の半導体装置の製造装置は、
複数個の半導体チップと複数個のリードフレームとを一
時的に固定可能な固定ブロックを有し、複数個の半導体
チップをウエハから固定ブロック上に供給する機構と、
複数個のリードフレームを固定ブロックと半導体チップ
との上に搬送する機構と、複数個のリードフレーム中の
すべての半導体チップ保持部と複数個の半導体チップと
の間隙に接着剤を塗布する機構と、接着剤を硬化する機
構とを有するものであり、複数対の半導体チップとリー
ドフレームとの固定を一回の半導体チップとリードフレ
ームとの固定に要する時間で行うことが可能となるた
め、半導体チップとリードフレームとを固定する工程の
単位時間当たりの加工量を増大することができる。Further, the semiconductor device manufacturing apparatus of the present invention
A fixed block capable of temporarily fixing a plurality of semiconductor chips and a plurality of lead frames, a mechanism for supplying the plurality of semiconductor chips from the wafer to the fixed block,
A mechanism for transporting a plurality of lead frames onto the fixed block and the semiconductor chip, a mechanism for applying an adhesive to a gap between all the semiconductor chip holding portions in the plurality of lead frames and the plurality of semiconductor chips, and And a mechanism for curing the adhesive, so that a plurality of pairs of semiconductor chips and a lead frame can be fixed in a time required for fixing the semiconductor chip and the lead frame once. The processing amount per unit time of the step of fixing the chip and the lead frame can be increased.

【００１５】[0015]

【発明の実施の形態】以下、本発明の実施の形態につい
て、図面を参照しながら説明する。Embodiments of the present invention will be described below with reference to the drawings.

【００１６】図１（ａ）〜（ｅ）に、本発明の第１の実
施の形態における半導体装置の製造方法の工程断面図を
示す。FIGS. 1A to 1E are sectional views showing the steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

【００１７】まず図１（ａ）に示すように、半導体チッ
プ１とリードフレーム中の半導体チップ保持部２とを固
定ブロック３上で位置合わせを行う。次に図１（ｂ）に
示すように、半導体チップ１と半導体チップ保持部２と
の間にディスペンサーノズル４から熱硬化型の接着剤５
を塗布する。次に図１（ｃ）に示すように、インナーリ
ード６と半導体チップ１中の電極パッドとの間をキャピ
ラリー７を用いて金線８でワイヤーボンディングするの
と同時に、接着剤５を硬化し、半導体チップ１を半導体
チップ保持部２に固定する。次に図１（ｄ）に示すよう
に、固定ブロック３から半導体チップ１とリードフレー
ムを取り外す。最後に図１（ｅ）に示すように、封止樹
脂９で封止を行う。First, as shown in FIG. 1A, the semiconductor chip 1 and the semiconductor chip holder 2 in the lead frame are aligned on the fixed block 3. Next, as shown in FIG. 1B, a thermosetting adhesive 5 is provided between the semiconductor chip 1 and the semiconductor chip holder 2 through a dispenser nozzle 4.
Is applied. Next, as shown in FIG. 1C, wire bonding between the inner lead 6 and the electrode pad in the semiconductor chip 1 is performed by using the capillary 7 with the gold wire 8, and at the same time, the adhesive 5 is cured. The semiconductor chip 1 is fixed to the semiconductor chip holding unit 2. Next, as shown in FIG. 1D, the semiconductor chip 1 and the lead frame are removed from the fixed block 3. Finally, sealing is performed with a sealing resin 9 as shown in FIG.

【００１８】本実施の形態では、固定ブロック３を２２
０℃の温度に加熱し、ワイヤーボンディングを行い、ま
た接着剤５を固定ブロック３から伝わる熱で硬化させ
る。このことにより、金線８がインナーリード６および
半導体チップ１中の電極パッドに正常にボンディングさ
れる。その上、接着剤５の硬化後に接着剤５中にボイド
が発生せず、半導体チップ１と半導体チップ保持部２と
の接着力を十分確保できるとともに樹脂封止後の半導体
装置の耐湿信頼性は良好である。In the present embodiment, the fixed block 3 is
It is heated to a temperature of 0 ° C. to perform wire bonding, and the adhesive 5 is cured by heat transmitted from the fixing block 3. Thus, the gold wire 8 is normally bonded to the inner lead 6 and the electrode pad in the semiconductor chip 1. In addition, voids are not generated in the adhesive 5 after the adhesive 5 is cured, and the adhesive strength between the semiconductor chip 1 and the semiconductor chip holding portion 2 can be sufficiently ensured, and the moisture resistance reliability of the semiconductor device after resin sealing is improved. Good.

【００１９】また、半導体チップ１とリードフレームと
を接着固定するのに要する時間は、まず半導体チップ１
とリードフレームとの搬送、位置合わせが０．５秒、接
着剤５の塗布が１．０秒、接着剤５の硬化が７．０秒で
あり、ワイヤーボンディングに要する時間は６．５秒で
ある。このことから、接続されていない半導体チップ１
とリードフレームとを物理的、電気的に接続するのに、
従来のように半導体チップ１を接着固定した後ワイヤー
ボンディングを行うと、１５秒の時間を要していたが、
本実施の形態では８．５秒の時間で可能となる。The time required for bonding and fixing the semiconductor chip 1 and the lead frame is as follows.
The time required for the transfer and alignment of the lead frame with the lead frame is 0.5 seconds, the application of the adhesive 5 is 1.0 second, the curing of the adhesive 5 is 7.0 seconds, and the time required for wire bonding is 6.5 seconds. is there. For this reason, the unconnected semiconductor chip 1
To physically and electrically connect
When wire bonding is performed after the semiconductor chip 1 is bonded and fixed as in the related art, it takes 15 seconds.
In the present embodiment, it is possible in 8.5 seconds.

【００２０】ここで、固定ブロック３の温度を２００℃
より低くすると金線８がインナーリード６もしくは半導
体チップ１中の電極パッドへ正常にボンディングされな
いという不良が発生する。また、固定ブロック３の温度
を２４０℃より高くすると接着剤５の硬化後に接着剤５
中にボイドが発生する。以上より、固定ブロック３の温
度は２００℃以上２４０℃以下にする必要がある。Here, the temperature of the fixed block 3 is set to 200 ° C.
If it is lower, a defect that the gold wire 8 is not properly bonded to the inner lead 6 or the electrode pad in the semiconductor chip 1 occurs. When the temperature of the fixing block 3 is higher than 240 ° C., the adhesive 5 is hardened after the adhesive 5 is cured.
Voids occur inside. As described above, the temperature of the fixed block 3 needs to be 200 ° C. or higher and 240 ° C. or lower.

【００２１】なお今回、固定ブロック３からの熱により
接着剤５を硬化させ、半導体チップ１とリードフレーム
中の半導体チップ保持部２とを固定させたが、他の方法
により接着剤５を硬化させてもよい。In this case, the adhesive 5 is cured by the heat from the fixing block 3 to fix the semiconductor chip 1 and the semiconductor chip holding portion 2 in the lead frame, but the adhesive 5 is cured by another method. You may.

【００２２】次に、図２に本発明の第２の実施の形態に
おける半導体装置の製造装置の要部斜視図を示す。FIG. 2 is a perspective view showing a main part of a semiconductor device manufacturing apparatus according to a second embodiment of the present invention.

【００２３】この半導体装置の製造装置は、半導体チッ
プ１１をチップコレット１２により固定ブロック１３と
同一面上の仮テーブル１４上へ運び、チップ突き棒１５
により固定ブロック１３上へ供給する機構と、リードフ
レーム１６をフレーム搬送レール１７により固定ブロッ
ク１３上へ搬送し、半導体チップ１１と位置合わせする
機構と、固定ブロック１３上に位置合わせされた半導体
チップ１１とリードフレーム１６の間隙の複数部分に接
着剤をディスペンサーノズル１８により塗布する機構
と、塗布された接着剤を硬化させる機構と、半導体チッ
プ１１の電極パッドとリードフレーム１６中のインナー
リードとの金線１９接続をキャピラリー２０により行う
機構と、半導体チップ１１と物理的、電気的接続された
リードフレーム１６をフレーム搬送レール１７により搬
送する機構とを備えている。In this semiconductor device manufacturing apparatus, the semiconductor chip 11 is carried by the chip collet 12 onto the temporary table 14 on the same plane as the fixed block 13 and
, A mechanism for transporting the lead frame 16 onto the fixed block 13 by the frame transport rail 17 and aligning the semiconductor chip 11 with the semiconductor chip 11, A mechanism for applying an adhesive to a plurality of portions of the gap between the lead frame 16 and the dispenser nozzle 18, a mechanism for curing the applied adhesive, and a method for bonding the electrode pads of the semiconductor chip 11 to the inner leads in the lead frame 16. A mechanism for connecting the wire 19 by the capillary 20 and a mechanism for transporting the lead frame 16 physically and electrically connected to the semiconductor chip 11 by the frame transport rail 17 are provided.

【００２４】以上の機構を備えている製造装置を用いる
ことにより、本発明の第１の実施の形態の半導体装置の
製造方法を実現することが可能となり、非常に長い接着
剤硬化時間を利用してその間にワイヤーボンディングを
行うため、工程削減とコストの低減が可能となるととも
に搬送時の不良発生もなくすことができる。By using the manufacturing apparatus having the above mechanism, the method of manufacturing a semiconductor device according to the first embodiment of the present invention can be realized, and a very long adhesive curing time can be used. In addition, since wire bonding is performed during this time, it is possible to reduce the number of steps and cost, and it is also possible to prevent the occurrence of defects during transportation.

【００２５】次に図３（ａ）〜（ｆ）に、本発明の第３
の実施の形態における半導体装置の製造方法の工程断面
図を示す。Next, FIGS. 3A to 3F show a third embodiment of the present invention.
FIG. 7 is a process cross-sectional view of the method for manufacturing the semiconductor device in the embodiment.

【００２６】まず図３（ａ）に示すように、半導体チッ
プ２１とリードフレーム２２とが固定ブロック２３
（１）上で固定されている。次に図３（ｂ）に示すよう
に、半導体チップ２１とリードフレーム２２との位置関
係が変わらないように固定ブロック２３（１）を搬送
し、半導体チップ２１とリードフレーム２２との間にデ
ィスペンサーノズル２４から熱硬化型の接着剤２５を塗
布する。次に図３（ｃ）に示すように、半導体チップ２
１とリードフレーム２２との位置関係が変わらないよう
に固定ブロック２３（１）を搬送し、この間に接着剤２
５を熱により硬化し半導体チップ２１とリードフレーム
２２とを固定させる。これと同時に固定ブロック２３
（２）上の半導体チップ２１とリードフレーム２２との
間にディスペンサーノズル２４から熱硬化型の接着剤２
５を塗布する。次に図３（ｄ）に示すように、固定ブロ
ック２３（１）を搬送し、固定ブロック２３（１）から
半導体チップ２１とリードフレーム２２とを取り外す。
固定ブロック２３（１）上で行った工程を順次固定ブロ
ック２３（２）、ブロック２３（３）、ブロック２３
（４）、・・・で行う。次に図３（ｅ）に示すように、
金線２６でワイヤーボンドを行う。最後に図３（ｆ）に
示すように、封止樹脂２７で封止を行う。First, as shown in FIG. 3A, a semiconductor chip 21 and a lead frame 22 are fixed to a fixed block 23.
(1) It is fixed above. Next, as shown in FIG. 3B, the fixed block 23 (1) is transported so that the positional relationship between the semiconductor chip 21 and the lead frame 22 does not change, and a dispenser is provided between the semiconductor chip 21 and the lead frame 22. A thermosetting adhesive 25 is applied from a nozzle 24. Next, as shown in FIG.
The fixing block 23 (1) is transported so that the positional relationship between the lead frame 1 and the lead frame 22 does not change.
5 is cured by heat to fix the semiconductor chip 21 and the lead frame 22 together. At the same time, the fixed block 23
(2) A thermosetting adhesive 2 is provided between the upper semiconductor chip 21 and the lead frame 22 through the dispenser nozzle 24.
5 is applied. Next, as shown in FIG. 3D, the fixed block 23 (1) is transported, and the semiconductor chip 21 and the lead frame 22 are removed from the fixed block 23 (1).
The steps performed on the fixed block 23 (1) are sequentially performed on the fixed block 23 (2), the block 23 (3), and the block 23.
(4),... Next, as shown in FIG.
Wire bonding is performed with the gold wire 26. Finally, as shown in FIG. 3F, sealing is performed with a sealing resin 27.

【００２７】ここで、半導体チップ２１とリードフレー
ム２２とを接着固定するのに要する時間は、まず半導体
チップ２１とリードフレーム２２との搬送、位置合わせ
が０．５秒、接着剤２５の塗布が１．０秒、接着剤２５
の硬化が７．０秒である。このことから、半導体チップ
２１とリードフレーム２２とを固定する工程の単位時間
当たりの加工量は、従来のように同一の場所で半導体チ
ップ２１とリードフレーム２２の位置合わせ、接着剤２
５の塗布、硬化を行うと、４２０個／時間となるのに対
し、本実施の形態では２４００個／時間となった。The time required for bonding and fixing the semiconductor chip 21 and the lead frame 22 is as follows. First, the transfer and alignment of the semiconductor chip 21 and the lead frame 22 are performed for 0.5 seconds, and the application of the adhesive 25 is performed. 1.0 second, adhesive 25
Is 7.0 seconds. From this, the processing amount per unit time of the step of fixing the semiconductor chip 21 and the lead frame 22 is the same as that of the related art, in which the position of the semiconductor chip 21 and the lead frame 22 is aligned and the adhesive 2
When the coating and curing of No. 5 were performed, the number was 420 pieces / hour, whereas in the present embodiment, it was 2400 pieces / hour.

【００２８】次に、図４に本発明の第４の実施の形態に
おける半導体装置の製造装置の要部側面透視図を示す。FIG. 4 is a side perspective view of a main part of a semiconductor device manufacturing apparatus according to a fourth embodiment of the present invention.

【００２９】この半導体装置の製造装置は、複数の固定
ブロック３１が環状につながっておりこれらが駆動部３
２の回転により周回する機構と、半導体チップ３３をチ
ップコレット３４により固定ブロック３１の一つの上へ
供給する機構と、リードフレーム３５をフレームローダ
ー３６により固定ブロック３１上に搬送し、半導体チッ
プ３３と位置合わせする機構と、真空ライン４９により
固定ブロック３１上の半導体チップ３３およびリードフ
レーム３５を固定ブロック３１に真空吸引固定する機構
と、固定ブロック３１上に位置合わせされた半導体チッ
プ３３とリードフレーム３５の間隙の複数部分に接着剤
３７をディスペンサーノズル３８により塗布する機構
と、ヒーターブロック３９から固定ブロック３１を通じ
て伝わる熱により塗布された接着剤３７を硬化させる機
構と、半導体チップ３３と固定されたリードフレーム３
５をフレーム搬送レール４０により搬送する機構とを備
えている。In this apparatus for manufacturing a semiconductor device, a plurality of fixed blocks 31 are connected in a ring shape and these
2, a mechanism for feeding the semiconductor chip 33 onto one of the fixed blocks 31 by the chip collet 34, and a mechanism for transporting the lead frame 35 onto the fixed block 31 by the frame loader 36. A mechanism for positioning, a mechanism for vacuum-suction-fixing the semiconductor chip 33 and the lead frame 35 on the fixed block 31 to the fixed block 31 by the vacuum line 49, and a mechanism for positioning the semiconductor chip 33 and the lead frame 35 on the fixed block 31. A mechanism for applying the adhesive 37 to a plurality of portions of the gap by the dispenser nozzle 38, a mechanism for curing the applied adhesive 37 by heat transmitted from the heater block 39 through the fixing block 31, and a lead fixed to the semiconductor chip 33. Frame 3
5 is transported by the frame transport rail 40.

【００３０】以上の機構を備えている製造装置を用いる
ことにより、本発明の第３の実施の形態の半導体装置の
製造方法を実現することが可能となり、半導体チップ３
３とリードフレーム３５とを固定する工程の単位時間当
たりの加工量が、非常に長い接着剤３７の硬化時間に律
速されなくなるため、単位時間当たりの加工量を増大す
ることができる。By using the manufacturing apparatus having the above mechanism, the method of manufacturing a semiconductor device according to the third embodiment of the present invention can be realized.
Since the processing amount per unit time in the process of fixing the lead 3 and the lead frame 35 is not limited by the extremely long curing time of the adhesive 37, the processing amount per unit time can be increased.

【００３１】次に、図５（ａ）〜（ｆ）に本発明の第５
の実施の形態における半導体装置の製造方法の工程断面
図を示す。Next, FIGS. 5A to 5F show a fifth embodiment of the present invention.
FIG. 7 is a process cross-sectional view of the method for manufacturing the semiconductor device in the embodiment.

【００３２】まず図５（ａ）に示すように、３個の半導
体チップ４１と３個のリードフレーム中の半導体チップ
保持部４２とを固定ブロック４３上で位置合わせを行
う。次に図５（ｂ）に示すように、３個の半導体チップ
４１と３個のリードフレーム中の半導体チップ保持部４
２との間にディスペンサーノズル４４から接着剤４５を
塗布する。次に図５（ｃ）に示すように、そのままの状
態で接着剤４５を硬化し、半導体チップ４１を半導体チ
ップ保持部４２に固定する。次に図５（ｄ）に示すよう
に、固定ブロック４３から半導体チップ４１とリードフ
レームを取り外す。次に図５（ｅ）に示すように、イン
ナーリード４６と半導体チップ４１中の電極パッドとの
間を金線４７でワイヤーボンディングを行う。最後に図
５（ｆ）に示すように、封止樹脂４８で封止を行う。First, as shown in FIG. 5A, the three semiconductor chips 41 and the semiconductor chip holders 42 in the three lead frames are aligned on the fixed block 43. Next, as shown in FIG. 5B, three semiconductor chips 41 and three semiconductor chip holders 4 in the lead frame are provided.
The adhesive 45 is applied from the dispenser nozzle 44 to the gap 2. Next, as shown in FIG. 5C, the adhesive 45 is cured as it is, and the semiconductor chip 41 is fixed to the semiconductor chip holding portion 42. Next, as shown in FIG. 5D, the semiconductor chip 41 and the lead frame are removed from the fixed block 43. Next, as shown in FIG. 5E, wire bonding is performed between the inner lead 46 and the electrode pad in the semiconductor chip 41 with a gold wire 47. Finally, as shown in FIG. 5F, sealing is performed with a sealing resin.

【００３３】ここで、半導体チップ４１とリードフレー
ムを接着固定するのに要する時間は、まず半導体チップ
４１とリードフレームの搬送、位置合わせが０．５秒、
接着剤４５の塗布が１．０秒、硬化が７．０秒である。
このことから、半導体チップ４１とリードフレームとを
固定する工程の単位時間当たりの加工量は、従来のよう
に半導体チップ４１とリードフレームを１対ずつ固定を
行うと、４２０個／時間となるのに対し、本実施の形態
では１１００個／時間となった。Here, the time required for bonding and fixing the semiconductor chip 41 and the lead frame is as follows.
The application time of the adhesive 45 is 1.0 second, and the curing time is 7.0 seconds.
From this, the processing amount per unit time of the step of fixing the semiconductor chip 41 and the lead frame is 420 pieces / hour when the pair of the semiconductor chip 41 and the lead frame are fixed as in the related art. On the other hand, in the present embodiment, it was 1100 pieces / hour.

【００３４】なお本実施の形態では、３対の半導体チッ
プ４１とリードフレームの固定を一度に行ったが、可能
な限り多数対の半導体チップ４１とリードフレームの固
定を一度に行った方が本発明の効果が大きくなる。In this embodiment, the three pairs of semiconductor chips 41 and the lead frame are fixed at one time. However, it is better to fix as many pairs of semiconductor chips 41 and the lead frame as possible at once. The effect of the invention is increased.

【００３５】次に、図６に本発明の第６の実施の形態に
おける半導体装置の製造装置の要部斜視図を示す。FIG. 6 is a perspective view of a main part of a semiconductor device manufacturing apparatus according to a sixth embodiment of the present invention.

【００３６】この半導体装置の製造装置は、複数の半導
体チップ５１をチップコレット５２により固定ブロック
５３上に供給する機構と、複数のリードフレーム５４を
フレーム搬送レール５５により固定ブロック５３上に搬
送し、半導体チップ５１と位置合わせする機構と、固定
ブロック５３上に位置合わせされた複数の半導体チップ
５１と複数のリードフレーム５４の間隙の複数部分に接
着剤をディスペンサーノズル５６により塗布する機構
と、塗布された接着剤を熱により硬化させる機構と、半
導体チップ５１と固定されたリードフレーム５４をフレ
ーム搬送レール５５により搬送する機構とを備えてい
る。This apparatus for manufacturing a semiconductor device includes a mechanism for supplying a plurality of semiconductor chips 51 onto a fixed block 53 by a chip collet 52, and a method for transporting a plurality of lead frames 54 onto the fixed block 53 by a frame transport rail 55. A mechanism for aligning the semiconductor chip 51 with the semiconductor chip 51, a mechanism for applying an adhesive by a dispenser nozzle 56 to a plurality of portions of a gap between the plurality of semiconductor chips 51 and the plurality of lead frames 54 aligned on the fixed block 53, and A mechanism for curing the adhesive by heat and a mechanism for transporting the lead frame 54 fixed to the semiconductor chip 51 by the frame transport rail 55 are provided.

【００３７】また、図７のように接着剤塗布機構部と、
半導体チップ５１供給部とが離れており、固定ブロック
５３が両部の間を移動できる機構を備えていてもよい。Also, as shown in FIG.
The supply unit of the semiconductor chip 51 may be separated, and a mechanism may be provided in which the fixed block 53 can move between the two units.

【００３８】以上の機構を備えている製造装置を用いる
ことにより、本発明の第５の実施の形態の半導体装置の
製造方法を実現することが可能となり、複数対の半導体
チップ５１とリードフレーム５４との固定を一回の半導
体チップ５１とリードフレーム５４の固定に要する時間
で行うことが可能となるため、単位時間当たりの加工量
を増強することができる。By using the manufacturing apparatus having the above-described mechanism, the method of manufacturing a semiconductor device according to the fifth embodiment of the present invention can be realized, and a plurality of pairs of semiconductor chips 51 and lead frames 54 are provided. Can be fixed in the time required for fixing the semiconductor chip 51 and the lead frame 54 one time, so that the processing amount per unit time can be enhanced.

【００３９】[0039]

【発明の効果】以上のように、本発明によれば、インナ
ーリードと電極パッドとをワイヤーボンディングするの
と同時に半導体チップをリードフレームに固定する工
程、もしくは半導体チップとリードフレームとを搬送し
ながら固定する工程、もしくは複数の半導体チップと複
数のリードフレームとを一度に固定する工程を有するこ
とにより、製造工程の短縮、製造時間の短縮が可能とな
る上に、高い性能を有する半導体装置を高精度に製造す
ることが可能となる。As described above, according to the present invention, the step of fixing the semiconductor chip to the lead frame at the same time as the wire bonding of the inner lead and the electrode pad, or while transporting the semiconductor chip and the lead frame. By having a fixing step or a step of fixing a plurality of semiconductor chips and a plurality of lead frames at once, it is possible to shorten a manufacturing process and a manufacturing time, and to improve a semiconductor device having high performance. It is possible to manufacture with high accuracy.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施の形態における半導体装置
の製造方法を示す工程断面図FIG. 1 is a process sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

【図２】本発明の第２の実施の形態における半導体装置
の製造装置を示す要部斜視図FIG. 2 is a perspective view of a main part showing an apparatus for manufacturing a semiconductor device according to a second embodiment of the present invention;

【図３】本発明の第３の実施の形態における半導体装置
の製造方法を示す工程断面図FIG. 3 is a process sectional view illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

【図４】本発明の第４の実施の形態における半導体装置
の製造装置を示す要部側面透視図FIG. 4 is an essential part side perspective view showing a semiconductor device manufacturing apparatus according to a fourth embodiment of the present invention;

【図５】本発明の第５の実施の形態における半導体装置
の製造方法を示す工程断面図FIG. 5 is a process sectional view illustrating a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

【図６】本発明の第６の実施の形態における半導体装置
の製造装置を示す要部斜視図FIG. 6 is an essential part perspective view showing a semiconductor device manufacturing apparatus according to a sixth embodiment of the present invention;

【図７】本発明の第７の実施の形態における半導体装置
の製造装置を示す要部斜視図FIG. 7 is an essential part perspective view showing a semiconductor device manufacturing apparatus according to a seventh embodiment of the present invention;

【図８】従来の半導体装置の製造方法を示す工程断面図FIG. 8 is a process sectional view showing a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

１、１１、２１、３３、４１、５１ 半導体チップ ２、４２ 半導体チップ保持部 ３、１３、２３、３１、４３、５３ 固定ブロック ４、１８、２４、３８、４４、５６ ディスペンサーノ
ズル ５、２５、３７、４５ 接着剤 ６、４６ インナーリード ７、２０ キャピラリー ８、１９、２６、４７ 金線 ９、２７、４８ 封止樹脂 １２、３４、５２ チップコレット １４ 仮テーブル １５ チップ突き棒 １６、２２、３５、５４ リードフレーム １７、４０、５５ フレーム搬送レール ３２ 駆動部 ３６ フレームローダー ３９ ヒーターブロック ４９ 真空ライン1, 11, 21, 33, 41, 51 Semiconductor chip 2, 42 Semiconductor chip holder 3, 13, 23, 31, 43, 53 Fixed block 4, 18, 24, 38, 44, 56 Dispenser nozzle 5, 25, 37, 45 Adhesive 6, 46 Inner lead 7, 20 Capillary 8, 19, 26, 47 Gold wire 9, 27, 48 Sealing resin 12, 34, 52 Chip collet 14 Temporary table 15 Chip piercing rod 16, 22, 35 , 54 Lead frame 17, 40, 55 Frame transport rail 32 Drive unit 36 Frame loader 39 Heater block 49 Vacuum line

Claims (8)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップの電極パッドと外部回路と
の電気的接続を行うための複数のインナーリードとアウ
ターリードと複数の半導体チップ保持部とを備えたリー
ドフレームの中央部に、前記半導体チップ保持部と一定
の間隙を設けて半導体チップを配置する工程と、前記間
隙内に接着剤を充填する工程と、前記インナーリードと
電極パッドとをワイヤーボンディングするのと同時に前
記接着剤を硬化して前記半導体チップを前記リードフレ
ームに固定する工程とを有する半導体装置の製造方法。The semiconductor chip is provided at a central portion of a lead frame including a plurality of inner leads, an outer lead, and a plurality of semiconductor chip holders for electrically connecting an electrode pad of the semiconductor chip to an external circuit. A step of disposing a semiconductor chip by providing a predetermined gap with the holding portion, a step of filling the gap with an adhesive, and simultaneously curing the adhesive by wire bonding the inner lead and the electrode pad. Fixing the semiconductor chip to the lead frame. 【請求項２】 前記接着剤が熱硬化型であり、前記接着
剤を熱により硬化して前記半導体チップを前記リードフ
レームに固定する工程を有する請求項１に記載の半導体
装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the adhesive is a thermosetting type, and the method further comprises a step of curing the adhesive by heat to fix the semiconductor chip to the lead frame. 【請求項３】 前記半導体チップと前記リードフレーム
とを一時的に固定可能な固定ブロックの温度が２００℃
以上２４０℃以下であり、前記固定ブロック上で、前記
インナーリードと前記電極パッドとをワイヤーボンディ
ングするのと同時に前記接着剤を硬化して前記半導体チ
ップを前記リードフレームに固定する工程を有する請求
項２に記載の半導体装置の製造方法。3. The temperature of a fixed block capable of temporarily fixing the semiconductor chip and the lead frame is 200 ° C.
240 ° C. or less, and a step of wire-bonding the inner leads and the electrode pads on the fixing block and simultaneously curing the adhesive to fix the semiconductor chip to the lead frame. 3. The method for manufacturing a semiconductor device according to item 2. 【請求項４】 半導体チップの電極パッドと外部回路と
の電気的接続を行うための複数のインナーリードとアウ
ターリードと複数の半導体チップ保持部とを備えたリー
ドフレームと、半導体チップとを、前記半導体チップと
前記半導体チップ保持部との間に一定の間隙を設けて配
置する工程と、前記間隙内に接着剤を充填する工程と、
前記リードフレームと前記半導体チップとの位置関係が
変化しない状態で搬送させながら前記接着剤を硬化して
前記半導体チップを前記リードフレームに固定する工程
とを有する半導体装置の製造方法。4. A lead frame including a plurality of inner leads, an outer lead, and a plurality of semiconductor chip holders for electrically connecting an electrode pad of the semiconductor chip to an external circuit, and the semiconductor chip, A step of providing a fixed gap between the semiconductor chip and the semiconductor chip holding portion, and a step of filling the gap with an adhesive;
Curing the adhesive while transporting the lead frame and the semiconductor chip in a state where the positional relationship does not change, and fixing the semiconductor chip to the lead frame. 【請求項５】 半導体チップの電極パッドと外部回路と
の電気的接続を行うための複数のインナーリードとアウ
ターリードと複数の半導体チップ保持部とを備えた複数
個のリードフレームと、複数個の半導体チップとを、前
記半導体チップと前記半導体チップ保持部との間に一定
の間隙を設けて配置する工程と、すべての前記間隙内に
接着剤を充填する工程と、すべての前記接着剤を硬化し
てすべての前記半導体チップをすべての前記リードフレ
ームに固定する工程とを有する半導体装置の製造方法。5. A plurality of lead frames each including a plurality of inner leads and an outer lead for electrically connecting an electrode pad of a semiconductor chip to an external circuit, and a plurality of semiconductor chip holders. A step of disposing a semiconductor chip with a constant gap between the semiconductor chip and the semiconductor chip holding portion, a step of filling all the gaps with an adhesive, and curing all the adhesives Fixing all the semiconductor chips to all the lead frames. 【請求項６】 半導体チップとリードフレームとを一時
的に固定可能な固定ブロックを有し、半導体チップを前
記固定ブロック上へ供給する機構と、リードフレームを
前記固定ブロック上へ搬送する機構と、前記リードフレ
ーム中の複数の半導体チップ保持部と前記半導体チップ
との間隙に接着剤を塗布する機構と、前記リードフレー
ム中の複数のインナーリードと前記半導体チップ中の電
極パッドとをワイヤーボンディングする機構と、前記接
着剤を硬化する機構とを有する半導体装置の製造装置。6. A mechanism having a fixed block capable of temporarily fixing a semiconductor chip and a lead frame, for supplying a semiconductor chip onto the fixed block, a mechanism for transporting the lead frame onto the fixed block, A mechanism for applying an adhesive to a gap between the plurality of semiconductor chip holding portions in the lead frame and the semiconductor chip, and a mechanism for wire bonding between the plurality of inner leads in the lead frame and the electrode pads in the semiconductor chip And a mechanism for manufacturing the semiconductor device having a mechanism for curing the adhesive. 【請求項７】 半導体チップとリードフレームとを一時
的に固定可能な固定ブロックを複数個有し、すべての前
記固定ブロックが環状につながっており、１つの前記固
定ブロック上に半導体チップを供給する機構と、前記固
定ブロックと前記半導体チップとの上にリードフレーム
を搬送する機構と、前記リードフレーム中の複数の半導
体チップ保持部と前記半導体チップとの間隙に接着剤を
塗布する機構と、環状につながった前記固定ブロックが
周回する機構と、前記接着剤を硬化する機構とを有する
半導体装置の製造装置。7. A plurality of fixed blocks capable of temporarily fixing a semiconductor chip and a lead frame, all the fixed blocks are connected in a ring shape, and the semiconductor chip is supplied onto one fixed block. A mechanism for transporting a lead frame over the fixed block and the semiconductor chip, a mechanism for applying an adhesive to a gap between the plurality of semiconductor chip holders in the lead frame and the semiconductor chip, An apparatus for manufacturing a semiconductor device, comprising: a mechanism for rotating the fixing block connected to the above; and a mechanism for curing the adhesive. 【請求項８】 複数個の半導体チップと複数個のリード
フレームとを一時的に固定可能な固定ブロックを有し、
複数個の半導体チップを前記固定ブロック上に供給する
機構と、複数個のリードフレームを前記固定ブロックと
前記半導体チップとの上に搬送する機構と、複数個の前
記リードフレーム中のすべての半導体チップ保持部と複
数個の前記半導体チップとの間隙に接着剤を塗布する機
構と、前記接着剤を硬化する機構とを有する半導体装置
の製造装置。8. A fixing block for temporarily fixing a plurality of semiconductor chips and a plurality of lead frames,
A mechanism for supplying a plurality of semiconductor chips onto the fixed block, a mechanism for transporting a plurality of lead frames onto the fixed block and the semiconductor chip, and all the semiconductor chips in the plurality of lead frames An apparatus for manufacturing a semiconductor device, comprising: a mechanism for applying an adhesive to a gap between a holding unit and a plurality of the semiconductor chips; and a mechanism for curing the adhesive.
JP9278372A 1997-10-13 1997-10-13 Method and device for manufacture of semiconductor device Pending JPH11121499A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9278372A JPH11121499A (en) 1997-10-13 1997-10-13 Method and device for manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9278372A JPH11121499A (en) 1997-10-13 1997-10-13 Method and device for manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH11121499A true JPH11121499A (en) 1999-04-30

Family

ID=17596426

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9278372A Pending JPH11121499A (en) 1997-10-13 1997-10-13 Method and device for manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH11121499A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002050643A (en) * 2000-07-03 2002-02-15 Esec Trading Sa Method and apparatus for mounting semiconductor chip on flexible substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002050643A (en) * 2000-07-03 2002-02-15 Esec Trading Sa Method and apparatus for mounting semiconductor chip on flexible substrate

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