JPH11134878A - Non-volatile semiconductor memory - Google Patents

Abstract

(57) [Problem] To provide a nonvolatile semiconductor memory capable of minimizing a difference in read speed and a difference in read margin according to a selected memory cell. SOLUTION: In order to read data from a memory cell storing a plurality of bits of data to a column line by changing the amount of charge stored in a floating gate, a column line potential is set to a plurality of reference potentials (1A, 1B, 2A). , 2B, 3A, and 3B) and a plurality of sense amplifiers (1A,
1B, 2A, 2B, 3A, 3B) and switch circuits (SW1, SW) for switching the reference potential supplied to the sense amplifier between normal reading and verify reading.
2).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory, and more particularly to a nonvolatile semiconductor memory in which one memory cell stores data of a plurality of bits.

[0002]

2. Description of the Related Art A nonvolatile semiconductor memory in which two bits of data are stored in one nonvolatile memory cell is disclosed in Japanese Patent Laid-Open No. 59-121 proposed by the present inventors.
No. 696.

In this conventional memory, a sense amplifier unit as shown in FIG. 17 is used, and a relationship between potential levels as shown in FIG. 18 is used. As shown in FIG. 17, three sense amplifiers 1, 2, and 3 and reference potentials 1, 2, and 3 are provided.
The bit line potential read from the memory cell to the bit line is compared with a reference potential by a sense amplifier to detect stored data. That is, the sense amplifiers 1, 2, and 3, to which the reference potentials 1, 2, and 3 are input, respectively, compare the bit line potential with the reference potentials 1, 2, and 3, and determine where the bit line potential is located with respect to the reference potential. 2 bits of data are read depending on whether the data is read.

In this case, as shown in Tables 1 and 2 below, if the bit line potential is lower than the reference potentials 1, 2, and 3, the outputs 1, 2, which are the outputs of the sense amplifiers 1, 2, and 3, respectively. , 3 are both '0', which are detected by, for example, a logic circuit (not shown) and D1 = '0' and D2 = '0' are output as storage data of the memory cells.

[0005]

[Table 1]

[0006]

[Table 2]

Similarly, if the bit line potential is a potential between reference potentials 1 and 2, output 1 is "1" and outputs 2, 3
Are both '0', which are detected by the logic circuit, and D1 = '0' and D2 =
'1' is output.

The combination of the two bits of data is 4
These four types are stored by changing the injection amount of electrons into the floating gate of the nonvolatile memory cell to four types and setting the threshold voltage of the memory cell to four types Vth1 to Vth4 corresponding to the injection amount. ing.

That is, if the bit line potential is lower than the smallest reference potential 1 among the reference potentials, two-bit data of '00' is stored (the state where the threshold voltage is lowest = Vth
1) If the bit line potential is higher than the largest reference potential 3 among the reference potentials, the data “11” is stored (the state where the threshold voltage is the highest = Vth4), and the bit line potential is set to the reference potential 1 and the reference potential. If it is between the potentials 2, the data of '01' is stored (threshold voltage having the third highest voltage = Vth2), and if the bit line potential is between the reference potentials 2 and 3, '10' is stored.
(The state where the threshold voltage is the second highest = Vth3).

Here, a sectional structure of the nonvolatile memory cell will be described. FIG. 19A shows a memory cell having no offset gate portion, and FIG. 19B shows a memory cell having an offset gate in which a part of a channel is controlled by a control gate.

At the time of erasing data from these memory cells, the control gate is set to 0 V, and a high voltage is applied to the drain or source in the memory cell of FIG. In a memory cell, a high voltage is applied to a drain to emit electrons from a floating gate.

At this time, in the memory cell of the type shown in FIG. 19A, the threshold voltage of the memory cell must be kept from becoming negative, so that the control becomes complicated. Since the memory cell has an offset gate, the threshold voltage of the transistor portion having the channel region controlled by the floating gate may be a negative value, which has an advantage that the control at the time of erasing is simplified.

However, the size of the memory cell is as shown in FIG.
The memory cell of the type (a) has an advantage that it can be smaller than the memory cell of the type in FIG. Next, general writing and erasing (writing of a kind of data) of data to the memory as described above will be described with reference to a timing chart of FIG.

At the time of data writing, predetermined voltages are respectively applied to the drain and the control gate of the memory cell, the source is set to 0 V, a current flows through the memory cell, and electrons are injected into the floating gate. When writing data, the data is read from the memory cell after the writing (verify reading), and the writing and reading are repeated until the output result from the sense amplifiers 1, 2, and 3 matches the data to be written. Sometimes I stop writing. The coincidence may be determined by reading the data externally and judging externally, or the coincidence may be determined inside the memory chip. ) To detect after.

At the time of erasing data, the control gate of the memory cell is set to 0 V, a high voltage is applied to the drain or source, and electrons are emitted from the floating gate to the drain or source. The state erased in this way corresponds to the state where the data of Vth1, which is the lowest threshold voltage in Table 2, that is, '00' is stored. When erasing data,
After erasing, verify reading is performed, and whether the bit line potential is lower than reference potential 1 is detected by a sense amplifier, erasing and verify reading are repeated, and erasing ends when a predetermined threshold voltage is reached. Thereafter, the above-described data writing is performed.

In a nonvolatile semiconductor memory in which such nonvolatile memory cells are arranged in a matrix,
For example, the potential of the bit line can be set between the reference potential 1 and the reference potential 2 according to the data stored in the memory cell.

However, since the write characteristics of the memory cells are different for each memory cell, depending on the write characteristics of the selected memory cell, between the reference potential 1 and the reference potential 2 or between the reference potential 2 and the reference potential. 3, the potential of the bit line differs for each of the selected memory cells. Therefore, conventionally, the read speed differs depending on the selected memory cell.

That is, in FIG. 18, the bit line potential is represented by one line, but actually, for example, the bit line potential 2 is shown in FIG. 18 according to the selected memory cell. Since there exists a distribution having distributions above and below the line 2, the reading speed was different (was varied) depending on where the selected memory cell belongs to the distribution.

When the potential of the bit line between the reference potential 1 and the reference potential 2 or between the reference potential 2 and the reference potential 3 is closer to the reference potential on either side, the potential is close. There is also a problem that a margin at the time of reading is reduced with respect to the reference potential.

FIG. 21 shows the state of the distribution of the threshold voltage of such a memory cell. That is, the threshold voltage of the memory cell is V
Even if it is attempted to set th1 to Vth4, there is a certain distribution for each set threshold voltage due to variations in characteristics of each memory cell. Further, this distribution changes depending on each chip as shown by the broken line itself. For this reason, the read speed and the read margin are different for each chip.

[0021]

As described above, the conventional nonvolatile semiconductor memory has different write characteristics for each memory cell, so that the read speed is different depending on the selected memory cell. Therefore, there is a problem that the read speed and the read margin are different for each chip.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a nonvolatile semiconductor memory capable of minimizing a difference in read speed and a difference in read margin according to a selected memory cell. Aim.

[0023]

A nonvolatile semiconductor memory according to the present invention comprises a row line, a column line, a drain, a source, a floating gate connected to the column line, and a control gate connected to the row line. A memory cell that stores a plurality of bits of data by varying the amount of charge stored in the floating gate; and a plurality of reference potentials and a potential of the column line when reading data from the memory cell. A sense amplifier for comparing and detecting data stored in the memory cell; writing data to the memory cell; verify reading for checking the accumulation state of the charge of the floating gate after the writing; and verify reading When it is determined that the desired data has been written, the writing is terminated, and the desired data is written by the verify read. Program means for repeatedly performing the writing and the verify reading until it is determined that desired data has been written when it is determined that the desired data has not been written, wherein the sense amplifier has a plurality of first reference potentials as a plurality of reference potentials. Normal reading is performed using at least six reference potentials whose potentials are sequentially set higher in the order of a second reference potential, a third reference potential, a fourth reference potential, a fifth reference potential, and a sixth reference potential. When the potential of the column line is
Whether it is lower than the second reference potential, between the first reference potential and the fourth reference potential, or between the third reference potential and the sixth reference potential The data is read by detecting whether the potential is higher than the fifth reference potential. In the verify reading, the potential of the column line is set between the second reference potential and the third reference potential. , Or between the fourth reference potential and the fifth reference potential or higher than the sixth reference potential to read data.

Further, the nonvolatile semiconductor memory of the present invention comprises:
A row line, a column line, a drain connected to the column line, a source, a floating gate, and a control gate connected to the row line, by varying the amount of charge stored in the floating gate. A memory cell that stores a plurality of bits of data, a sense amplifier that detects data stored in the memory cell by comparing a plurality of reference potentials and a potential of the column line when reading data from the memory cell, Write data to the memory cell, verify read to check the charge accumulation state of the floating gate after the write, and when it is determined that desired data has been written by the verify read, the write is terminated. When it is determined that the desired data has not been written by reading, it is determined that the desired data has been written. Until then and a repeated program means and said verify reading and the writing, the sense amplifier, as a plurality of reference potential, first
At least six reference potentials whose potentials are sequentially set higher in the order of the reference potential, the second reference potential, the third reference potential, the fourth reference potential, the fifth reference potential, and the sixth reference potential; A seventh reference potential set to a potential between the first reference potential and the second reference potential, and an eighth reference potential set to a potential between the third reference potential and the fourth reference potential. Using a reference potential and a ninth reference potential set to a potential between the fifth reference potential and the sixth reference potential, during normal reading, the potential of the column line is set to the second reference potential. Lower than a reference potential, between the first reference potential and the fourth reference potential,
The data is read by detecting whether the potential is between the third reference potential and the sixth reference potential or higher than the fifth reference potential. At the time of the verify read, the data is read from the column line. The potential is equal to the seventh reference potential and the eighth reference potential.
The data is read out by detecting whether it is between the reference potential of the second reference potential, the eighth reference potential and the ninth reference potential, or higher than the ninth reference potential. Features.

Further, the nonvolatile semiconductor memory of the present invention comprises:
A row line, a column line, a drain connected to the column line, a source, a floating gate, and a control gate connected to the row line, by varying the amount of charge stored in the floating gate. A memory cell that stores a plurality of bits of data, a sense amplifier that detects data stored in the memory cell by comparing a plurality of reference potentials and a potential of the column line when reading data from the memory cell, Write data to the memory cell, verify read to check the charge accumulation state of the floating gate after the write, and when it is determined that desired data has been written by the verify read, the write is terminated. When it is determined that the desired data has not been written by reading, it is determined that the desired data has been written. Until then and a repeated program means and said verify reading and the writing, the sense amplifier, as a plurality of reference potential, first
And at least four reference potentials of at least two reference potentials higher than the first reference potential and a second reference potential higher than the at least two reference potentials. Detecting whether the potential of the line is lower than a first reference potential, between at least two reference potentials higher than the first reference potential, or higher than the second reference potential; In the case of the verify read, a reference potential of a lower potential than the lower reference potential of the at least two reference potentials and a reference potential of a higher potential than the higher reference potential of the at least two reference potentials are read. Data is read by detecting whether the potential is higher than the potential or higher than a reference potential lower than the second reference potential.

Also, the nonvolatile semiconductor memory of the present invention
A row line, a column line, a drain connected to the column line, a source, a floating gate, and a control gate connected to the row line, by varying the amount of charge stored in the floating gate. A memory cell that stores a plurality of bits of data, a sense amplifier that detects data stored in the memory cell by comparing a plurality of reference potentials and a potential of the column line when reading data from the memory cell, Potential setting means for setting the plurality of reference potentials supplied to the sense amplifier to a predetermined potential after manufacturing the nonvolatile semiconductor memory is provided.

Further, the nonvolatile semiconductor memory of the present invention comprises:
A memory cell in which a gate is connected to a row line, a column line, and the row line, and a drain is connected to the column line, and a reference potential is compared with a potential of the column line when data is read from the memory cell. And a sense amplifier for detecting data stored in the memory cell, and setting the reference potential corresponding to the potential of the column line so as to increase the potential difference from the potential of the column line. A reference potential setting means is provided.

Further, the nonvolatile semiconductor memory of the present invention comprises:
A row line, a column line, a memory cell having a drain connected to the column line, and a reference potential and a potential of the column line at the time of reading data from the memory cell are stored in the memory cell. A sense amplifier for detecting data; and reference potential setting means for setting the reference potential so as to increase the potential difference between the potential of the column line and the potential of the column line in accordance with the potential of the column line. Features.

[0029]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a part of the nonvolatile semiconductor memory according to the first embodiment of the present invention. The memory shown in FIG. 1 has, for example, a memory cell array in which memory cells of the type described above with reference to FIG. 19A are arranged in a matrix.

In FIG. 1, 1 is a memory cell arranged in a matrix, WL is a word line (row line), BL is a bit line (column line), SL is a source line, 2 is a row decoder,
Is a column decoder, 4 is a column selection transistor, 5 is a bit line load transistor, 6 is a bit line potential clamp transistor for setting the drain voltage of the memory cell to a predetermined value, and 7 is a bias potential at the gate of the bit line potential clamp transistor. Is applied to the bias circuit.

The memory cell 1 has a drain, a source,
It has a floating gate and a control gate, and stores a plurality of bits (two bits in this example) of data by varying the amount of charge stored in the floating gate. The drain is connected to the bit line BL, the source is connected to the source line SL, and the control gate is connected to the word line WL.

Reference numeral 8 denotes data writing to the memory cell 1, verify reading for checking the accumulation state of the electric charge of the floating gate after the writing, and writing when desired data is determined to have been written by the verify reading. Is completed, and when it is determined that the desired data has not been written by the verify reading, a program means for controlling the writing and the verify reading to be repeated until it is determined that the desired data has been written. A sequence control circuit is used.

Hereinafter, a plurality of embodiments in the case where 2-bit data is stored in one memory cell will be described. <First Embodiment> FIG. 2 shows a sense amplifier unit of a read system according to a first embodiment of the semiconductor memory of FIG.

In the first embodiment, six sense amplifiers 1A, 1B, 2A, 2B, 3A, 3B (first sense amplifier 21 to sixth sense amplifier 26) and six sense amplifiers (first to sixth sense amplifiers 26) are used. ) Reference potentials 1A, 1B, 2A, 2B, 3A, 3B.

In FIG. 2, six sense amplifiers 1A,
1B, 2A, 2B, 3A, and 3B are bit line potentials (potentials of column lines, in this example, load transistors in FIG. 1) from which data is read from the memory cells when data stored in the memory cells are read. 5 and the bit line potential clamp transistor 6).

The six sense amplifiers 1A, 1A,
B, 2A, 2B, 3A, 3B correspond to the second reference potential 1B, the first reference potential 1A, the fourth reference potential 2B, respectively, when data is read from the memory cell 1.
A third reference potential 2A, a sixth reference potential 3B, and a fifth reference potential 3A are supplied.

Thus, when reading data from the memory cell 1, the six sense amplifiers 1A, 1A
B, 2A, 2B, 3A, and 3B detect data by comparing corresponding two inputs.

FIG. 3 shows the six reference potentials 1A, 1A in FIG.
B, 2A, 2B, 3A, 3B and the threshold voltage V of the memory cell
The level relationship between bit line potentials 1 to 4 determined according to th1 to Vth4 is shown.

Here, the reference potential is the first reference potential 1
A, second reference potential 1B, third reference potential 2A, fourth reference potential 2B, fifth reference potential 3A, sixth reference potential 3
The potentials are set higher in the order of B.

Next, an outline of the operation of the first embodiment will be described. At the time of erasing the data of the memory cell, the bit line potential after erasing is set to be lower than the reference potential 1A.

At the time of data writing, the threshold voltage Vth2
For the memory cell that is to be set to the threshold voltage Vth3, it is detected that the bit line potential is set between the reference potentials 1B and 2A, and the writing is stopped. , Detecting that the bit line potential is set between the reference potentials 2B and 3A and stopping the writing,
For a memory cell to be set to the threshold voltage VVth4, writing is stopped by detecting that the bit line potential is set higher than the reference potential 3B.

In other words, at the time of verify reading for checking whether or not predetermined data has been written after writing of data to the memory cell, the bit line potential is set to the second reference potential 1B and the third reference potential. The data is read out by detecting whether it is between 2A, between the fourth reference potential 2B and the fifth reference potential 3A, or higher than the sixth reference potential 3B.

On the other hand, at the time of normal reading, the bit line potential is lower than the second reference potential 1B or the first reference potential 1B.
Or the bit line potential is between the third reference potential 2A and the sixth reference potential 3B.
, Or is set higher than the fifth reference potential 3A to read data.

For example, when data is read from a memory cell having a threshold voltage of Vth2, it is detected during normal reading that there is a bit line potential between the first reference potential 1A and the fourth reference potential 2B. At the time of verify reading, it detects that there is a bit line potential between the second reference potential 1B and the third reference potential 2A (within a voltage range narrower than that during normal reading).

When data is read from a memory cell having a threshold voltage of, for example, Vth3, it is determined that there is a bit line potential between the third reference potential 2A and the sixth reference potential 3B during normal reading. At the time of detection and verify reading, it is detected that the bit line potential exists between the fourth reference potential 2B and the fifth reference potential 3A (within a voltage range narrower than that during normal reading).

In the above example, the reference potentials 2B and 2B are used when reading data from the memory cell having the threshold voltage Vth2 and when reading data from the memory cell having the threshold voltage Vth3.
Although A is shared, it is needless to say that it is not necessary to share as described above if a reference potential having the same relationship as the above-mentioned potential relationship is used. Next, in the data read operation in the first embodiment, FIGS.
This will be described in detail with reference to the truth table of Table 3 below.

[0047]

[Table 3]

At the time of normal reading, the bit line potential from the memory cell and the second reference potential 1B are input to the first sense amplifier 1A. When the bit line potential is lower than the reference potential 1B, the output of the sense amplifier 1A is output. 1 is set to '0', and when high, the output 1 of the sense amplifier 1A is set to '1'.

The bit line potential from the memory cell and the first reference potential 1A are input to the second sense amplifier 1B, and when the bit line potential is lower than the reference potential 1A, the output 2A of the sense amplifier 1B is set to ' It is set to 0, and when high, the output 2A of the sense amplifier 1B is set to '1'.

Further, the bit line potential from the memory cell and the fourth reference potential 2B are input to the third sense amplifier 2A. When the bit line potential is lower than the reference potential 2B, the output 2B of the sense amplifier 2A becomes low. It is set to 0, and when high, the output 2B of the sense amplifier 2A is set to '1'.

The bit line potential from the memory cell and the third reference potential 2A are input to the fourth sense amplifier 2B. When the bit line potential is lower than the reference potential 2A, the output 3A of the sense amplifier 2B becomes' It is set to 0, and when high, the output 3A of the sense amplifier 2B is set to '1'.

Further, the bit line potential from the memory cell and the sixth reference potential 3B are input to the fifth sense amplifier 3A. When the bit line potential is lower than the reference potential 3B, the output 3B of the sense amplifier 3A becomes' It is set to 0, and when high, the output 3B of the sense amplifier 3A is set to '1'.

Further, the bit line potential from the memory cell and the fifth reference potential 3A are input to the sixth sense amplifier 3B. When the bit line potential is lower than the reference potential 3A, the output 4 of the sense amplifier 3B becomes' It is set to 0, and when high, the output 4 of the sense amplifier 3B is set to '1'.

One of the two bits of data stored in one memory cell, D1, is when the bit line potential is between the reference potential 2A and the reference potential 3B and higher than the reference potential 3A. The data D2 is determined to be "1", and the other data D2 is determined to be "1" when the bit line potential is between the reference potential 1A and the reference potential 2B and when the bit line potential is higher than the reference potential 3A. Two-bit data (D1, D2) stored in one memory cell is obtained by the following logical expression.

D1 = (output 3A) · (/ output 3B) + (output 4) D2 = (output 2A) · (/ output 2B) + (output 4) As can be seen from this equation, the storage data of the memory cell is Since the output 1 is not used for detection, the first sense amplifier 1
A is not particularly necessary.

However, at the time of verify reading after erasing, the first sense amplifier 1A may detect that the bit line potential has become lower than the first reference potential 1A. Alternatively, at the time of verify reading after erasing, if the second sense amplifier 1B is used to detect that the potential is lower than the first reference potential 1A,
The first sense amplifier 1A becomes unnecessary.

When the first sense amplifier 1A is not used at the time of normal reading, the second sense amplifier 1A is not used.
Since the first reference potential 1A supplied to B and the bit line potential 1 approach each other, the margin may be reduced. The case where the potential difference from such another reference potential may decrease is indicated by adding an asterisk in the truth table of Table 3.

When a memory cell as shown in FIG. 19B is used, electrons can be sufficiently removed from the floating gate at the time of erasing data.
19 (a) and (b). When the memory cell shown in FIGS. 19A and 19B is used, when the bit line potential 4 is set, electrons are sufficiently injected to turn on when selected. Not doing so can increase the margin.

In other words, it is necessary to pay close attention when injecting electrons when setting the bit line potential 2 and the bit line potential 3. In order to improve such a case, the first sense It is preferable to use the output 1 of the amplifier 1A.

The logical expression of the data (D1, D2) for two bits when such an improvement is achieved is shown below. D1 = (output 2B) · (/ output 3B) + (output 3A) ·
(/ Output 3B) + (output 3A) · (/ output 4) + (output 3B) + (output 4) D2 = (output 1) · (/ output 2B) + (output 2A) ·
(/ Output 2B) + (Output 2A) · (/ Output 3A) + (Output 3B) + (Output 4) When reading data from the memory cell, when the bit line potential is stable, the bit line potential is: It is not between the reference potentials 1A and 1B, but is similarly between the reference potentials 2A and 2B.
Between the reference potentials 3A and 3B.

Therefore, the bit potential 3 and the bit line potential 4 for detecting that the storage data D1 is "1"
May be detected as shown in the above logical expression. That is, the bit line potential 3 is higher than the reference potential 2B and lower than the reference potential 3B, or higher than the reference potential 2A and lower than the reference potential 3B, or higher than the reference potential 2A and It is detected whether the potential is lower than 3A and D1 is set to '1' at this time, or
When it is detected that the bit line potential 4 is higher than the reference potential 3A or 3B, D1 is set to "1" at this time.

When detecting the bit potential 2 and the bit line potential 4 for detecting that the storage data D2 is "1", the bit line potential 4 is higher than the reference potential 1B and higher than the reference potential 2B. Is lower than the reference potential 1A and lower than the reference potential 2B, or higher than the reference potential 1A and lower than the reference potential 2A, or the reference potential 3A or the reference potential 3
It is detected that it is higher than B, and at this time, D2 is set to '1'.

As a result, data can be read with the potential difference between the bit line potential and the reference potential being the largest. FIG. 4 shows an example of a reference potential control circuit for changing the reference potential supplied to the sense amplifier section between the verify read operation and the normal read operation in the first embodiment. 2 shows an example of a reference potential switching circuit to be supplied to a sense amplifier.

In the reference potential switching circuit shown in FIG. 4, switching circuits SW1 and SW2 are each provided with a first CMO.
An S transfer gate TG1 to a sixth CMOS transfer gate TG6.
A reference potential 1A corresponding to each end of the transfer gate,
1B, 2A, 2B, 3A, and 3B are input.

The first to sixth switching circuits SW1
Of the CMOS transfer gates are controlled to be turned on when the signal NR is “0” and the signal VER is “1” (at the time of verify reading), and the sense amplifiers 1A, 1B, and 2A correspond to the outputs at the other ends. , 2B, 3A and 3B.

On the other hand, the switching circuit SW
The second to sixth CMOS transfer gates are controlled to be on when the signal NR is “1” and the signal VER is “0” (during normal reading), and correspond to the output at the other end. And sense amplifiers 1B, 1A, 2B, 2A, 3B,
3A.

Next, the operation of the reference potential switching circuit of FIG. 4 will be described. At the time of normal reading, the signal NR becomes “1”,
The signal VER is set to “0”, the switching circuit SW1 is turned off, and the switching circuit SW2 is turned on. Thereby, the sense amplifier 1 is connected through the switching circuit SW2.
A is supplied with reference potential 1B, sense amplifier 1B is supplied with reference potential 1A, sense amplifier 2A is supplied with reference potential 2B, and sense amplifier 2B is supplied with reference potential 2A.
Is supplied, the reference potential 3B is supplied to the sense amplifier 3A, and the reference potential 3A is supplied to the sense amplifier 3B.

On the other hand, at the time of verify reading, the signal NR is set to "0", the signal VER is set to "1", the switching circuit SW1 is turned on, and the switching circuit SW2 is turned off. Thus, the reference potential 1A is supplied to the sense amplifier 1A, the reference potential 1B is supplied to the sense amplifier 1B, the reference potential 2A is supplied to the sense amplifier 2A, and the sense amplifier 2 is supplied through the switching circuit SW1.
Reference potential 2B is supplied to B, reference potential 3A is supplied to sense amplifier 3A, and reference potential 3B is supplied to sense amplifier 3B.

FIG. 5 shows, as another example of the reference potential control circuit in the first embodiment, a reference potential variable circuit for changing the reference potential itself supplied to the sense amplifier between normal reading and verify reading. The circuit is shown.

That is, in the reference potential variable circuit shown in FIG. 5, reference numeral 50 denotes a voltage dividing circuit in which a plurality of NMOS transistors are connected in series between a power supply potential and a ground potential, for example. Of the two nodes N1 and N2 are selectively used.

The potential at the node N1 is determined by the signal NR being "1".
At the time of (normal reading), the potential is taken out through the transistor TR1 which is controlled to the on state, and the potential of the node N2 is controlled to the on state when the signal VER is "1" (at the time of verify reading). Taken out through.

The potential extracted through the transistor TR1 or TR2 is applied to the gate electrode of the dummy cell DM (the electrode corresponding to the floating gate of the memory cell). In the dummy cell DM, the source side is grounded and the drain side is connected to the load transistor L1.
A reference potential output from a connection point between the dummy cell DM and the load transistor L1 is supplied to the sense amplifier.

Next, the operation of the reference potential variable circuit of FIG. 5 will be described. The reference potential variable circuit of FIG. 5 supplies a potential to the gate electrode of the dummy cell DM, and changes the reference potential between normal reading and verify reading to change the reference potential.

Since the channel region of the memory cell is substantially controlled by the potential of the floating gate, a voltage is directly applied to the gate electrode corresponding to the floating gate of the dummy cell DM equivalent to the memory cell as shown in FIG. If supplied, the state of the potential of the floating gate of the memory cell can be made in the dummy cell DM, so that the reference potential can be accurately made in accordance with the accumulation state of the electric charge of the floating gate of the memory cell.

When generating the reference potential 1A, the potential between the floating gate potential of the memory cell at the bit line potential 1 and the potential of the floating gate of the memory cell at the bit line potential 2 is set to the gate electrode of the dummy cell DM. What is necessary is just to supply to.

When the reference potential 1B is generated, the potential of the floating gate of the memory cell when the bit line potential is 1 and the potential of the floating gate of the memory cell when the bit line potential is 2 are set at the reference potential 1A. What is necessary is just to supply a predetermined potential lower than the gate potential to the gate electrode of the dummy cell DM.

When generating the reference potential 2A, the potential between the floating gate potential of the memory cell when the bit line potential is 2 and the floating gate potential of the memory cell when the bit line potential is 3 is set to the gate electrode of the dummy cell DM. What is necessary is just to supply to.

When the reference potential 2B is generated, the potential of the floating gate of the memory cell at the bit line potential 2 and the potential of the floating gate of the memory cell at the bit line potential 3 is set at the reference potential 2A. What is necessary is just to supply a predetermined potential lower than the gate potential to the gate electrode of the dummy cell DM.

When the reference potential 3A is generated, the potential between the floating gate potential of the memory cell when the bit line potential is 3 and the floating gate potential of the memory cell when the bit line potential is 4 is set to the gate electrode of the dummy cell DM. What is necessary is just to supply to.

When the reference potential 3B is generated, the potential of the floating gate of the memory cell at the bit line potential 3 and the potential of the floating gate of the memory cell at the bit line potential 4 are set at the reference potential 3A. What is necessary is just to supply a predetermined potential lower than the gate potential to the gate electrode of the dummy cell DM.

For example, FIG. 5 shows an example in which the reference potential is supplied to the sense amplifier 2A in FIG. 2 in the first embodiment. In the case of normal reading, the signal NR is "1" and the signal VER is Since the transistor TR1 is turned on and the transistor TR2 is turned off, the potential of the node N1 of the voltage dividing circuit 50 is supplied to the gate electrode corresponding to the floating gate of the dummy cell DM through the transistor TR1. The reference potential 2B is output from the connection point with the load transistor L1 and supplied to the sense amplifier 2A.

In the case of verify reading, the signal N
R is set to “0”, the signal VER is set to “1”, the transistor TR1 is turned off, and the transistor TR2 is turned on. Therefore, the potential of the node N2 higher than the potential of the node N1 of the voltage dividing circuit 50 passes through the transistor TR2. The reference potential 2A that is supplied to the gate electrode corresponding to the floating gate of the dummy cell DM and is lower than the reference potential 2B by a predetermined potential from the connection point between the dummy cell DM and the load transistor L1 is output and supplied to the sense amplifier 2A. In other sense amplifiers, voltage division is performed so that a predetermined potential is applied to the gate electrode corresponding to the floating gate of the dummy cell DM to obtain a necessary reference potential during normal reading and verify reading. The potential at the corresponding node of the circuit is supplied through a transistor which is controlled by switching.

That is, as described above, in the first embodiment, when detecting the memory cells having the threshold voltages Vth2 and Vth3, the same reference potential 2 as in the conventional example shown in FIG. Instead of detecting whether the potential is lower or higher than the potential, when detecting the memory cell of Vth2 as shown in FIG. 3, it is determined whether or not the potential is lower than the reference potential 2B. When a cell is detected, it is detected whether or not the potential is higher than the reference potential 2A, which is lower than the reference potential 2B.

That is, since different reference potentials are used to detect Vth2 and Vth3, the potential difference between the reference potential and the bit line potential can be increased, thereby increasing the read speed and The read margin can be increased.

<Second Embodiment> In this second embodiment, FIG.
As shown in FIG. 7, at the time of verify reading, the reference potentials 1A, 1B, 2A, 2B, 3A,
Verify read is performed using 3B to detect whether the bit line potential is set to a predetermined potential. During normal reading, a reference potential is provided between the reference potentials 1A and 1B, between the reference potentials 2A and 2B, and between the reference potentials 3A and 3B, respectively, and the three reference potentials are used. Perform reading.

Even in this case, compared to the conventional example,
The difference between the bit line potential and the reference potential can be increased, the margin can be widened, and the number of sense amplifiers at the time of normal reading can be three, so that the current consumption in the sense amplifier unit can be suppressed to the same level as in the conventional case.

<Third Embodiment> In the third embodiment, FIG.
As shown in FIG. 7, during normal reading, the reference potentials 1A, 1B, 2A, 2B, 3A, 3B
Is read by using. At the time of verify read, the reference potentials 1A and 1B and the reference potentials 2A and 2A
B, and a reference potential is provided between the reference potentials 3A and 3B, respectively, and it is detected whether or not the bit line potential is set to a predetermined potential using the three reference potentials.

Even in such a case, compared to the conventional example,
The difference between the bit line potential during normal reading and the reference potential can be increased, and the margin is increased. By the way, as shown in FIG. 21, the threshold voltage of the memory cell after erasing and writing data varies with a certain distribution for each set threshold voltage due to variation in characteristics of each memory cell. Further, this distribution changes depending on each chip as shown by the broken line itself. A fourth embodiment which addresses such a problem will be described below.

<Fourth Embodiment> FIG. 8 shows a sense amplifier unit of a read system according to a fourth embodiment of the semiconductor memory of FIG.

In the sense amplifier section shown in FIG. 8, three sets of reference potentials having different potentials are prepared, and one of the three sets of reference potentials has three switches controlled by signals S1 to S3. Circuits 1 to 3 (first switch circuits 84 to
The data is read by being selected by the third switch circuit 86 and supplied to the three sense amplifiers 1 to 3 (the first sense amplifier 81 to the third sense amplifier 83).

When the signal S1 is "1" and the signals S2 and S3 are both "0", the switch circuit 1 is selected, and the reference potentials 1A, 2A and 3A are respectively passed through the switch circuit 1 to the sense amplifiers. 1, 2 and 3.

When the signal S2 is "1" and the signals S1 and S3 are both "0", the switch circuit 2 is selected, and the reference potentials 1B, 2B and 3B respectively correspond to the sense amplifiers through the switch circuit 2. 1, 2 and 3.

When the signal S3 is "1" and the signals S1 and S2 are both "0", the switch circuit 3 is selected, and the reference potentials 1C, 2C and 3C are respectively passed through the switch circuit 3 to the corresponding sense amplifiers. 1, 2 and 3.

FIG. 9 shows the relationship between the levels of the reference potentials. For example, the reference potentials 1A, 1B, and 1C supplied as the reference potential 1 to the sense amplifier 1 are sequentially increased in this order. . That is, the reference potential 1 supplied through the switch circuit 1 is the lowest among the reference potentials 1, 2, and 3, and the reference potential 2 supplied through the switch circuit 2 is 2 among the reference potentials 1, 2, and 3. The second highest potential, the reference potential 3 supplied through the switch circuit 3,
This is the highest potential among the reference potentials 1, 2, and 3.

The control for setting the signals S1 to S3 to "0" or "1" is performed by a fuse element (not shown).
May be provided and the corresponding fuse element may be cut off to set the same, or the same transistor as the memory cell (not shown)
And it may be set depending on whether or not electrons are injected into the floating gate.

FIG. 8 shows an example in which three sets of reference potentials having different potentials are prepared. However, the present invention is not limited to three sets, and a plurality of sets of reference potentials may be prepared. That is, as described above, in the fourth embodiment, a plurality (n) sets of reference potentials are prepared, and the distribution and variation of the bit line potentials corresponding to the respective stored data are checked for each chip, and a plurality of signal potentials are determined. In S1 to Sn, an optimal set of reference potentials is selected and supplied to the sense amplifier. As a result, the optimum reference potential can be supplied to each chip, so that there is an advantage that the data reading speed is improved.

<Fifth Embodiment> FIG. 10 shows a read sense amplifier section according to a fifth embodiment of the semiconductor memory of FIG.

FIG. 11 shows the reference potentials 1, 2, 3 in FIG.
And the bit line potentials 1, 2, 3, and 4. In the fifth embodiment, three sense amplifiers 1, 2,
3 (the first sense amplifier 101 to the third sense amplifier 1
03) and six (first to sixth) reference potentials 1A, 1B, 2
A, 2B, 3A and 3B, and the sense amplifier 1
By changing the reference potentials 1, 2, and 3 supplied to 2, 3 according to the bit line potential at the time of normal reading, a margin at the time of normal reading is increased.

At the time of verify read, the same read method as in each of the above-described embodiments may be applied, or the read method of the conventional example may be applied. Next, a reading method during normal reading according to the fifth embodiment will be described. For example, when detecting the bit line potential 1, the reference potential 1B shown in FIG. 11 is supplied to the sense amplifier 1 as the reference potential 1, and the reference potential 2B shown in FIG. , The reference potential 3B shown in FIG.

As a result, the bit line potential 1 becomes the reference potential 1
B is compared with the sense amplifier 1, and the potential difference between them can be increased. That is, for example, when data is output to the outside, a margin can be increased with respect to fluctuation of the power supply voltage due to a current when charging and discharging the external terminal.

Next, when a different memory cell is selected and the bit line potential changes from bit line potential 1 to bit line potential 2, the bit line is charged and the bit line potential is changed to the reference potential. 1B, the output 1 of the sense amplifier 1 changes its logic level from “0” to “1”. Based on this change, the reference potential 1 supplied to the sense amplifier 1 changes to the reference potential 1A. It is controlled to change.

Thus, when the bit line potential reaches the position of bit line potential 2, the potential difference between bit line potential 2 and reference potential 1 (reference potential 1A) can be increased. As described above, the power supply fluctuation is large when data is output to the outside. At this time, if the difference between the reference potential and the bit line potential is small, the power supply changes in the opposite potential directions. When you do, the data comes out by mistake.

Therefore, as described above, it is better that the difference between the reference potential and the bit line potential is large. However, in the fifth embodiment,
The output of the sense amplifier section changes, and this change is transmitted to, for example, an output buffer circuit (not shown), and the reference potential 1 is changed from 1B to 1A in a time until data is output from the output buffer circuit to the outside. Since the difference between the reference potential and the bit line potential is increased, the read margin can be increased.

The reference potentials 2 and 3 supplied to the sense amplifiers 2 and 3 at the time of the bit line potential 2 are equal to the bit line potential 1
Does not change from the time when is detected. When the bit line potential changes from bit line potential 2 to bit line potential 1, the bit line is discharged. When the bit line potential becomes lower than reference potential 1A, output 1 of sense amplifier 1 changes its logic level, Based on this change, control is performed so that the reference potential 1 supplied to the sense amplifier 1 changes to the reference potential 1B.

When the bit line potential 2 changes to the bit line potential 3, the bit line is charged, and when the bit line potential becomes higher than the reference potential 2B, the output 2 of the sense amplifier 2 is output. The logic level is changed, and based on this change, control is performed such that the reference potential 2 supplied to the sense amplifier 2 changes to the reference potential 2A. At this time, the reference potential supplied to the sense amplifiers 1 and 3 does not change.

When the bit line potential 3 changes to the bit line potential 2, the bit line is discharged. When the bit line potential becomes lower than the reference potential 2A, the output 2 of the sense amplifier 2 changes its logic level. And the reference potential 2 supplied to the sense amplifier 2 based on this change is changed to the reference potential 2
B is controlled to change.

When the bit line potential 3 changes to the bit line potential 4, the bit line is charged, and when the bit line potential becomes higher than the reference potential 3B, the output 3 of the sense amplifier 3 is output. The logic level is changed, and based on this change, control is performed so that the reference potential 3 supplied to the sense amplifier 3 changes to the reference potential 3A. At this time, the reference potential supplied to the sense amplifiers 1 and 2 does not change. Table 4 below shows the outputs 1 to 3 of the sense amplifiers 1 to 3 in FIG.
And the data (D1, D2) stored in the memory cells.

[0108]

[Table 4]

<Reference Potential Supply Circuit 1 of Fifth Embodiment> FIG.
2 shows an example of a circuit for supplying a reference potential to the sense amplifier section in the fifth embodiment.

In the reference potential supply circuit shown in FIG.
The sense amplifier 1 includes a pair of NMOS transistors for inputting a bit line potential and a reference potential to a gate, and a pair of NMOS transistors
And a PMOS current mirror circuit connected as a load of the OS transistor. Then, an output obtained by comparing the bit line potential with the reference potential 1 by the voltage comparison circuit is output via the inverter circuit I1.

The output of the sense amplifier 1 is inverted by an inverter circuit I2 to become a signal B, and is inverted by an inverter circuit I4 to become a signal C. On the other hand, the reference potential 1A is equal to the PMOS transistor Tr1 and the NMO
An input to one end of a first switch circuit composed of an S transistor Tr2, the reference potential 1B is applied to a PMOS transistor Tr2.
3 and one end of a second switch circuit composed of an NMOS transistor Tr4. The first switch circuit is controlled by the signal B and a signal obtained by inverting the signal B by an inverter circuit I3, and the second switch circuit is controlled by the signal C and a signal obtained by inverting the signal C by an inverter circuit I5. Is done. In this example, the signal B
Is at the "0" level, the first switch circuit is turned on, and when the signal C is at the "1" level, the second switch circuit is turned on.

The circuit shown in FIG. 12 shows only a circuit portion related to normal reading. FIG. 12 shows a sense amplifier 1 and a reference potential switching circuit for switching and supplying the corresponding reference potential 1, but the sense amplifiers 2 and 3 and their corresponding reference potential switching circuits can be similarly configured.

Next, the operation of the reference potential switching circuit of FIG. 12 will be described. When the bit line potential is the bit line potential 1, the bit line potential is lower than the reference potential 1, so that the node A of the differential sense amplifier 1 becomes "1", and the potential of the node A is input. The output 1 of the sense amplifier 1 which is the output of the inverter I1 becomes '0'. The outputs B and C of the inverters I2 and I4 to which the output 1 is input are both "1", the output / B of the inverter I3 to which the output B is input is "0", and the output C is input. The output / C of the inverter I5 also becomes '0'.

As a result, the transistors Tr1 and Tr2
Is turned off, and the transistors Tr3 and Tr
4 is turned on, and the transistors Tr3 and Tr
4, the reference potential 1B is supplied to the sense amplifier 1 as the reference potential 1.

Next, when the bit line is charged and the bit line potential becomes higher than the reference potential 1B, the node A becomes "0", and the output 1 which is the output of the inverter I1 to which the potential of the node A is input. Becomes '1'. The outputs B and C of the inverters I2 and I4 to which the output 1 is inputted are both "0", the output / B of the inverter I3 to which the output B is inputted becomes "1", and the output C is inputted. The output / C of the inverter I5 also becomes '1'.

As a result, the transistors Tr1 and Tr2
Turns on, the transistor Tr3 and the transistor Tr
4 is turned off, and the transistors Tr1, Tr
2, the reference potential 1A is supplied to the sense amplifier 1 as the reference potential 1.

When the bit line potential changes from bit line potential 2 to bit line potential 1, the bit line is discharged. When the bit line potential becomes lower than reference potential 1A, output 1 of sense amplifier 1 changes to '0'. The outputs B and C of the inverters I2 and I4 to which the output 1 is input are both "1", the output / B of the inverter I3 to which the output B is input is "0", and the output C is the input. The output / C of the inverter I5 also becomes '0'.

As a result, the transistors Tr1 and Tr2
Is turned off, and the transistors Tr3 and Tr
4 is turned on, and the transistors Tr3 and Tr
4, the reference potential 1B is supplied to the sense amplifier 1 as the reference potential 1.

When the bit line potential 2 changes to the bit line potential 3, the bit line is charged.
Since the bit line potential is higher than the reference potential 1, the output 1 of the sense amplifier 1 remains "1", and the reference potential 1A is changed to the reference potential 1 through the transistors Tr1 and Tr2.
Is supplied to the sense amplifier 1.

As described above, in the circuit of FIG. 12, transistors Tr1 and Tr2 are connected to inverters I2 and I2, respectively.
3 and the transistors Tr3 and Tr4 were controlled by the outputs of the inverters I5 and I4, respectively. The reason is that the transistors Tr1, Tr2, Tr3, Tr4 are not turned off at the same time by making the circuit threshold voltages of the inverters different, that is, the transistors Tr1, Tr2, Tr3, Tr4 are turned off at the same time. This is so that the period in which the transistors Tr1 and Tr2 are on and the period in which the transistors Tr3 and Tr4 are on temporarily overlap so that the reference potential 1 does not become electrically floating.

In the circuit of FIG. 12, the capacitor C is connected between the reference potential input node of the sense amplifier 1 and the ground node in order to stabilize the reference potential 1, but this is not particularly necessary.

<Reference potential supply circuit 2 of fifth embodiment> FIG.
3 shows another example of a circuit for supplying a reference potential to the sense amplifier section in the fifth embodiment.

In the reference potential supply circuit shown in FIG.
The sense amplifier 1 includes a pair of NMOS transistors for inputting a bit line potential and a reference potential to a gate, and a pair of NMOS transistors
And a PMOS current mirror circuit connected as a load of the OS transistor. Then, an output obtained by comparing the bit line potential with the reference potential 1 by this voltage comparison circuit is output via the inverter circuit I8.

The output of inverter circuit I8 is inverted by inverter circuit I6 to become signal / VR. On the other hand, the reference potential 1A is input to one end of a first switch circuit including a PMOS transistor Tr1 and an NMOS transistor Tr2, and the reference potential 1B is input to one end of a second switch circuit including a PMOS transistor Tr3 and an NMOS transistor Tr4. The first switch circuit and the second switch circuit are complementarily controlled to be on / off by the signal / VR and the signal VR obtained by inverting the signal / VR by the inverter circuit I7. In this example, when the signal / VR is at the "0" level, the first switch circuit is turned on, and when the signal / VR is at the "1" level, the second switch circuit is turned on.

That is, the reference potential switching circuit of FIG.
Transistor Tr such as the reference potential switching circuit shown in FIG.
1, Tr2, Tr3, Tr4 are not controlled by the outputs of the different inverters, respectively.
Tr4 is the output of the inverter I6, the transistor Tr
2. Tr3 is controlled by the output of the inverter I7, so that the number of inverters is reduced as compared with the reference potential switching circuit in FIG.

In the circuit of FIG. 13, only a circuit portion related to normal reading is shown. FIG.
Although the sense amplifier 1 and the reference potential switching circuit for switching and supplying the corresponding reference potential are shown, the sense amplifiers 2 and 3 and the corresponding reference potential switching circuits can be similarly configured.

Next, the operation of the reference potential switching circuit shown in FIG. 13 will be described. The threshold voltages of the N-channel transistors Tr2 and Tr4 are both set to Vthn, and the P-channel transistor Tr
1. Both the threshold voltage of Tr3 is Vthp (Vthp is a negative value)
And If the output signal of the inverter I6 is / VR and the output signal of the inverter I7 is VR, the reference potential 1A
With respect to, if VR−Vthn ≧ reference potential 1A, reference potential 1 = reference potential 1A.

When VR-Vthn <reference potential 1A, Tr2 is turned off when the potential of reference potential 1 is higher than VR-Vthn, and when lower than VR-Vthn, reference potential 1 is charged to the potential of VR-Vthn. Tr2 is turned off.

If / VR-Vthp <reference potential 1A, reference potential 1 = reference potential 1A. If / VR-Vthp≥reference potential 1A, Tr1 is turned off when the potential of reference potential 1 is lower than / VR-Vthp, and when higher than / VR-Vthp, reference potential 1 is discharged to the potential of / VR-Vthp. Tr1 is turned off.

As for the reference potential 1B, / VR-Vthn
If ≧ reference potential 1B, reference potential 1 = reference potential 1B. If / VR-Vthn <reference potential 1B, Tr4 is turned off when the potential of reference potential 1 is higher than / VR-Vthn, and when lower than / VR-Vthn, reference potential 1 is set to /
Tr4 is turned off by being charged to the potential of VR-Vthn.

If VR-Vthp <reference potential 1B, reference potential 1 = reference potential 1B. VR−Vthp ≧ reference potential 1
In the case of B, when the potential of the reference potential 1 is lower than VR-Vthp, Tr3 is turned off. When the potential is higher than VR-Vthp, the reference potential 1 is discharged to the potential of VR-Vthp and Tr3 is discharged.
3 turns off.

Reference potential 1 is not in an electrically floating state because VR-Vthn ≧ reference potential 1A or / VR-
Vthp <reference potential 1A, or / VR-Vthn ≧ reference potential 1B, or VR-Vthp <reference potential 1B. Here, considering VR,
VR where reference potential 1 is not in an electrically floating state is VR ≧ reference potential 1A + Vthn, or VR <reference potential 1B +
In the case of Vthp, / VR in which reference potential 1 is not in an electrically floating state is the case where / VR <reference potential 1A + Vthp or / VR ≧ reference potential 1B + Vthn.

That is, when the signals / VR and VR fall within the range of the region A or the region B in FIG.
May be in an electrically floating state, but this is not a problem as long as the time is short.

<Reference Potential Supply Circuit 3 of Fifth Embodiment> FIG.
5 shows still another example of the circuit for supplying the reference potential to the sense amplifier section in the fifth embodiment.

In the reference potential supply circuit shown in FIG.
DM is a dummy cell for generating a reference potential formed by a transistor equivalent to a memory cell, and L1 and L2 are PMOSs for a load transistor connected to the dummy cell DM.
A transistor, which supplies a signal output to a connection node between the dummy cell DM and the load transistor to the sense amplifier unit.

In this case, as the load transistors of the dummy cell DM, two first load transistors L1,
Is used. The gate of the first load transistor L1 is connected to the ground potential, and the signal VR is applied to the gate of the second load transistor L2. This signal VR is obtained in the same manner as the signal VR in FIG.

That is, the reference potential supply circuit shown in FIG. 15 switches the reference potential 1A and the reference potential 1B by a switching circuit as in the reference potential supply circuit shown in FIG. 12 or FIG. 1 and a dummy cell DM formed of a transistor equivalent to a memory cell and a first load transistor L1.
And the second load transistor L2 supplies a reference potential.

Although FIG. 15 shows a reference potential supply circuit for supplying a reference potential corresponding to the sense amplifier 1, reference potential supply circuits corresponding to the sense amplifiers 2 and 3 can be similarly configured.

Next, the operation of the reference potential supply circuit of FIG. 15 will be described. When the signal VR is "0", the second load transistor L2 is turned on and the two load transistors L1, L
2 is a load transistor for the memory cell. At this time, a reference potential 1 corresponding to the reference potential 1B is generated.

On the other hand, when the signal VR is "1", the second load transistor L2 is turned off, and only the first load transistor L1 serves as a load transistor for the memory cell. As a result, a voltage corresponding to the reference potential 1A which is lower than when both of the first and second load transistors are turned on is generated.

That is, since the signal VR is '0' when the bit line potential is 1, the second load transistor L2 is turned on, and the reference potential 1 corresponding to the reference potential 1B is supplied to the sense amplifier 1, When the bit line potential rises and becomes higher than the reference potential 1 (reference potential 1B), the signal VR becomes “1”, the second load transistor L2 turns off,
The reference potential 1 is switched to a potential corresponding to the reference potential 1A, which is lower than the reference potential 1B, and supplied to the sense amplifier 1.

When the reference potential supply circuit shown in FIG. 15 is used, the reference potential does not enter an electrically floating state, so that it is not particularly necessary to consider that the reference potential enters an electrically floating state. The fifth embodiment shown in FIGS. 12 to 15 is characterized in that the reference potential is changed in a direction in which the difference between the bit line potential and the reference potential increases in accordance with the change in the bit line potential. Needless to say, the present invention can be applied not only to a configuration in which two-bit data of one memory cell is stored, but also to a configuration in which one-bit data is stored in one memory cell.

In each of the above embodiments, the case where two bits of data are stored in one memory cell has been described as an example. However, the present invention is not limited to this example, and how many bits of data are stored in one memory cell. Needless to say, this may be done.

Next, 1.5 is stored in one nonvolatile memory cell.
A memory for storing bits of data will be described. <Sixth Embodiment> FIG. 16 shows a reference potential and a bit line potential used in a sense amplifier unit when 1.5 bits of data are stored in one memory cell as a sixth embodiment of the semiconductor memory of FIG. Shows the relationship of height.

In the sixth embodiment, four reference potentials 1
Using A, 1B, 3A, and 3B, the bit line potential is classified into three types (bit line potentials 1, 2, and 3), that is, the threshold voltage of one memory cell is classified into three.

Therefore, by using two such memory cells, eight of the nine combinations of the threshold voltages of the two memory cells are selected and three bits of data (D1, D2, D3) are selected. Can be stored.
Also in the sixth embodiment, reading may be performed by a method according to each of the above embodiments.

[0147]

As described above, according to the nonvolatile semiconductor memory of the present invention, the potential difference between the reference potential and the bit line potential during normal reading is smaller than the potential difference between the reference potential and the bit line potential during verify reading. Since the potential difference is made large, the data read margin at the time of normal read can be made larger than before, and the reference potential is set according to the write state of the chip after the chip is completed. Therefore, there is an advantage that the reference potential can be optimally supplied to each chip.

Further, in the nonvolatile semiconductor memory according to the present invention, the reference potential supplied to the sense amplifier is controlled so as to increase the potential difference between the bit line and the reference potential corresponding to the potential of the bit line. In the same manner as described above, the normal read margin can be further increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a part of a nonvolatile semiconductor memory according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a sense amplifier unit of a read system according to the first embodiment of the semiconductor memory of FIG. 1;

FIG. 3 shows a plurality of reference potentials 1A, 1B, 2A, 2 in FIG.
FIG. 7B is a diagram for explaining a level relationship between B, 3A, and 3B and bit line potentials 1 to 4 determined according to threshold voltages of memory cells.

FIG. 4 is a diagram showing a reference potential as an example of a reference potential control circuit for making a reference potential supplied to a sense amplifier unit according to a first embodiment of the semiconductor memory of FIG. 1 different between verify reading and normal reading; FIG. 3 is a circuit diagram illustrating an example of a switching circuit.

5 is a first embodiment of a reference potential control circuit for making a reference potential supplied to a sense amplifier unit different between a verify read operation and a normal read operation according to the first embodiment of the semiconductor memory of FIG. 1; FIG. 4 is a circuit diagram showing a reference potential variable circuit as another example of the reference potential control circuit in FIG.

FIG. 6 is a view for explaining a manner in which a reference potential supplied to a sense amplifier unit according to a second embodiment of the semiconductor memory in FIG. 1 is made different between verify reading and normal reading;

FIG. 7 is a view for explaining a manner in which a reference potential supplied to a sense amplifier unit according to a third embodiment of the semiconductor memory in FIG. 1 is made different between verify reading and normal reading;

FIG. 8 is a block diagram showing a read system sense amplifier unit according to a fourth embodiment of the semiconductor memory of FIG. 1;

FIG. 9 is a diagram for explaining a level relationship between a plurality of sets of reference potentials supplied to sense amplifiers 1, 2, and 3 in FIG. 8;

FIG. 10 is a block diagram showing a sense amplifier unit of a read system according to a fifth embodiment of the semiconductor memory of FIG. 1;

FIG. 11 is a view for explaining a level relationship between reference potentials 1, 2, and 3 and bit line potentials 1, 2, 3, and 4 in FIG. 10;

12 is a circuit diagram illustrating an example of a circuit that supplies a reference potential to a sense amplifier unit in FIG.

FIG. 13 is a circuit diagram showing another example of a circuit for supplying a reference potential to the sense amplifier unit in FIG.

FIG. 14 is a diagram illustrating a range of a region A or B in which signals / VR and VR in FIG. 13 may be in an electrically floating state;

FIG. 15 is a circuit diagram showing still another example of a circuit for supplying a reference potential to the sense amplifier unit in FIG. 10;

FIG. 16 is a view for explaining a level relationship between a reference potential and a bit line potential used in a sense amplifier unit when storing 1.5-bit data in one memory cell as a sixth embodiment of the semiconductor memory of FIG. 1; Shown in

FIG. 17 is a block diagram showing a sense amplifier unit of a read system in a conventional example of a nonvolatile semiconductor memory in which data of two bits is stored in one nonvolatile memory cell.

18 is a diagram illustrating a relationship between a read potential (bit line potential) according to a threshold voltage of a memory cell, a plurality of reference potentials, and two bits of data stored in a memory cell in the memory of FIG. 17; .

FIG. 19 is a view showing a cross-sectional structure of two different examples of a nonvolatile memory cell used in a nonvolatile semiconductor memory in which data of a plurality of bits is stored in one nonvolatile memory cell.

20 is a timing chart shown to explain general writing and erasing of data in a memory cell in the memory of FIG. 17;

21 is a diagram illustrating a state of distribution of threshold voltages of nonvolatile memory cells in the memory of FIG. 17;

[Description of References] SW1, SW2: switch circuit, TG1 to TG6: transfer gate.

Claims (10)

[Claims] An amount of electric charge stored in a floating gate having a row line, a column line, a drain, a source, a floating gate connected to the column line, and a control gate connected to the row line. A plurality of reference potentials and a potential of the column line at the time of reading data from the memory cell to detect data stored in the memory cell. Write data to the memory cell, verify read to check the accumulation state of the charge of the floating gate after the write, and perform write when it is determined that desired data has been written by the verify read. When it is determined that the desired data has not been written by the verify reading, the desired data is written. Program means for controlling the writing and the verify reading to be repeatedly performed until it is determined that the plurality of reference potentials have been detected. The sense amplifier includes a first reference potential, a second reference potential, 3, at least six reference potentials whose potentials are sequentially set higher in the order of a third reference potential, a fourth reference potential, a fifth reference potential, and a sixth reference potential are used. The potential is lower than the second reference potential, between the first reference potential and the fourth reference potential, or between the third reference potential and the sixth reference potential; , Or higher than the fifth reference potential, the data is read out. At the time of the verify readout, the potential of the column line is changed to the second reference potential and the third reference potential. Between or A non-volatile semiconductor memory reading data by detecting whether it is between a fourth reference potential and the fifth reference potential or higher than the sixth reference potential. 2. The nonvolatile semiconductor memory according to claim 1, wherein a reference potential used in said sense amplifier is switched and supplied by a switching means in accordance with said normal reading and said verify reading. Nonvolatile semiconductor memory. 3. An amount of charge stored in the floating gate, comprising a row line, a column line, a drain, a source, a floating gate connected to the column line, and a control gate connected to the row line. A plurality of reference potentials and a potential of the column line at the time of reading data from the memory cell to detect data stored in the memory cell. Write data to the memory cell, verify read to check the accumulation state of the charge of the floating gate after the write, and perform write when it is determined that desired data has been written by the verify read. When it is determined that the desired data has not been written by the verify reading, the desired data is written. Program means for repeatedly performing the writing and the verify reading until it is determined that the reference potential has been lost, wherein the sense amplifier includes a first reference potential, a second reference potential, and a third reference potential as a plurality of reference potentials. , A fourth reference potential, a fifth reference potential, and a sixth reference potential, and at least six reference potentials whose potentials are sequentially set higher in order, and between the first reference potential and the second reference potential. A seventh reference potential set to a potential; an eighth reference potential set to a potential between the third reference potential and the fourth reference potential;
And a ninth reference potential which is set to a potential between the reference potential and the sixth reference potential. During normal reading, the potential of the column line is lower than the second reference potential, Whether it is between the first reference potential and the fourth reference potential, between the third reference potential and the sixth reference potential, or higher than the fifth reference potential And at the time of the verify read, the potential of the column line is between the seventh reference potential and the eighth reference potential, or A non-volatile semiconductor memory reading data by detecting whether it is between the ninth reference potential and higher than the ninth reference potential. 4. An amount of electric charge stored in the floating gate, comprising a row line, a column line, a drain, a source, a floating gate connected to the column line, and a control gate connected to the row line. A plurality of reference potentials and a potential of the column line at the time of reading data from the memory cell to detect data stored in the memory cell. Write data to the memory cell, verify read to check the accumulation state of the charge of the floating gate after the write, and perform write when it is determined that desired data has been written by the verify read. When it is determined that the desired data has not been written by the verify reading, the desired data is written. Program means for repeatedly performing the writing and the verify reading until it is determined that the reference potential has been set, wherein the sense amplifier comprises a plurality of reference potentials, a first reference potential, at least two higher than the first reference potential. One reference potential, at least four reference potentials of a second reference potential higher than the at least two reference potentials, and at the time of normal reading, the potential of the column line is lower than the first reference potential; The data is read by detecting whether the voltage is between at least two reference potentials higher than the first reference potential or higher than the second reference potential. A reference potential lower than the lower reference potential of the two reference potentials and a potential higher than the higher reference potential of the at least two reference potentials And reading the data by detecting whether the potential is higher than the reference potential or higher than a reference potential lower than the second reference potential. 5. The nonvolatile semiconductor memory according to claim 4, wherein the same sense amplifier is used at the time of normal reading and at the time of verify reading, and the reference potential is a difference between a power supply potential and a ground potential. The gate electrode of a transistor equivalent to the memory cell corresponding to the floating gate of the memory cell is supplied from a connection point of a load transistor connected in series between the transistor and a transistor equivalent to the memory cell. A non-volatile semiconductor memory, wherein different potentials are supplied via a switching unit between a read operation and the verify read operation. 6. An amount of charge stored in the floating gate, comprising a row line, a column line, a drain, a source, a floating gate connected to the column line, and a control gate connected to the row line. A plurality of reference potentials and a potential of the column line at the time of reading data from the memory cell to detect data stored in the memory cell. And a potential setting unit for setting the plurality of reference potentials supplied to the sense amplifier to a predetermined potential after manufacturing the nonvolatile semiconductor memory. . 7. The nonvolatile semiconductor memory according to claim 6, wherein a plurality of sets of said plurality of reference potentials are prepared, and said potential setting means selects a predetermined one of said plurality of sets and sets said sense potential. A non-volatile semiconductor memory, which is controlled so as to be supplied to an amplifier. 8. A memory cell having a row line, a column line, a gate connected to the row line, and a drain connected to the column line, a reference potential and a column line when reading data from the memory cell. And a sense amplifier for detecting data stored in the memory cell by comparing the potential of the memory cell with the potential of the column line so that a potential difference between the reference potential and the potential of the column line becomes large. A non-volatile semiconductor memory, comprising: a reference potential setting unit configured to perform setting. 9. The non-volatile semiconductor memory according to claim 8, wherein said memory cell has a drain, a source, a floating gate, and a control gate connected to said row line, and a charge stored in said floating gate. A non-volatile semiconductor memory storing a plurality of bits of data by varying the amount. 10. An amount of electric charge stored in the floating gate, comprising a row line, a column line, a drain, a source, a floating gate connected to the column line, and a control gate connected to the row line. A plurality of reference potentials and a potential of the column line at the time of reading data from the memory cell to detect data stored in the memory cell. A plurality of sense amplifiers, and a switch circuit for switching a reference potential supplied to the sense amplifier between normal reading and verify reading.