JPH11135774A - High dielectric constant silicate gate dielectric - Google Patents

Abstract

(57) [Problem] To provide a field effect semiconductor device provided with a high dielectric constant silicate gate dielectric. SOLUTION: A semiconductor channel region 24 is formed on a silicon substrate, a metal silicate gate dielectric layer 36 is formed on the substrate, and then a conductive gate 38 is formed. The silicate layer 36 is preferably a material such as hafnium silicate in which the dielectric constant of the gate dielectric is much larger than that of silicon dioxide. However, silicate
The gate dielectric can also be designed with the advantages of silicon dioxide, such as high breakdown, low boundary region density of state, and high stability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a structure of a semiconductor device and a method of manufacturing the same, and more particularly, to a gate dielectric for a field effect device formed on an integrated circuit.

[0002]

2. Description of the Related Art Semiconductor devices such as field effect transistors are widely used in the electronics industry. Such devices are formed in very small sizes,
Thousands and millions of such devices may be formed on a single monocrystalline silicon substrate or "chip", interconnected and performing useful functions in integrated circuits such as microprocessors .

[0003] Although the design and fabrication of transistors is very complex, the general structure and operation of a single transistor is simple. FIG. 1 is a cross-sectional view of a simplified field-effect transistor. In the field effect transistor, a portion near the surface of the substrate 100 serves as a channel 120 in a processing process. The channel 120 is electrically connected to the source 140 and the drain 160 so that a current flows through the channel 120 when a voltage difference exists between the source 140 and the drain 160. When the semiconductor characteristics of the channel 120 change, the gate 19 which is a conductive layer covering the channel 120 is formed.
The resistance is controlled by the voltage applied to zero. Thus, by changing the voltage of the gate 190,
Some current flows through the channel 120. Gate 1
90 and channel 120 are separated by a gate dielectric 180. The gate dielectric is insulative so that little current flows between the gate 190 and the channel 120 during operation (though current flows due to "tunneling" if the dielectric is thin). However, even with the gate dielectric, the gate voltage induces an electric field in the channel 120. This is the origin of the name "field effect transistor".

Generally, the operation and density of integrated circuits are
"Scaling" can be enhanced by reducing the size of individual semiconductor devices on a chip. However, since the field effect semiconductor device outputs an output signal that is directly proportional to the width of the channel, the scaling reduces the output. To compensate for this effect, in the past, the field effect has generally been enhanced by reducing the thickness of the gate dielectric 180 and bringing the gate closer to the channel.

[0005]

As device sizes have become smaller and smaller, the thickness of the gate dielectric has also decreased. Although further device size reductions are possible, the thickness of the gate dielectric has been virtually reduced to near limit with the conventional gate dielectric material silicon dioxide. The further shrinking of the silicon dioxide gate dielectric involves enormous problems. Extremely thin layers result in large current leakage due to direct tunneling through the oxide. Also, since such thin layers are literally formed from several layers of atoms, repeated manufacturing of such layers requires strict manufacturing control. Furthermore, uniform covering has reached its limit. The device parameters vary greatly with or without one single layer of dielectric material. Furthermore, such thin layers provide a weak diffusion barrier for impurities.

[0006] Recognizing the limitations of silicon dioxide, researchers have sought dielectric materials that can be formed thicker than silicon dioxide and still provide the same field effect performance. This performance is expressed as “equivalent oxide film thickness”. A thicker alternative material layer is a material that has the same effect as a much thinner layer of silicon dioxide (commonly referred to as "oxidized" silicon). Most, but not all, promising candidates are metal oxides such as tantalum pentoxide and barium strontium titanate.

Researchers have found that forming a gate dielectric with such a metal oxide is problematic.
At typical metal oxide deposition temperatures, the oxygen environment or oxygen containing precursor required for formation is likely to oxidize the silicon substrate,
An oxide layer is created at the interface between the substrate and the gate dielectric. Having such an oxide layer at the boundary increases the effective oxide thickness and reduces the effectiveness of using an alternative gate dielectric. The presence of an oxide layer in the boundary region is a significant barrier to the performance of alternative dielectric field effect devices.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a semiconductor device structure using a metal silicate dielectric layer, and a method for manufacturing the same. According to the present invention, the metal silicate gate dielectric can be formed with a dielectric constant substantially higher than that of a conventional thermal silicon dioxide or silicon nitride dielectric, so that the metal silicate dielectric layer comprises:
An equivalent field effect can be obtained even when formed substantially thicker than conventional gate dielectrics. The present invention can substantially avoid the disadvantages such as the formation of silicon dioxide in the boundary region and the high density state of the boundary region, which are found in the conventional dielectric.

The present invention can totally eliminate the problems of other alternative dielectrics by using oxide dielectric materials that contain significant amounts of silicon, especially at the silicon / dielectric interface. In one preferred embodiment,
A graded silicate layer is formed, where the silicate layer contains a large amount of SiO ₂ component near the silicon boundary region, while the silicate layer contains a large amount of metal oxide component above the silicate layer. With such a configuration, as a result of obtaining SiO ₂ bonds mainly in the silicon boundary region, the state density in the boundary region is reduced. However, since the silicate layer contains a high atomic number metal, the dielectric constant of the film can be considerably increased. Also, the amorphous silicate gate dielectric provided by the present invention has a high density microstructure and can eliminate many of the problems associated with granular boundaries in polycrystalline dielectrics.

According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising providing a single crystal silicon substrate, forming a metal silicate dielectric layer on the substrate, and forming a conductive gate on the metal silicate dielectric layer. Form. The method can consist of one of several methods for forming a metal silicate dielectric layer. For example, a metal is deposited on a clean Si surface, a silicide layer is formed by annealing, and the silicide layer is oxidized. Alternatively, metal is deposited on the substrate in an oxidizing environment and then annealed in an oxidizing environment. Alternatively, in the same manner as either method, both metal and silicon are deposited on the substrate.

According to another aspect of the present invention, there is provided an integrated circuit on which a field effect device is formed, comprising a single-crystal silicon semiconductor channel, a metal silicate dielectric overlaid on the channel region, and a gate dielectric. Stacked conductive gates. The gate dielectric can be either an amorphous or polycrystalline film. The metal silicate may be, for example, zirconium silicate, cerium silicate, zinc silicate, thorium silicate, bismuth silicate, hafnium silicate, lanthanum silicate, tantalum silicate, or a combination of these materials. Preferably, the metal silicate layer has a graded composition, with the ratio of silicon to metal near the semiconductor channel region being greater than the ratio of silicon to metal near the conductive gate.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION
As described below, it can be typically manufactured using a Si (100) substrate. In the description of these embodiments, as shown in FIG. 2, an epitaxial layer 22 is formed on a substrate 20 and the epitaxial layer 22 is formed.
After the active channel region 24 has been implanted therein.
It is also assumed that a protective or native silicon oxide region 26 (preferably of less than 1 nm of oxide) is overlaid on the channel 24 within the region according to the invention. Such a silicon oxide layer can be applied to a clean substrate at 600-700 ° C. for about 30 seconds at 10 ⁻³ Torr.
It can be formed by heating in an oxygen environment of r or less. The various manufacturing processes leading to this step are known to those skilled in the art, and the present invention can be applied to any of them. In the following example, it is assumed that the channel 24 is formed in the upper layer 22. However, the invention is also applicable to gate dielectrics formed directly on substrate 20 or other relatively pure Si substrates.
In the following description, the layer 20, the layer 22, and the region 24 may be interchanged with each other, unless the context indicates a specific thing.

Particular embodiments for forming a silicate gate dielectric include silicon oxide regions 26 that may be left intact and used to form a silicate layer, or the underlying silicon may be removed to form a silicate layer. It is distinguished by whether it is used to form a layer or is removed and replaced with a chemical reaction inhibiting layer to prevent interaction with the substrate during the metal silicate deposition process. The description that follows relates to preparing the substrate for deposition of the silicate-forming material and applies to the specific embodiments that follow. When removing the silicon oxide region 26, there are two preferred surfaces for the present invention. The region 26 is removed, leaving an empty exposed top surface 28, as shown in FIG. 3, or a hydrogenated surface, as shown in FIG. When the oxide region 26 is removed, if a chemical reaction on the highly reactive Si surface can be prevented, for example, in an ultra-vacuum (less than 10 ⁻⁸ Torr) until a point where oxygen is allowed to be exposed in a specific process. The exposed surface is preferably a non-hydrogen surface rather than a hydrogen surface, as long as it can be prevented by treatment. Otherwise, exposure S
The i-surface should be stopped with a suitable reaction inhibitor such as hydrogen. Hydrogen prevents re-oxidation and can be easily removed at the appropriate point in the process.

The method of oxide removal is not believed to be critical to the present invention. In short, it is only necessary that a clean surface without oxide can be maintained until vapor deposition is performed thereon. One preferred method of removing oxide 26 is to expose it to wet HF. For example, the substrate is immersed in diluted HF for 30 seconds and then washed with deionized water. Thus, the native oxide can be removed and the surface can be stopped with hydrogen. Another preferred method is to apply HF vapor. With this, almost the same result can be obtained. However, since this method can be used in a cluster tool, reoxidation or contamination of the surface can be further prevented. Both methods may use other removal chemicals. HF or NH ₄ F solutions are preferred for use in the final step of surface finishing.

According to some other methods, as shown in FIG. 3, an unstopped surface 28 results. One such method applies to Si flux desorption with a cluster tool. Temperature below 78 at 10 ^-8 Torr
0 ° C., preferably 1.5 Å / sec
By applying a Si flux of 600 seconds
Not only can native oxide be removed, but an atomically smooth stepped surface is obtained, which is advantageous for ultra-thin gate dielectrics. Alternatively, detachment may be performed simply by heating the substrate to a high temperature under vacuum in a hydrogen environment. Where S
It is believed that the i-flux method results in a better surface structure. In any case, unless the substrate is held in an ultra-high vacuum until the overlay deposition is completed, surface 28
Hydrogen termination can be achieved, for example, by exposure to hydrogen atoms generated by a plasma or hot filament in a hydrogen environment.

The surface 28 can be passivated by an ultra-thin layer such as a silicon nitride or silicon oxynitride layer. Strictly speaking, this is not an oxide of silicon. Such a layer acts as a diffusion barrier and provides oxidation resistance to the substrate while forming the overlapping silicate layers. If a silicon oxynitride layer is used, the preferred method of oxynitridation is to expose to NO. Oxynitrides produced by this other method are:
It is not believed to provide sufficient oxidation resistance in the thickness required to complete the gate dielectric structures disclosed herein, and / or higher processing temperatures are not preferred. For example, N ₂ O treatment is NO
The contribution of N is much lower than the processing. In the NH ₃ treatment, it is necessary to prepare a SiO ₂ film in advance, and thus it is difficult to obtain a uniform sub-nanometer oxynitride film using NH ₃ . In addition, in the NH ₃ annealing, there is an unfavorable result that hydrogen enters the film structure.

A typical NO treatment applied to the present invention is:
Proceed as follows. Remove and clean the pad oxide from the substrate. As a final cleaning step, the substrate is immersed in diluted HF for 30 seconds and washed with deionized water. Next, the substrate is placed in the reaction chamber, and the reaction chamber is set to 3 × 10 ⁻⁸ To
After evacuating to rr, the substrate is heated to 500 ° C. to remove hydrogen reaction suppression from the substrate surface. The substrate was heated to 700 ° C., and 4 Torr of NO was introduced into the chamber for 10 seconds.
An oxynitride reaction suppression layer is formed. FIG. 5 shows a passivation layer 30, for example, an oxynitride or nitride passivation layer.

When the substrate is ready to provide a clean Si surface, oxide layer, or protective barrier layer as described above, the metal silicate gate dielectric may be deposited on the substrate by one of several methods. To form Although the particular embodiments of gate dielectric formation described below are readily applicable to a wide range of metal silicate compositions and structures, the preferred metal silicate compositions and structures have several properties described below.

First, the metal silicate is preferably stable next to silicon. The heat to form a suitable silicate is generally more negative than the heat to form silicon oxide. This is to form a more stable gate structure and to prevent the boundary region silicon oxide from being easily formed. Examples of these silicates are Ba, La, Hf, and rare earth elements. SiO
Silicate with a formation heat close to ₂ (eg, Sr, Y,
Zr, Ta) are also useful in the present invention, but the stability of these silicates is generally lower than that of the first group. Table 1 is a candidate for this layer when considering the heat of formation, and silicon dioxide is also included for comparison.

[Table 1]

Second, the metal silicate preferably has a higher dielectric constant than the dielectric constant of silicon dioxide (4 or less) or the dielectric constant of silicon nitride (7 or less). Generally, the dielectric constant of a silicate increases with the number of atoms of the contained metal. Therefore, Ba, La, Hf
Metals having a high atomic weight, such as, and rare earth elements are preferred.

Third, the silicate can be formed as a polycrystalline or amorphous film. Generally, polycrystalline films have better dielectric constants. However, an amorphous film generally has higher breakdown performance, a good diffusion barrier, and a low density of states in a boundary region. Also, in many of the preferred embodiments of forming a silicate dielectric according to the present invention, forming an amorphous film is simpler than forming a polycrystalline film. This is because a uniform stoichiometry is required to form a polycrystalline film. Amorphous silicate films can also be stabilized by including one or more metals in the mixed metal silicate film.

Finally, the present invention utilizes a graded (graded) dielectric composition. In a preferred embodiment, in the portion where the silicate film is formed, the ratio of silicon to metal changes in the depth direction of the film. For example, provide a similar quality of the boundary area and that obtained by the pure SiO ₂ to form a graded silicate film boundary region between the substrate is primarily SiO ₂ (e.g., 2 ^-10 mol% metal oxide) can do. Since the ratio of silicon to metal gradually decreases when viewed from the cross section, the ratio of metal oxide increases as approaching the top of the gate dielectric film.

Embodiment 1 In one embodiment of the present invention, a metal silicate dielectric is formed by depositing a metal on a clean Si surface, and a metal silicide is formed by annealing the metal silicate dielectric. The material layer is oxidized and annealed. In this embodiment, a substrate as shown in FIG. 3 or FIG. 4 is used. As shown in FIG.
If 8 is passivated, the substrate can be easily removed by heating to 500 ° C. in a vacuum or inert environment.

Referring to FIG. 6, a metal layer 32 (eg, zirconium or hafnium) is deposited directly on surface 28 by, for example, sputtering, vapor deposition, chemical vapor deposition (CVD), or plasma CVD. In the sputtering method, the parallelization (c
originated sputter or long-range (long-
Preferably, it is performed by a low energy plasma system such as a sputter. Note that a low deposition rate (for example, about several angstroms per second) is preferable. This is because the entire vapor deposition thickness is small and uniformity is desired. In the case of an 8-inch wafer, the system for performing deposition is based on a base pressure of 10 ⁻⁸ Torr or less.
The working pressure is less than 10 ^-4 Torr, the distance between the sputter gun and the wafer is set at 16 inches (about 40 cm), and the wafer may be rotated to improve uniformity. Argon can be used as a sputter gun. During deposition
The wafer is kept at 400 degrees C.

Instead of the sputtering method, the metal layer 32 may be deposited on a substrate at 500 ° C. from an electron beam source.
At this time, the net deposition rate is from 1/10 angstroms to several angstroms per second. Preferably, the substrate is rotated to improve uniformity. Others
For example, a CVD method using a suitable precursor such as zirconium tetrachloride and hydrogen gas or a plasma CVD method may be used. Also in these methods, a lower deposition rate and a lower temperature (600 ° C. or lower) are preferable. Also, downstream plasma reactors are preferred over reactors where plasma is generated on the substrate.

In FIG. 7, the metal silicide layer 34 is formed by
The substrate 20 provided with the metal layer 32 is placed in an inert environment, a reducing environment,
Alternatively, annealing is performed in a vacuum. The exact value depends on the type of metal used and the desired silicide thickness, but it is generally sufficient to anneal in a vacuum of 700 ° C. for 20 seconds. In most silicide processing, silicon from substrate 20 diffuses into metal layer 32 to form metal silicide layer 34. In this technique, the metal layer 32 may be deposited to be thicker so that a portion of the layer 32 that is not converted to silicide remains during annealing. In this case, the silicide thickness is controlled by the anneal time, and excess metal is etched away after the silicide anneal step.

In FIG. 8, the silicide layer 34 is converted to a silicate layer 36 by oxidation. In this step, control of oxidation is important. This is because if the oxidation is insufficient, the resistance is insufficient.
The capacity of 6 is reduced (since the underlying silicon is oxidized). Various oxygen annealing treatments can be used for this step. For example, low temperature oxygen annealing with or without ultraviolet light, or O with ultraviolet light
Active oxygen anneal such as ₃ , downstream oxygen plasma, N ₂
O or low-temperature oxygen plasma using a DC bias substrate. As an example of this last process, 1 mTorr
Using a downstream 1500W ECR source operating at 13.60MHz or 30.
Helium backside cooling at 80 ° C. may be applied to the substrate by applying 0 kHz. The processing time is experimentally determined so that the resistance and the dielectric constant are within an allowable range.

Generally, by selecting a high temperature anneal of the silicate layer 36, the film will be dense and crystallized after low temperature oxidation. For example, the substrate can be densified by annealing with argon at 750 ° C. for 20 seconds. This annealing can be performed in an inert or reducing environment. In particular, when the metal layer 32 is deposited by a CVD method using halogen, the reducing environment is effective. If a reducing environment is used, an additional low-temperature post-anneal with oxygen can be performed to improve the dielectric properties of the silicate layer 36.

Finally, referring to FIG.
8 is deposited on the silicate gate dielectric 36. The process of depositing gate 38 is well known to those skilled in the art. Gate 38 may be formed, for example, of doped polysilicon, metal, or conductive metal oxide. As a modified example of this embodiment, the step of silicide and the step of oxidation may be combined. The oxidizing environment may be introduced before the silicide is completely formed, or the two steps may be completely repeated. In the latter case, a substrate as shown in FIG. 2 is preferred. This is because the silicon oxide layer 26 is oxygen and silicon for forming the silicate layer 36.

Embodiment 2 In a second embodiment of the present invention, forming a metal silicate gate dielectric comprises depositing a metal on a substrate in an oxidizing environment;
This is performed by annealing. This embodiment utilizes any of the substrates corresponding to FIG. 2, FIG. 3, or FIG. 4, and the metal deposition preferably uses one of the methods described in the first embodiment. . The differences from the first embodiment are as follows.

Referring to FIG. 10, metal oxide layer 40 may be deposited on clean Si by the above-described sputtering method.
However, when the metal is provided to the substrate, the activity of oxygen is controlled to some extent to at least partially oxidize layer 40. For example, by sputtering with argon, the flow rate of oxygen is reduced to about 1/10 of the flow rate of argon, and oxygen or water plus hydrogen is introduced near the substrate. To obtain a metal deposition rate of 0.1 nanometer per second, it is preferable to introduce the oxidizing gas 0-5 seconds after the start of the deposition process.

When the metal oxide layer 40 is formed by vapor deposition, the substance to be oxidized is preferably added near the substrate. To almost completely oxidize the deposited metal is 5 ^-10
Metal deposition is performed at 0.1 nm / sec using oxygen of Torr or less. When using the CVD method, a suitable precursor supplies the required oxygen (eg, zirconium tetrachloride and water).

Referring to FIG. 11, layer 40 is reacted with the substrate to form metal silicate layer 36. this is,
As described in the first embodiment, the annealing is preferably performed by low-temperature oxygen annealing followed by high-temperature annealing. One example of a preferred oxygen anneal is an anneal under O ₃ at 400 ° C. for 60 seconds.

It should be noted that this embodiment can be easily modified to produce a graded silicate layer. One variation of this method is shown in FIG. Here, layer 40 is deposited over silicon oxide layer 26. In such an embodiment, the activity of oxygen during the annealing can be reduced, and the formation of the silicate layer 36
This can be done by "stealing" both oxygen and silicon from layer 26. The gradation of the substrate is layer 26
It can be adjusted by adjusting the relative initial thickness of the layers 40 and 40. In order to supply Si to the layer 40, it is preferable to inject vigorous ions from remote plasma and apply a DC bias to the substrate to adjust the penetration depth. For example, Si may be implanted into the layer 40 using silane.

Embodiment 3 In a third embodiment of the present invention, the formation of a metal silicate gate dielectric is performed by depositing both metal and silicon on a substrate in an oxidizing environment, followed by annealing. Do. In this embodiment, the preparation of the substrate can be selected from those shown in FIGS. Since this method does not rely on silicon from the substrate as a component of the silicate film, a surface that limits oxidation of the substrate, such as the diffusion barrier surface of FIG. 5, is preferred. One of the methods described in the first embodiment can be used for depositing metal and silicon. However, there are the following differences.

Referring to FIG. 13, the metal oxide and silicon layer 42 is deposited on the clean Si surface by sputtering as described in the deposition of metal oxide 40 in the second embodiment. Deposition of both metal and silicon is accomplished by replacing the metal target with a suitable silicide target. The disadvantage of this method is that it is difficult to deposit a graded layer from a single composition target.

If the formation of the metal oxide and silicon layer 42 is performed by evaporation, a method similar to that of the second embodiment can be selected. In this case, it is preferable to use metal and silicon from different electron beam sources and adjust the ratio of silicon to metal during the deposition process.

When using the CVD method, a suitable precursor will provide the required oxygen. The use of a combination of precursors, such as a combination of silane, zirconium tetrachloride and oxygen, can produce a uniform stoichiometric layer, but it is difficult to obtain a graded composition layer. To obtain a graded layer, it is preferable to use a combination of silicon tetrachloride, zirconium tetrachloride and water as a CVD precursor.

In order to form a high-performance silicate layer using this process, generally, both low-temperature oxygen annealing and high-temperature annealing as described in the first and second embodiments are required. It is. FIG. 14 and FIG.
Shown is a layer 42 deposited on the silicon oxide layer 26 and a layer 42 deposited on the diffusion barrier layer 30 (eg, a silicon oxynitride layer). As described above, the diffusion barrier layer 30
If so, more aggressive oxygen annealing can be selected.

Embodiment 4 In a fourth embodiment of the present invention, forming a metal silicate dielectric comprises depositing both metal and silicon on a substrate,
This is done by annealing it. The silicate formed by this embodiment is shown in FIGS.
Alternatively, it can be formed on a substrate prepared based on FIG. To put it simply, this embodiment is
The silicide is directly deposited by combining the metal deposition / silicide technique of the first embodiment and the metal / silicon deposition source of the third embodiment.

Referring to FIG. 16, to deposit metal silicide layer 44 on a clean Si surface, a sputtering method is used as described in the deposition of metal layer 34 in the first embodiment. Metal and silicon are deposited by replacing the metal target with a suitable silicide target. The disadvantage of this method is that it is difficult to form a graded layer from a single composition target.

The formation of the metal silicide layer 44 is performed by evaporation (evaporation).
(ratio) method, a method similar to that of the first embodiment can be selected. In this case, it is preferable that metal and silicon electron beam sources are separately prepared, and the ratio of silicon to metal is changed during the deposition process.

When using the CVD method, a suitable precursor will provide the required oxygen. The use of a combination of precursors, such as a combination of silane and zirconium tetrachloride, can produce a uniform stoichiometric layer, but it is difficult to obtain a graded composition layer.
To obtain a graded layer, it is preferable to use a combination of silicon tetrachloride, zirconium tetrachloride and hydrogen as a CVD precursor. To prevent chlorine from entering the film, the amount of hydrogen must be increased.

To form a high performance silicate layer 46 (FIG. 17) from layer 44 using this process, generally,
Both low-temperature oxygen anneal and high-temperature anneal, as described in the first embodiment in particular, are necessary. As described above, with the diffusion barrier layer 30, more aggressive oxygen annealing can be selected.

Embodiment 5 In a fifth embodiment of the present invention, a metal silicate is formed by depositing both metal oxide and silicon on a substrate.
Subsequently, oxygen annealing is performed. This method may work better than the silicide method described above. This is because the deposited layer is not in a highly reduced (ie, oxygen deficient) state, but at least as good as an intermediate method using silicide.

The silicate formed according to this embodiment can be formed on a substrate prepared based on FIG. 2, FIG. 3, FIG. 4, or FIG.

Referring to FIG. 19, to deposit a partially reduced metal silicate layer 50 on a clean Si surface,
A metal oxide such as ZrO ₂ and a Si element are simultaneously sputtered (co-sputtering) to form oxygen-deficient zirconium silicate. Alternatively, Hf
A combination of O ₂ and Si, may be formed anoxic hafnium silicate. Although this zirconium is partially reduced, it can be completely oxidized to silicate more easily than to completely oxidize zirconium silicide.

As a system for performing vapor deposition on an 8-inch wafer, a base pressure of 10 ⁻⁸ Torr or less and a working pressure of
^{At -3} Torr or less, the distance between the sputter gun and the wafer is set at 16 inches (about 40 cm), and the wafer is preferably rotated for more uniformity. Argon or a mixture of argon and oxygen (10-50% oxygen or less) can be used as the sputter gas. During the deposition, the wafer is kept at a temperature of 400-500C. RF power can be as low as about 50
Set to -100 watts to prevent grain and defects. S
The power setting of i is usually not critical. ZrO ₂
It may be the same as the setting.

As an alternative to the sputtering method, a zirconium oxide electron beam source and a silicon
A partially reduced metal silicate layer 50 may be formed by vapor deposition on a substrate at 0 to 600 ° C. On this occasion,
The deposition rate is set to about 1/10 angstrom to several angstrom per second. The substrate may be rotated for uniformity.

Next, referring to FIG. 20, a partially reduced metal silicate 50 is converted into a silicate layer 52 by oxidation.
Changes to In this step, control of oxidation is important. If the oxidation is insufficient, sufficient resistance cannot be obtained,
Also, if oxidized too much, the capacity of layer 52 will decrease (because the underlying silicon will oxidize). By post-annealing at about 400-550 ° C. for about 30 minutes or less under oxygen,
Usually, the capacitance can be increased while keeping the leakage current low. Higher temperatures or longer anneals tend to reduce capacity. There are various oxygen annealing methods in this step. For example, a low temperature oxygen anneal with or without ultraviolet light, or an active oxygen anneal such as O ₃ with ultraviolet light, a downstream oxygen plasma, N ₂ O, or a low temperature oxygen plasma using a DC biased substrate. As an approximate example of this last process, a 1500 W downstream operating at 1 mTorr
Use an ECR source, connect it to the board at DC 60V or less,
Applying 3.56 MHz or 300 kHz,
Helium backside cooling at 80 ° C. may be applied to the substrate. The processing time is experimentally determined so that the resistance and the dielectric constant are within an allowable range.

In general, by selecting a high temperature anneal of the silicate layer 52, the film will be dense and crystallized after low temperature oxidation. For example, the substrate can be densified by annealing at 750 ° C. for 20 seconds under argon. This annealing can be performed in an inert or reducing environment. In particular, the reducing environment is effective when the partially reduced metal silicate layer 50 is deposited by a CVD method using halogen. If a reducing environment is used, to improve the dielectric properties of the silicate layer 52,
An additional low temperature post-anneal under oxygen can be performed. For physical vapor deposited (PVD) dielectrics, an inert or oxidizing environment is generally preferred. As described in the above embodiment, if the diffusion barrier layer 30 is provided, more aggressive oxygen annealing can be selected. By independently introducing a metal oxide such as ZrO ₂ and silicon, the metal-to-silicon stepped cross section of the silicate dielectric can be directly controlled.

From our findings, it is not always desirable for the gate dielectric to form strictly stoichiometric ZrSiO ₄ , but rather a slight ZrSiO _4.
In some cases, it is preferable to include abundantly or to form a Zr-deficient film. The stoichiometric ZrSiO ₄ facilitates crystallization, but the non-stoichiometric film is more stable in an amorphous state. Further, by controlling the Zr content, it is possible to control the dielectric constant and boundary region characteristics similar to SiO ₂ . Oxygen-rich silicates have low leakage current and good boundary region characteristics. Because Si
This is because a boundary region and a film similar to O ₂ improve both.

As a variant of the invention, the oxygen content of the partially reduced metal silicate layer 50 can be changed slightly. Sputtering or evaporation (evapora)
The oxygen content can be increased slightly by using SiO ₂ instead of Si in the method. In this SiO ₂ sputtering method, SiO is formed and provides more oxygen than ZrO ₂ or Si, but not so much as to form stoichiometric ZrSiO ₄ .

A slightly reduced metal silicate layer is often desired. However, sometimes, first, but not completely, the more reduced metal silicate layer 50 may be preferred. In such a case, Zr may be used instead of ZrO ₂ and SiO ₂ may be used instead of Si. The resulting SiO provides a silicate with a higher oxygen content than the silicide method described above, but less than the ZrO ₂ / Si method according to the fifth embodiment.

Embodiment 6 In addition to the embodiments described above, the composition of the silicate layer can be changed by repeating some of the deposition steps. 17 and 18, for example, the layer 46
Only becomes an intermediate layer. For example, using the electron beam evaporation method described in the fourth embodiment, silicon,
One or more single layers of metal, or a combination thereof, are deposited and a short anneal is performed in an oxidizing environment to form the intermediate layer 46. Next, in a similar process, a second intermediate layer having the same or different composition is deposited. Using this method, the silicon oxide and metal oxide layers will be interleaved before the final anneal. Or,
The graded composition may be deposited directly.

The present invention is not limited to the above embodiment. Although a particular substrate and a particular type of device have been discussed herein for simplicity, the present invention applies generally to devices that change the semiconductor properties of the active region using the field effect of the overlying conductive region. Can be. The above described steps can produce silicate gate dielectrics in other combinations as well, which are also within the scope of the present invention.

This application claims priority from the following US provisional application: That is, US Provisional Application No. 60 / 053,661,
Filing date July 24, 1997, No. 60 / 053,616
No., filing date July 24, 1997, and No. 60/05
3,617, filed July 24, 1997.

The present invention relates to the presently filed TBD (TI-2
5859) and TBD No. (TI-26146), which are referenced above.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of an integrated circuit field effect transistor as a typical conventional example.

FIG. 2 shows a cross section of a semiconductor device according to the invention, representing a surface suitable for the deposition of a silicate gate dielectric.

FIG. 3 shows a cross section of a semiconductor device according to the invention, representing a surface suitable for the deposition of a silicate gate dielectric.

FIG. 4 shows a cross section of a semiconductor device according to the invention, representing a surface suitable for the deposition of a silicate gate dielectric.

FIG. 5 is a cross-section of a semiconductor device according to the present invention, illustrating a surface suitable for depositing a silicate gate dielectric.

FIG. 6 is a cross-sectional view illustrating a process of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 7 is a sectional view illustrating a semiconductor device manufacturing process according to one embodiment of the present invention.

FIG. 8 is a sectional view illustrating a semiconductor device manufacturing process according to one embodiment of the present invention.

FIG. 9 is a sectional view illustrating a semiconductor device manufacturing process according to one embodiment of the present invention.

FIG. 10 is a sectional view illustrating a semiconductor device manufacturing process according to a second embodiment of the present invention.

FIG. 11 is a sectional view illustrating a semiconductor device manufacturing process according to a second embodiment of the present invention.

FIG. 12 is a sectional view illustrating a semiconductor device manufacturing process according to a second embodiment of the present invention.

FIG. 13 is a sectional view illustrating a semiconductor device manufacturing process according to a third embodiment of the present invention.

FIG. 14 is a sectional view illustrating a semiconductor device manufacturing process according to a third embodiment of the present invention.

FIG. 15 is a sectional view illustrating a semiconductor device manufacturing process according to a third embodiment of the present invention.

FIG. 16 is a sectional view illustrating a semiconductor device manufacturing process according to a fourth embodiment of the present invention.

FIG. 17 is a sectional view illustrating a semiconductor device manufacturing process according to a fourth embodiment of the present invention.

FIG. 18 is a sectional view illustrating a semiconductor device manufacturing process according to a fourth embodiment of the present invention.

FIG. 19 is a sectional view illustrating a manufacturing process of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 20 is a sectional view illustrating a manufacturing process of a semiconductor device according to a fifth embodiment of the present invention.

[Explanation of symbols]

 20, 100 Substrate 24, 120 Channel 140 Source 160 Drain 180 Gate dielectric 190 Gate 22 Epitaxial layer 26 Silicon oxide region 28 Surface 30 Diffusion barrier layer 32 Metal layer 34 Silicide layer 36 Silicate gate dielectric 40 Metal oxide layer 42 Silicon Layer 44 Metal silicide layer 46, 52 Silicate layer 50 Partially reduced metal silicate layer

Continued on the front page (72) Robert M. Inventor. Wallace Park Bend Drive, Richardson, Texas, United States 428 (72) Inventor Glendi. Wilk United States Dallas, Texas, Markville Drive 9050 Number 821

Claims (10)

[Claims] 1. A method of fabricating a field effect device on an integrated circuit, comprising: providing a single crystal silicon substrate; forming a metal silicate dielectric layer on the substrate; Forming a conductive gate. 2. The step of forming a metal silicate dielectric layer on the substrate includes exposing clean Si on the substrate, depositing a first metal on the Si surface, and annealing the substrate in an inert environment. Forming a first metal silicide layer on the substrate, and oxidizing the first metal silicide layer to form a metal silicate dielectric layer. 2. The method according to 1. 3. The step of forming a metal silicate dielectric layer comprises: forming at least a partially oxidized layer on a substrate by depositing a first metal and silicon on the substrate in an oxidizing environment; 2. The method of claim 1 comprising annealing in a oxidizing environment. 4. The method of claim 3, wherein the step of depositing the first metal and silicon comprises sputtering a substance onto a substrate from a target comprising the first metal and silicon. . 5. The method of claim 3, wherein depositing the first metal and silicon comprises depositing the first metal and silicon from a common source. 6. The method of claim 3, wherein the step of depositing the first metal and silicon comprises simultaneously depositing the first metal and silicon from separate sources. 7. The step of forming a metal silicate dielectric layer includes exposing clean Si on a substrate, depositing partially reduced metal silicate on a Si surface, and removing the partially reduced metal silicate in an oxygen environment. 2. The method of claim 1, comprising forming a metal silicate dielectric layer by annealing the metal silicate substrate. 8. The method of claim 7, wherein the step of depositing the partially reduced metal silicate on the Si surface comprises simultaneously physically depositing a metal oxide and silicon. Method. 9. The step of depositing a partially reduced metal silicate on the Si surface comprises: zirconium oxide;
The method of claim 7, comprising simultaneously physical depositing an oxide and silicon selected from the group consisting of hafnium oxide and mixtures thereof. 10. An integrated circuit in which a field effect device has been fabricated, said field effect device comprising: a single crystal silicon semiconductor channel region; and a metal silicate gate dielectric overlaid on said channel region. Metal silicates are zirconium silicate, barium silicate, cerium silicate, zinc silicate, thorium silicate, bismuth silicate, hafnium silicate, tantalum silicate,
And a conductive gate covering the gate dielectric.