JPH11145304A - Semiconductor device, its manufacture and differential amplifier device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce input offset voltage and to highly precisely detect matching of a micro potential difference, by setting sum of first and second area thickness to be smaller than the thickness of a source or drain area, and setting an impurity concentration of the second area to be higher than that of the first area. SOLUTION: When appropriate voltage is applied to a source drain and a gate terminal, a depletion layer is formed in a substrate of an inversion layer 7 formed on a surface of a channel of a semiconductor area, which is immediately below a gate electrode 3 and whose both sides are sandwiched by source drain diffused layers 4 and 5. Since the concentration in the first region near a substrate surface is low in the range of WDEP from the surface by depth in the depletion layer, threshold fluctuations are reduced. But, the concentration in the second region part is high in the range of WDEP, the extension of the depletion layer in a lateral direction from the source drain is suppressed and short channel effect is improved. Consequently, impurity concentration is distributed to be low on a surface side and high on an inner side and short channel effect is not deteriorated, a threshold is not changed, and only the threshold fluctuations are reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having a MISFET with small variations in characteristics, a method of manufacturing the same, and a differential amplifier circuit using the same.

[0002]

2. Description of the Related Art As an effective circuit for amplifying a minute voltage, a differential amplifier circuit in which two identical transistors are combined is known, and is widely used in semiconductor integrated circuits.

In a differential amplifier circuit using two MISFETs, that is, two transistors T1 and T2, a transistor T
1 and T2 are called a "differential pair". The differential amplifier circuit inputs the differential signals Vin1 and Vin2, and outputs the differential output signal Vout1.
And Vout2.

In this example, the difference between the input signals (Vin1-V
The larger (in2) is, the larger the difference (Vout1-Vout2) between the output signals is. Also, the sign of the difference between the input signals and the sign of the difference between the output signals match.

One of the important uses of the differential amplifier circuit is to determine whether the difference between the input signals (Vin1−Vin2) is positive or negative.
For that purpose, it is necessary that the characteristics of the two transistors T1 and T2 are uniform. If there is a difference between the threshold voltages of the transistors T1 and T2 and the threshold value of the transistor T1 is higher than the threshold value of the transistor T2 by dV _TH , then dV _TH > Vi
In the range of n1−Vin2> 0, Vout1−Vout2 <0 despite Vin1−Vin2> 0, and an error occurs in the sign determination.

In other words, an input offset voltage having a threshold voltage difference dV _TH is generated. Therefore, in order to realize a highly accurate code determination, it is necessary to suppress irregularities in characteristics such as the threshold voltage difference dV _TH as much as possible. Such an error is caused by variation in MISFET characteristics.

[0007]

As the miniaturization of integrated circuits progresses, the power supply voltage decreases, and there is a need to accurately detect the positive or negative of a smaller potential difference. For this purpose, it is necessary to reduce the variation in the characteristics between the MISFETs constituting the differential pair, especially the variation in the threshold value _VTH .

[0008] Among the variations of the threshold value _VTH , nonuniformity caused by a locational factor in a manufacturing process does not cause much problem in an integrated differential amplifier. This is because the influence can be suppressed by arranging the differential pair MISFETs close to each other.

However, in addition to the above, there is a variation in the threshold value VTH caused by the micro fluctuation of the impurity introduced into the region serving as the channel of the transistor in the substrate. That is, the number of impurities present in the channel region of the fine MISFET (strictly speaking, the depletion layer region below the channel) is, for example, only 300 on average assuming a MISFET having a width and length of 0.1 μm. The arrangement of each impurity is random because it is introduced by ion implantation or diffusion, and only the average concentration is determined. Therefore, the number of impurities in each MOSFET is 320 or 2
It could be 80.

Such a variation (unevenness) of the threshold value _VTH due to the randomness of the arrangement of the impurities cannot be removed no matter how close the MISFET is, since it is a completely random phenomenon. There is a property that it becomes more remarkable as the MISFET is miniaturized.

[0011] Implementation of this the way advance the miniaturization, while irregular threshold voltage V _TH by the fluctuation of the impurity distribution is increased, since the voltage becomes smaller handling, differential amplifier having a sufficient performance There is a problem that becomes difficult.

The present invention has been made in view of the above circumstances. Therefore, an object of the present invention is to provide a semiconductor integrated circuit including transistors having uniform characteristics, a method of manufacturing the same, and a differential amplifier using the same.

[0013] Another object of the present invention is to provide a semiconductor integrated circuit in which irregularities in characteristics due to fluctuations in impurity distribution are prevented.
An object of the present invention is to provide a manufacturing method thereof and a differential amplifier using the same.

Still another object of the present invention is to provide a differential amplifier capable of suppressing an input offset voltage and detecting a voltage with high accuracy in an integrated circuit using a MISFET.

[0015]

In order to achieve the first aspect of the present invention, a semiconductor device according to the present invention comprises a plurality of MISFs.
Including ET. Each of the plurality of MISFETs has a gate electrode formed on a substrate, a source region and a drain region formed on the surface of the substrate, and at least a region under the gate electrode of the substrate has a first region. Is provided,
A second region is provided inside the substrate from the first region. The sum of the thickness of the first region and the thickness of the second region is smaller than the thickness of the source region or the drain region, and the second region has a higher impurity concentration than the first region.

A plurality of MISFETs;
Each of the ISFETs has a gate electrode formed on a substrate, a source region and a drain region formed on the surface of the substrate, and includes a depletion layer formed when a threshold voltage is applied to the gate electrode. , A first from the surface of the substrate
And a second region following the first region in the substrate than the first region, wherein the second region has a higher impurity concentration than the first region.

The sum of the thickness of the first region and the thickness of the second region is smaller than the thickness of the source region or the drain region, and the first region is of the same conductivity type or intrinsic as the substrate. The second region is of the same conductivity type as the substrate.

A method of manufacturing a semiconductor device according to the present invention includes a first step of forming a first region and a second region in a surface region of the semiconductor substrate between element isolation insulating films formed on the semiconductor substrate; Forming a MISFET having a source region, a drain region, and a gate electrode in the surface region of the semiconductor substrate. Here, the second region has a higher impurity concentration than the first region.

The first step includes the step of implanting impurity ions into the surface of the semiconductor substrate to form the second region, and the step of forming a layer having a lower impurity concentration than the second region on the surface of the semiconductor substrate. The method may include forming a first region and forming the element isolation insulating film.

Alternatively, the first step includes a step of forming the element isolation insulating film;

Implanting impurity ions into the surface of the semiconductor substrate between the device isolation insulating films to form the second region; forming a second region between the device isolation insulating films on the surface of the semiconductor substrate from the second region; The layer having a low impurity concentration is
Forming the region as a region.

The semiconductor device of the present invention has first and second MISFETs which are designed to be the same, and a voltage applied to the gate electrode of the first MISFET and a voltage applied to the gate electrode of the second MISFET. In the amplifying device that amplifies and outputs a difference from the applied voltage, the depth direction distribution of the substrate impurity concentration in the channel region of the MISFET gives the same threshold value and the impurity concentration is uniform in the depth direction. It is characterized in that the effective substrate concentration is set to be lower than in the case.

Further, the semiconductor device is designed to have the same design.
An amplification device having 1 and a second MISFET, and amplifying and outputting a difference between a voltage applied to a gate electrode of the first MISFET and a voltage applied to a gate electrode of the second MISFET, The depth direction distribution of the substrate impurity concentration within the depletion layer formed immediately below the channel inversion layer of the MISFET,
The first region from the substrate surface is smaller than the second region inside the first region.

Further, the semiconductor device is the same as the first designed.
An amplification device having 1 and a second MISFET, and amplifying and outputting a difference between a voltage applied to a gate electrode of the first MISFET and a voltage applied to a gate electrode of the second MISFET, The channel region of the MISFET has an epitaxial growth layer, and the epitaxial growth layer has an impurity concentration lower than that of the semiconductor region immediately below the epitaxial growth layer.

As described above, in the present invention, the depth distribution of the impurity in the differential pair MISFET which reduces the variation in the threshold value due to the micro fluctuation of the impurity is adopted. More specifically, in the region where the channel of the MISFET forming the differential pair is formed, the impurity concentration in the vicinity of the substrate surface is suppressed lower than that in the deeper portion.

A first region from the surface of the substrate is provided in a depletion layer during operation of the MISFET, and a second region is provided inward of the substrate from the first region. A semiconductor device in which the highest impurity concentration is at least 100 times the highest impurity concentration in the first region.

A semiconductor device according to the present invention comprises a gate electrode and a 10 ¹⁸ at layer provided on an inversion layer in a substrate below the gate electrode.
An intermediate layer between the gate electrode and the first semiconductor region, and a first semiconductor region of oms / cm ^-3 or more, includes a gate oxide film and a second semiconductor region. Based on the capacitance, the thickness of the first semiconductor region and the second semiconductor region in the depth direction of the substrate, and the impurity concentration,
The threshold distribution of the MISFET having the gate electrode is controlled.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor integrated circuit according to the present invention will be described in detail with reference to the accompanying drawings.

First, the concept of the present invention will be described.

The present invention is based on the knowledge that the concentration distribution of a substrate impurity in the channel region in the depth direction affects the variation in the threshold value of the transistor due to the micro fluctuation of the impurity.

The channel area is a MI area schematically shown in FIG.
In the SFET, a region immediately below the gate electrode 3 and a semiconductor region sandwiched between the source / drain diffusion layers 4 and 5 on both sides. When an appropriate voltage is applied to the source, drain and gate terminals, an inversion layer 7 is formed on the surface of the channel region. A depletion layer is formed inside the substrate of the inversion layer 7. According to theoretical and experimental studies, the variation in the threshold value of the transistor due to the fluctuation of the impurity distribution is as follows.
Have been found to be described by an expression.

[0032]

(Equation 1)

[0033]

(Equation 2)

Here, ΔV _TH : standard deviation of threshold, F (N
_EFF ): increasing function of N _EFF approximated by the third side of equation (1),
q: elementary charge, C _OX : capacitance per unit area of the gate insulating film, W _DEP : depth of a depletion layer below the inversion layer when the MISFET is inverted, K: normal line in the vertical direction in FIG. 2 in a plane to the area of the channel side is in units of square _{W DEP, N SUB (x)} : the depth of the function of the impurity concentration in the channel region, x: position in the depth direction of the substrate surface as the origin Coordinates.

This is a variation for one MISFET. The standard deviation of the threshold difference between the differential pair MISFETs is 2 ^1/2 V _TH according to the law of statistics because the variation due to impurity fluctuation has no spatial correlation. In particular, considering the case where the substrate concentration is constant in the depth direction

[0036]

(Equation 3)

From the equation (1), the standard deviation of the threshold variation increases as the substrate concentration increases. _NEFF gives an effective substrate concentration with respect to threshold variation, and is hereinafter referred to as an effective substrate concentration. _NEFF is an index of threshold variation, and the larger this value is, the larger the threshold variation increases. From equation (1), the threshold variation increases the larger the N _EFF. Further, the smaller the element size (ie, K), the greater the variation. Note that W _DEP in Expressions (1) and (2) is determined by simultaneously combining the following two known expressions.

[0038]

(Equation 4)

[0039]

(Equation 5)

Here, E (x): electric field in the depth direction in the semiconductor, ε _S : dielectric constant of the semiconductor substrate, ψ _S : bending of the band at the time of inversion (about 1 V in the case of silicon), V _BS : This is the substrate potential (substrate bias) with respect to the source.

When the drain voltage is applied, the width of the depletion layer in the channel region is wider on the drain side than on the source side, as shown in FIG. 1, and also depends on the substrate bias.

In the present invention, the width W _DEP of the depletion layer is defined as a value when the drain and source voltages are the same and the substrate bias is set to a predetermined design value threshold voltage. At this time, the width of the depletion layer in the channel region becomes constant along the channel. The width W of the depletion layer defined in this way
_DEP is substantially equal to the width near the source shown in FIG. 2 when the drain voltage is applied.

The threshold voltage V _TH is calculated in combination with the equations (4) and (5).

[0044]

(Equation 6)

Is determined. Here, V _FB is a flat band voltage.

Assuming that the average number of impurities in a certain minute region is n, the number of impurities in the region follows a binomial distribution, and the standard deviation is given by the square root of n.
In addition, the inventors have found that the threshold shift caused by a certain number of impurity fluctuations depends on the distance of the minute region from the substrate surface.

The farther away from the substrate surface (the larger x)
The influence of the fluctuation of the number of impurities on the threshold becomes small, and x = W
_No effect at _DEP . Equations (1) and (2) represent these phenomena quantitatively. From Equations (1) and (2), generally, the smaller the impurity concentration, the smaller the variation. Also,
Reducing impurities near the substrate surface has a greater effect of reducing variations than reducing impurities in deep portions.

The structural features of the MISFET of the present invention are as follows:
FIG. 1 shows the distribution of impurities in the depth direction along the alternate long and short dash line.

The present invention is an application of this phenomenon.
The effect of the variation reduction by changing the impurity concentration and the depth distribution can be quantitatively described by how small the effective substrate concentration is.

FIG. 2 is a view for explaining an example of the impurity distribution according to the present invention. In FIG. 2, the solid curve schematically shows the impurity distribution in the depth direction along the alternate long and short dash line in FIG. 1 according to the present invention.

It is assumed that a desired threshold value is realized by a uniform impurity distribution shown by a dashed line in FIG. At this time, assuming that the gate insulating film thickness and the material of the gate are the same, a desired threshold value can be obtained even with an uneven distribution as indicated by a solid line.

Here, W _DEP is the width of the depletion layer defined above, and in the range from the surface to the depth W _DEP , in the first region near the substrate surface, the distribution of the solid line falls below the one-dot chain line.
Conversely, in the portion inside the substrate (the second region), which is deeper than the first region, the distribution is such that the solid line exceeds the one-dot chain line. As a result of the lower concentration in the first region near the surface, the variation in threshold value is smaller than that in the case of the dashed line distribution.

However, since the density is high in the second region portion within the range of the depth W _DEP , the threshold value is set to be the same as the case of the broken line. Furthermore, because the concentration in this deep part is high,
The spread of the depletion layer in the lateral direction from the source / drain is suppressed, and the short channel effect is expected to be improved as compared with the case of the dashed line.

As described above, in the range of the depletion layer width W _DEP on the substrate surface, the impurity concentration is low on the surface side and high on the inside side, so that the short channel effect is not deteriorated and the threshold value is changed. Instead, only the variation in the threshold value can be reduced.

FIG. 3 illustrates another example of impurity distribution according to the present invention. In FIG. 2, the concentration distribution is close to a step-like distribution which will be described later, and a low concentration layer having a substantially constant concentration exists near the substrate surface. However, the same effect can be obtained even with a distribution as shown in FIG. 3 in which the impurity concentration decreases exponentially as it approaches the substrate.

Such a distribution is easier when an ion implantation method is used for impurity introduction. On the surface of the substrate, the distribution of the solid line is below the dash-dot line, and in the deep part, the distribution of the solid line exceeds the dash-dot line.
Is the same as The distribution as shown in FIG. 3 can be easily realized by implanting impurities once.

Strictly speaking, the essence of the present invention is such that the depth distribution of the substrate impurity concentration in the channel region in the depth direction gives the same threshold value and the effective substrate concentration is lower than that in the case where the impurity concentration is uniform in the depth direction. Is set to be small.

Here, the "identical threshold value" is a predetermined value required in design and is determined in advance from requirements such as circuit operation. A typical value is 0.5V. Low effective substrate concentration reduces variation.

The above example is a typical example satisfying this condition. However, it is complicated to calculate the effective substrate concentration one by one, but the depth direction distribution of the substrate impurity concentration in the range of the depletion layer formed immediately below the channel inversion layer (from x = 0 to W _DEP ) is If a distribution that minimizes is used, the condition is almost automatically satisfied.

It should be noted that whether the impurity distribution on the substrate surface is substantially constant or changes exponentially, whether the maximum concentration is x <W _DEP when focusing on the range from x = 0 to W _DEP or x = Details such as whether they are W _DEPs are not important from the perspective of reducing variability. Further, since the effective substrate concentration is determined by the impurity concentration distribution at W _DEP from x = 0, the impurity distribution at a portion deeper than W _DEP does not affect the variation.

Next, how the above effects can be obtained by lowering the impurity concentration on the substrate surface will be described in more detail. In order to simplify the discussion, the calculation is performed assuming the step distribution shown in FIG. 4 as the impurity distribution. That is,
The distribution in which the impurity concentration is small at the substrate surface and large at a deep position is approximated by a step-like distribution in which N (x) = N1 and x> d and N (x) = N2 from x = 0 to d.

In FIG. 5, assuming the distribution of FIG.
The relationship between the threshold voltage calculated by (4), (5) and (6) and the effective substrate concentration is shown. However, the concentration N1 in the first region near the surface and the concentration N2 in the second region inside the substrate are fixed, and the depth d of the boundary where the concentration changes is changed as a parameter, and the gate material is n-type polysilicon. Is assumed. N1 = 1 × 10 ¹⁶ cm ⁻² , gate oxide film thickness (t _OX ) is 3.5 nm, and concentration N2 is 1 × 10 ¹⁷ cm
³ , 1 × 10 ¹⁸ cm ⁻² and 1 × 10 ¹⁹ cm ⁻² . Three solid curves in the figure correspond to the case where the density N2 is the above-described density in order from the left.

Such a curve for a certain set of concentrations N1 and N2 shows the locus of the combination of the threshold value and the effective substrate concentration value that can be realized by changing d. The dashed line is
This is a result when d = 0 (that is, constant at N (x) = N2) and N2 is continuously changed (corresponding to a uniform distribution). In this case, since the effective substrate concentration matches the actual substrate concentration, the vertical axis is equal to N2, and the threshold value is almost proportional to the square root of N2.

At the upper end of each solid line, that is, at the intersection with the broken line,
Since d = 0, and starting from this point and increasing d (increase the thickness of the low concentration layer), both the threshold value and the effective substrate concentration decrease along the solid line. However, when W _DEP <d, the effective substrate concentration becomes constant ( _NEFF = N1), and the curve becomes a horizontal straight line. Although N1 is ideally zero, it is difficult to realize the ideal state in reality, so a more realistic 1 × 10 ¹⁶ cm ⁻² was assumed.

The effect of the present invention will be described with reference to FIG.
For the assumed gate material and gate oxide thickness,
At a uniform substrate concentration of 1 × 10 ¹⁸ cm ⁻² , a threshold of 0.5 V is obtained. Point A in FIG. 5 corresponds to this state.

Since the substrate concentration is uniform, the effective substrate concentration is equal to the actual substrate concentration of 1 × 10 ¹⁸ cm ⁻² . Consider a method of lowering the effective substrate concentration by changing only the impurity depth distribution while obtaining the same threshold voltage. For that purpose, for example, the state at the point B may be realized.

Since point B is located on the third curve from the left, it can be seen from FIG. 5 that this can be realized by setting N2 = 1 × 10 ¹⁹ cm ⁻² and setting d to an appropriate value. FIG. 5 d
Although the specific value of can not be read directly, it is determined from the calculation results of equations (2), (4), (5), and (6) performed to draw FIG. 5 that d = 17 nm is appropriate. Is done.

If N2 is not limited to 1 × 10 ¹⁹ cm ⁻² but is a value larger than 1 × 10 ¹⁸ cm ⁻² , it is possible to determine d which realizes a state where the threshold values are equal and only the effective substrate concentration is reduced. It is.

The point B realized by such a design procedure
In such a state, "the effective substrate concentration is lower than that of a device having the same structure except for the distribution of the substrate impurity concentration and having the same threshold value and having a uniform substrate concentration" (in other words, the point B Is located below the broken line). Since the effective substrate concentration is low, the variation in threshold value is suppressed.

Although the above description assumes the simple impurity distribution shown in FIG. 4, this does not limit the scope of the present invention. However, FIG. 5 is a good approximation of the realistic distribution as shown in FIG. 2, and FIG. 5 can be sufficiently applied to an actual design. formula
Since (2), (4), (5), and (6) can be applied to any impurity distribution, such an approximation is not used, and a general impurity distribution as shown in FIGS. 2 and 3 is assumed. The design can be made by individually calculating the effective impurity concentration.

The impurity distribution for reducing the effective substrate concentration as shown in FIGS. 2 and 3 can be realized by ion implantation. That is, in order to lower the impurity concentration on the substrate surface, in the ion implantation for introducing the impurities, the implantation energy may be adjusted so that the peak position of the concentration becomes a sufficiently deep position.

A distribution having one peak as shown in FIG. 3 can be realized by one ion implantation in which the concentration peak position is adjusted. As shown in FIG. 2, in order to obtain a uniform distribution in a deep portion, it can be realized by sequentially performing ion implantation with different peak depths a plurality of times.

As a method for more precisely controlling the impurity distribution in the depth method, epitaxial growth of a semiconductor can be used. In ion implantation, when the implantation energy is increased, the width of the bottom of the impurity distribution increases, and the depth distribution of the impurity cannot always be set freely.

On the other hand, when the epitaxial growth technique is used, the impurity concentration of the grown layer can be controlled by the amount of impurities mixed into the source gas, so that the depth distribution can be more freely controlled than by ion implantation. That is, by sequentially laminating epitaxial layers of different concentrations, an impurity distribution having an arbitrary distribution in the depth direction can be formed. Due to this property, it is possible to easily realize the depth distribution of the impurity distribution in the present invention.

Generally, the smaller the MISFET is, the smaller the W _DEP is, and therefore, the desired thickness of the surface low concentration layer is reduced. For this reason, as the miniaturization progresses, it becomes difficult to sufficiently reduce the concentration of the low impurity concentration layer on the substrate surface when the ion implantation method is used. Therefore, after introducing impurities into the substrate,
If a semiconductor layer containing no impurities is epitaxially grown thereon, the concentration near the surface can be sharply reduced, and a thin low-concentration layer can be formed precisely.

FIG. 6 shows the state of FIG.
2 shows a process flow for creating an impurity distribution of FIG.

First, referring to FIG. 6A, after forming an element isolation insulating film 11 on a semiconductor substrate, a high impurity concentration layer 12 is provided on the substrate by ion implantation. Next, FIG.
As shown in (b), a known chemical vapor deposition (CVD)
According to the method, the semiconductor layer 13 in which impurities are not mixed is selectively epitaxially grown only on the surface where the semiconductor is exposed.

Subsequently, as shown in FIG. 6C, formation of a gate insulating film, formation of a gate electrode, and formation of a source / drain diffusion layer by oxidation are performed in the same manner as in a normal MISFET.

Since the impurity concentration changes abruptly between the epitaxial layer 13 and the ion-implanted layer 12, an impurity distribution close to a step shape as shown in FIG. 4 is obtained.

That is, in FIG. 4, the portion having the concentration N1 is constituted by the semiconductor layer 13 and the portion having the concentration N2 is constituted by the high impurity concentration layer 12, so that a steep concentration change is obtained and the effective substrate concentration can be effectively reduced. Becomes

In FIG. 6, the epitaxial growth is performed after forming the element isolation insulating film 11. However, as shown in FIG. 7, the epitaxial growth may be performed before the element isolation insulating film 11 is formed.

That is, as shown in FIG.
First, a high impurity concentration layer 12 is provided on a substrate by ion implantation.

Subsequently, as shown in FIG.
The semiconductor layer 13 containing no impurities is epitaxially grown on the entire surface of the semiconductor substrate by a known chemical vapor deposition (CVD) method. Subsequently, as shown in FIG. 7C, the formation of an element isolation insulating film, the formation of a gate insulating film by oxidation, the formation of a gate electrode, and the formation of a source / drain diffusion layer are performed by a normal MISFET.
Perform in the same manner as described above.

In the above, the MISFET has been described as being formed on the bulk semiconductor substrate. However, the same effect can be obtained in a MISFET using an SOI substrate. However, when the depletion layer of the channel reaches below the buried oxide film, the integral range of the equations (2), (4) and (5) needs to include the buried oxide film portion. At this time, if N _SUB (x) = 0 is set in the buried oxide film, the discussion so far can be applied as it is.

In the above, an example in which an n-channel type MISFET is used has been described. But p-channel type MISFET
It is obvious that the sign of the voltage may be reversed in the above description.

Next, a semiconductor device using the MISFET will be described.

FIG. 8 shows the most basic configuration of a differential amplifier circuit using MISFETs. The two transistors T1 and T2 are collectively called a "differential pair". Two input terminals Vin1 and Vin2 for receiving a differential signal are connected to the gate electrodes of two transistors T1 and T2 which are designed identically. The input signals Vin1 and Vin2 are amplified and output as output signals Vout1 and Vout2.

In this example, the difference between the input signals (Vin1-V
The larger (in2) is, the larger the difference (Vout1-Vout2) between the output signals is. Also, the sign of the difference between the input signals and the sign of the difference between the output signals match.

One of the important uses of the differential amplifier circuit is to determine whether the difference between the input signals (Vin1−Vin2) is positive or negative.
For that purpose, it is necessary that the characteristics of the two transistors T1 and T2 are uniform. For example, in the example of FIG. 8, there is a difference in the threshold voltages of the transistors T1 and T2, the threshold of the transistor T1 is higher by dVTH than the threshold value of the transistor T2, dV _TH> of Vin1-Vin2> 0 In the range, V
Although in1-Vin2> 0, Vout1-Vout2 <0, and an error occurs in the sign determination. Therefore, the MI of the present invention
If an SFET is used, this problem can be solved.

FIG. 8 shows the most basic differential amplifier, but this is an example, and the circuit configuration of the differential amplifier is various. FIG. 9 shows a configuration of a differential amplifying device often used for a sense amplifier of an SRAM. The differential pair is composed of n-channel MISFETs T1 and T2. The MISFET T11 in FIG. 9 functions as the constant current source Iss in FIG. By operating in the saturation region, the MISFET T11 approximately operates as a constant current source. The load resistance in FIG.
In place of R1 and R2, FIG. 9 shows a p-channel MISFET T3
A so-called current mirror configuration including T4 is used. That is, T3 and T4, which are formed identically, have their source electrode and gate electrode connected to each other, and when both operate in the saturation region, the same amount of current flows through T4 as T3.

In this configuration, when the voltage of the input signal Vin1 increases, the current flowing through T3 increases. As a result, the current of T4 also increases, and the output voltage Vout1 increases. With this configuration, a high gain can be realized. When a load is a simple resistor,
To increase the gain, it is necessary to increase the resistance.
However, in an integrated circuit, it is disadvantageous to produce a high resistance because a large area is required, so that a load is often constituted by a combination of transistors as in this example.

Although the circuit of FIG. 9 has a single output terminal and an asymmetric structure, if it is desired to obtain a differential output, use a symmetric configuration combining two circuits of FIG. 9 as shown in FIG. Can be. FIG. 10 shows a configuration in which two differential amplifiers are combined, so that the first differential pair including T1 and T2 and T5
And a second differential pair comprising T6 and T6.

FIG. 11 shows the basic configuration of a differential amplifier used as a sense amplifier of a DRAM. The differential pair is composed of n-channel MISFETs T1 and T2. The output of the left amplifying element consisting of T1 and T3 is directly connected at node N2 to the input signal Vin2 of the right amplifying element consisting of T2 and T4. Conversely, the output of the right amplification element is directly connected at the node N1 to the input signal Vin1 of the left amplification element. That is, the output is fed back to the input like a cross. Here, the terminals for the input signals Vin1 and Vin2 have a special structure that also serves as output terminals at the same time, and are suitable for the operation of a DRAM that performs rewriting immediately after reading.

In operation, first, the DRAM is connected to the input terminal Vin1.
Voltage (positive or negative) read from memory cell
And a reference voltage (1/2 of the normal power supply voltage), and the reference voltage is applied to Vin2. At this time, MISFET
Both T11 and T12 are turned off, and the nodes N11 and N12 are also set as reference voltages.

Next, when T11 is turned on, if Vin1> Vin2, T1 has higher conductivity than T2, so that the voltage of Vin2 is lower than that of Vin1. This further increases the conductivity of T1 compared to T2, and preferentially lowers the voltage of Vin2. As a result, after the potential difference between Vin1 and Vin2 is amplified to some extent, T12 is subsequently turned on.

Then, by the positive feedback action, T1 and T4 are turned on, T2 and T3 are turned off, Vin1 is Vdd, Vin2 is Vss
And the amplification is completed. The resulting voltage Vin1 or
Vin2 is read out to the outside, and Vin1 is also applied to the storage capacity of the read memory cell, thereby realizing data write-back. When Vin1 <Vin2, the operation is similar to the above.

As described above, the present circuit determines whether Vin1 is higher or lower than Vin2. If higher, Vin1 is raised to the power supply voltage Vdd, and if lower, Vin1 is lowered to the ground potential Vss.
Has a function suitable for M operation.

Here, the n-channel MISFET T1 is
The description has been made assuming that T2 is a differential pair, because it is assumed that the operation of first amplifying the very small voltage is performed by T1 and T2. In this case, since T3 and T4 do not function to detect the first minute potential difference, they can be regarded as load elements. However, the operation of reversing the roles of T1, T2, T11 and T3, T4, T12 is also possible, and in this case, T3 and T4 can be interpreted as constituting a differential pair.

As exemplified above, a differential amplifier generally using MISFETs has the same MISFET T1 as shown in FIG.
And T2, input terminals Vin1 and Vin2 coupled to their gates, high and low power supply terminals Vdd and Vss (for example, 5V for the former and 0V for the latter), and operate as a load or bias circuit And additional circuits C1 and C2, and at least one output terminal Vout.

In many cases, two output terminals are provided to provide a differential output. In a special case, the output terminal may be shared with the input terminal as in the example of FIG. In any case, the basic operation is common in that the difference between Vin1 and Vin2 is amplified and output to Vout.

What is particularly important here is the differential pair MISFET T1
And the characteristics of T2. The present invention provides a differential pair
By using a special vertical impurity distribution for MISFET,
It is intended to suppress the variation in the threshold value of T2 and reduce the unevenness of the characteristics of both.

A feature of the present invention lies in the structure of the differential pair MISFET used in the differential amplifier circuit having the basic structure of FIG. With the basic structure of FIG. 12, the present invention is effective regardless of the specific configuration of the differential amplifier circuit shown in FIGS. 9, 10 and 11, or any other configuration. .

[0103]

According to the present invention, in a differential amplifier using a MISFET as an input portion, an input offset voltage caused by variation is reduced, and a sign of a minute potential difference can be detected with high accuracy. Can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cross section of a MISFET.

FIG. 2 is a diagram showing an impurity concentration distribution along a cross section AA ′;

FIG. 3 is an impurity concentration distribution along a section AA ′ (2).

FIG. 4 is a diagram showing an ideal impurity distribution;

FIG. 5 is a view illustrating a calculation result of an effective substrate concentration.

FIG. 6 is a diagram illustrating a method of manufacturing a semiconductor device to which the present invention is applied.

FIG. 7 is a diagram showing a method of manufacturing a semiconductor device to which the present invention is applied.

FIG. 8 is a diagram illustrating a configuration of a basic differential amplifier.

FIG. 9 is a diagram illustrating a configuration of a current mirror load differential amplifying device (asymmetric type).

FIG. 10 is a diagram illustrating a configuration of a current mirror load differential amplifying device (symmetric type).

FIG. 11 is a diagram illustrating a configuration of a cross-coupled differential amplifier.

FIG. 12 is a diagram illustrating a configuration of a generalized differential amplifier.

[Explanation of symbols]

 1: semiconductor substrate 2: gate insulating film 3: gate electrode 4: source 5: drain 6: depletion layer 7: inversion layer 11: element isolation insulating film 12: ion implantation layer 13: epitaxial layer

Claims (12)

[Claims] A plurality of MISFETs, each of the plurality of MISFETs having a gate electrode formed on a substrate, and a source region and a drain region formed on a surface of the substrate; A first region is provided in a region below the gate electrode, a second region is provided in the substrate from the first region, and a thickness of the first region and a thickness of the second region are provided. The sum of the thicknesses is smaller than the thickness of the source region or the drain region, and the second region has a higher impurity concentration than the first region. 2. A semiconductor device comprising: a plurality of MISFETs; each of the plurality of MISFETs includes a gate electrode formed on a substrate, and a source region and a drain region formed on a surface of the substrate; A first voltage from the surface of the substrate in a depletion layer formed when a value voltage is applied.
And a second region following the first region in the substrate than the first region, wherein the second region has a higher impurity concentration than the first region. 3. The semiconductor device according to claim 2, wherein the sum of the thickness of the first region and the thickness of the second region is smaller than the thickness of the source region or the drain region. 4. The semiconductor device according to claim 1, wherein the first region has the same conductivity type or intrinsic property as the substrate, and the second region has the same conductivity type as the substrate. 5. A first step of forming a first region and a second region in a surface region of the semiconductor substrate between element isolation insulating films formed on a semiconductor substrate, and wherein the second region is formed of the first region and the second region. Forming a MISFET having a source region, a drain region, and a gate electrode in the surface region of the semiconductor substrate, the impurity concentration being higher than that of the first region;
A method for manufacturing a semiconductor device, comprising: 6. The first step comprises: implanting impurity ions into a surface of the semiconductor substrate;
Forming a region having a lower impurity concentration than the second region on the surface of the semiconductor substrate as the first region; and forming the element isolation insulating film. 6. The method for manufacturing a semiconductor device according to item 5. 7. The first step includes: forming the device isolation insulating film; and implanting impurity ions into the surface of the semiconductor substrate between the device isolation insulating films to form the second region. The second surface of the semiconductor substrate between the element isolation insulating films;
Forming a layer having an impurity concentration lower than that of the first region as the first region. 8. A semiconductor device having first and second MISFETs designed identically, wherein a voltage applied to a gate electrode of the first MISFET and a voltage applied to a gate electrode of the second MISFET are different from each other. In the amplifier that amplifies and outputs the difference, the depth direction distribution of the substrate impurity concentration in the channel region of the MISFET is:
A semiconductor device, wherein the same threshold value is given, and the effective substrate concentration is set to be lower than when the impurity concentration is uniform in the depth direction. 9. A semiconductor device having first and second MISFETs designed identically, wherein a voltage applied to a gate electrode of the first MISFET and a voltage applied to a gate electrode of the second MISFET are different from each other. In the amplifying device for amplifying and outputting the difference, the depth direction distribution of the substrate impurity concentration in the range of the depletion layer formed immediately below the channel inversion layer of the MISFET is the first distribution from the substrate surface.
A semiconductor device which is smaller than the first region in the second region in the first region. 10. A semiconductor device comprising first and second MISFETs designed identically, wherein a voltage applied to a gate electrode of the first MISFET and a voltage applied to a gate electrode of the second MISFET are different from each other. An amplifier device for amplifying and outputting a difference, wherein an epitaxially grown layer is provided in a channel region of the MISFET, and the impurity concentration of the epitaxially grown layer is lower than that of a semiconductor region immediately below the epitaxially grown layer. 11. A first region from a surface of the substrate in a depletion layer during operation of a MISFET, and a second region inwardly of the substrate from the first region, wherein the second region is provided in the depletion layer.
A semiconductor device in which the maximum impurity concentration of the region is 100 times or more the maximum impurity concentration of the first region. 12. A gate electrode, a first semiconductor region of 10 ¹⁸ atoms / cm ^-3 or more provided in an inversion layer in the substrate below the gate electrode, and the gate electrode and the first semiconductor region. The intermediate layer between the gate oxide film and the second semiconductor region includes at least the capacitance of the gate oxide film, the thickness of the first semiconductor region and the second semiconductor region in the depth direction of the substrate, and the impurity concentration. A semiconductor device in which a threshold distribution of a MISFET having the gate electrode is controlled based on the following.