JPH11150427A - Amplifier circuit and liquid crystal display device using the same - Google Patents

Abstract

(57) [Summary] [PROBLEM] To eliminate the need for a phase compensation capacitor for stabilization,
Provided is an amplifier circuit which can reduce the chip area by a large amount and can operate stably. A signal input terminal of an amplifier circuit is provided.
Input amplification stage 2 and output amplification stage 3 are cascaded between the output amplification stage 3 and the signal output terminal OUT, and a resistance circuit 4 including at least one resistor is inserted between the output terminal of the output amplification stage 3 and the signal output terminal OUT. By doing so, a first zero point having a lower frequency than the frequency at which the gain becomes 1 is formed in the open loop frequency characteristic of the amplifier circuit 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier circuit for driving a capacitive load according to an input signal voltage which changes every predetermined period, for example, and a liquid crystal display device using the same. And an amplifier circuit having a small area and low power consumption.

[0002]

2. Description of the Related Art In general, a liquid crystal display device has a structure in which liquid crystal cells are arranged in a matrix, and a plurality of signal lines to which image signals are supplied and a plurality of scanning lines are arranged so as to intersect. The liquid crystal display includes a display panel, a liquid crystal display driving circuit for supplying an image signal to a signal line to drive the liquid crystal display panel, and a scanning line selection circuit for selectively driving a scanning line.

As a signal line drive circuit of a liquid crystal display drive circuit of this liquid crystal display device, an amplifier circuit having a voltage follower configuration has been used. Since the gain A of the amplifier circuit is finite, an error between input and output caused by the voltage follower configuration is represented by 1 / A of the input voltage. In order to reduce this error, a two-stage configuration has been used as an amplifier circuit of the signal line drive circuit. More specifically, the configuration includes an input amplification stage and an output amplification stage having a phase compensation capacitance Cf.

[0004]

In the conventional configuration, when the load capacitance connected to the output amplifier stage is large, the phase compensation capacitance is set to, for example, 3 to 5 pF in order to stably operate the amplifier circuit with low power consumption. I have to make it as large as possible. Further, by increasing the bias current, it is necessary to increase the transconductor of the second amplification stage. Therefore, when a drive circuit including, for example, 300 amplifier circuits is integrated, a phase compensation capacitance Cf of 3 to 5 pF is required for one amplifier circuit.
There is a problem that a capacitance of 500 pF is required and the chip area becomes very large. Further, there is a problem that current consumption increases for stabilization.

As described above, in an amplifier circuit connected to a large-capacity capacitive load, the conventional method of stabilizing an amplifier circuit by a phase compensation capacitor requires a plurality of amplifier circuits to be integrated. However, there is a problem that the total sum of the phase compensation capacitors becomes very large, the chip area increases, and the cost increases. In addition, there is a problem that current consumption increases.

[0006]

According to the present invention, a phase compensation capacitor for stabilization is not required or can be greatly reduced to reduce the chip area and operate stably. It is an object of the present invention to provide an amplifier circuit that reduces noise.

According to the present invention, a plurality of amplifying stages cascaded between a signal input terminal and a signal output terminal to which a capacitive load is connected and having at least an input amplifying stage and an output amplifying stage; Provided is an amplifier circuit including a resistor circuit including at least one resistor inserted between an end and a signal output terminal.

This resistor circuit is constituted by a plurality of resistors, and at least one resistor selected from the plurality of resistors is connected between the output amplification stage and a signal output terminal.
This resistance circuit is composed of a plurality of resistors and a plurality of switches, and the resistance value of the resistance circuit is set by turning on / off the switches. Further, the resistance circuit may be configured by the on-resistance of the field effect transistor.

According to the present invention, a feedback path for providing feedback from the output terminal of the output amplifier stage to the input terminal of the input amplifier stage is provided, and the amplifier circuit is configured as a voltage follower.

In the amplifier circuit thus configured, the frequency of the second pole appearing in the open loop frequency characteristic is lower than the frequency at which the gain of the amplifier circuit becomes 1, and the first zero point appearing in the open loop frequency characteristic is obtained. Is preferably lower than the frequency at which the gain of the amplifier circuit becomes 1.

In addition, for example, in the input-converted offset voltage mode, the signal output terminal of the amplifier circuit is disconnected from the capacitive load, and equivalently the input / output terminal of the output amplifier stage is stabilized for stabilization when the load capacitance is reduced. Capacitance between (phase compensation capacitance)
May be provided.

In the amplifier circuit according to the present invention, the open loop frequency characteristic of the amplifier circuit is firstly adjusted by the resistance component of the resistance circuit and the capacitance component of the capacitive load inserted between the output terminal of the output amplification stage and the signal output terminal. A zero point is formed, and the phase advance at this zero point allows the output amplifying stage to compensate for the phase delay due to the pole. In other words, the phase margin, which is the difference between the phase when the gain is 1 and -180 degrees, can be increased, so that a phase compensation capacitor for stabilizing the operation of the amplifier circuit is not required. Further, even when a phase compensation capacitor is required, its value may be very small, so that the chip area required for forming the phase compensation capacitor can be reduced. Furthermore, current consumption can be reduced.

In the amplifier circuit of the present invention, when an input signal voltage that changes every predetermined period is input to the signal input terminal,
It is desirable that the time constant of the resistive circuit and the capacitive component of the capacitive load be 1/5 or less of the predetermined period. In this case, the resistance value of the resistance circuit is suitably, for example, 50 kΩ or less.

The amplifier circuit of the present invention may further include a control unit for detecting that the input signal voltage input to the signal input terminal has changed to a predetermined polarity and controlling the bias current of the output amplification stage. Good.

According to the present invention, the input amplification stage has a positive-side amplifier circuit and a negative-side amplifier circuit for inputting first and second input signals respectively changing to a positive side and a negative side with respect to a predetermined common voltage. It can also be applied to a two-input amplifier circuit.

According to a preferred embodiment of the two-input amplifier circuit, the positive-side amplifier circuit supplies a first differential transistor pair for inputting a first input signal and a tail current to the first differential transistor pair. A first current source, a first current mirror having a current input terminal and a current output terminal connected to two output terminals of the first differential transistor pair, respectively, and two outputs of the first differential transistor pair; A first switch provided between the terminals; the negative-side amplifier circuit supplies a second differential transistor pair for inputting a second input signal; and a tail current to the second differential transistor pair. A first current source;
A second current mirror having a current input terminal and a current output terminal connected to two output terminals of the second differential transistor pair, respectively, and a second current mirror provided between two output terminals of the second differential transistor pair. And when the first input signal is input to the positive side amplifier circuit, the first switch is controlled to be in an off state and the second switch is controlled to be in an on state. Is input to the negative-side amplifier circuit, the first switch is controlled to be on and the second switch is controlled to be off.

On the other hand, the output amplifying stage is constituted by a complementary transistor pair whose drain or collector is commonly connected to the output terminal of the output amplifying stage, and one of the gates or bases of the complementary transistor pair is connected to the positive side amplifier. The complementary transistor pair is connected to one output terminal of the circuit, and the other gate or base of the complementary transistor pair is connected to one output terminal of the negative side amplifier circuit.

In the two-input amplifier configured as described above, the phase compensation capacitor is not required as described above, or a very small capacitor can be used, and the positive and negative amplifier circuits can be used. The short circuit between the output terminals of the differential transistor pair in the amplifier circuit which is not used because the input signal voltage is not input and which is not used makes it possible to easily set the bias current of the output amplification stage.

Further, as another aspect of the two-input amplifier circuit, in addition to the configuration of the two-input amplifier circuit described above, the first and second current sources are turned on / off in the positive-side amplifier circuit and the negative-side amplifier circuit. A third and a fourth switch for turning off are added, and a second current output terminal of the first current mirror is connected to a current input terminal of the second current mirror via a fifth switch. When the second current output terminal of the second current mirror is connected to the current input terminal of the first current mirror via the sixth switch, and the first input signal is input to the positive side amplifier circuit, The first, fourth, and sixth switches are controlled to be in an off state, and the second, third, and fifth switches are controlled to be in an on state. When the second input signal is input to the negative side amplifier circuit, the first , The fourth and sixth switches are on, the second It may also be the third and fifth switches are controlled to be turned off, thus to further reduce power consumption becomes possible.

The amplifier circuit of the present invention configured as described above has a plurality of pixels, a signal line for selectively applying a signal voltage corresponding to an image signal to each of the pixels, and a signal line crossing the signal line. The present invention is useful as an amplifier circuit of a driving circuit in a liquid crystal display device including a liquid crystal display in which scanning lines are arranged and formed, a driving circuit for driving signal lines in accordance with an image signal, and a selecting circuit for sequentially selecting scanning lines.

According to the present invention, there is provided a liquid crystal display in which a plurality of pixels, a signal line for selectively applying a signal voltage corresponding to an image signal to each of the plurality of pixels, and a scanning line crossing the signal line are formed. And a drive circuit for driving the signal lines in accordance with the image signals, and a selection circuit for sequentially selecting the scan lines. The drive circuit is connected to a signal input terminal to which an input signal is supplied and a capacitive load. A plurality of amplifying stages having at least an input amplifying stage and an output amplifying stage connected in cascade with a signal output terminal; and at least one resistor inserted between an output terminal of the output amplifying stage and the signal output terminal The present invention provides a liquid crystal display device including an amplifier circuit constituted by a resistor circuit including:

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a basic configuration of an amplifier circuit according to one embodiment of the present invention. This amplifier circuit 1
Is a circuit that amplifies a differential input signal input between a pair of signal input terminals IN + and IN− and outputs the amplified signal from a signal output terminal OUT. The output amplification stage 3 for amplification is cascaded. Between the output terminal of the output amplification stage 3 and the signal output terminal OUT of the amplification circuit 1, a resistance circuit 4 according to the present invention is inserted.

Further, a feedback circuit 5 for providing feedback from the output terminal of the output amplification stage 3 to the input terminal (signal input terminal IN−) of the input amplification stage 2 is provided as needed. Further, a feedback circuit including a phase compensation capacitor Cf having a minute capacitance value may be inserted between the input and output terminals of the output amplification stage 3 as needed.

Next, the operation of the amplifier circuit 1 shown in FIG. 1 will be described.

FIG. 2 is an equivalent circuit of the amplifier circuit 1 and g
m1 is the transconductance of the input amplification stage 2, R1 is the parallel combined resistance of the output resistance of the input amplification stage 2 and the input resistance of the output amplification stage 3, C1 is the capacitance component added to the output terminal of the input amplification stage 2, gm2 Is the transconductance of the output amplifier stage 3, R2 is the output resistance of the output amplifier stage 3, Rf is the resistance component of the resistor circuit 4, and CL is the load capacitance. Also, vi is the input signal voltage to the signal input terminals IN + and IN−, v1 is the output voltage of the input amplification stage 2, v2 is the output voltage of the output amplification stage 3, and vo is the output signal voltage to the signal output terminal OUT. Represent.

Here, in the amplifier circuit 1 of FIG. 1, the frequency of the second pole appearing in the open-loop frequency characteristic is lower than the frequency at which the gain of the amplifier circuit 1 becomes 1, and the output terminal of the output amplifier stage 3 A resistance circuit 4 is connected between the signal output terminal OUT.
To introduce a first zero into this open loop frequency characteristic. That is, the first and second poles and the first zero point of the amplifier circuit 1 are obtained as follows from the transfer characteristics from the input signal voltage vi to the output voltage v2 derived using the equivalent circuit of FIG. .

First pole frequency (rad / sec): 1 /
((R2 + Rf) CL) (However, from R2 >> Rf, approximately 1 / (R2 · C
L)) Second pole frequency (rad / sec): 1 / (R1 · C1) First zero point frequency (rad / sec): 1 / (Rf · CL) FIGS. 3 (a) and 3 (b) The solid line indicates the open-loop frequency characteristics of the amplitude and phase when the resistor circuit 4 is provided.
When there is no resistance circuit 4 for comparison (Rf = 0)
Is indicated by a broken line. As shown in FIG. 3B, the phase delayed by the first and second poles can be advanced by the zero point formed by the resistance circuit 4 according to the present invention, and the phase margin can be improved. . Therefore, a phase compensation capacitor, which is conventionally required, is not required for stabilizing the operation of the amplifier circuit 1, so that a chip area required for forming the phase compensation capacitor can be reduced. .

In the conventional phase compensation, the second pole frequency is approximated to gm2 / CL with respect to a large capacity load. Therefore, the phase margin can be improved by increasing the current of the output amplification stage. , Power consumption had increased. On the other hand, in the present invention, since the transconductor itself does not directly relate to the frequency of the pole, phase compensation can be performed with low-frequency power.

As described above, the amplifier circuit of the present invention basically does not require a phase compensation capacitor. However, a minute phase compensation capacitor Cf may be added to the amplifier circuit 1 as described below. The amplifier circuit 1 generally has an input-converted offset voltage (Vos). This input-converted offset voltage V
os is modeled in such a manner that, as shown in FIG. 4A, for example, a voltage source corresponding to an input-referred offset voltage Vos is inserted into one input (here, a non-inverting input) of an amplifier circuit having no offset. it can. As shown in FIG. 4B, when negative feedback is applied to the amplifier circuit and the amplifier circuit is used in a voltage follower configuration, the output signal voltage Vout becomes the input signal voltage Vin.
Is offset by a voltage equivalent to the input conversion offset voltage Vos.

In order to cancel the input-converted offset voltage Vos, a capacitor Ch and switches SW1 to SW3 are conventionally used as shown in FIG.
By closing W3 and opening SW2 to make the amplifier circuit a voltage follower configuration, an input-converted offset voltage Vos is applied to the capacitor Ch (input-converted offset detection mode), and then as shown in FIG. Then, the switches SW1 and SW3 are opened and the switch SW2 is closed to change the connection so that the capacitance Ch to which the offset voltage Vos is applied enters the other input (inverted input) of the amplifier circuit in series, thereby canceling the input-converted offset Vos. Had to take a way.

In order to cancel the input-converted offset voltage, a time for detecting the offset voltage shown in FIG. 5A is required. In order to shorten this time, the signal output terminal of the amplifier circuit is usually connected to the input terminal. The load capacitance CL is disconnected by the switch SW4.

When this input-converted offset voltage canceling technique is applied to the amplifier circuit of the present invention as it is, in the offset voltage detection mode of FIG. 5A, the signal output terminal OUT of the amplifier circuit 1 of FIG. As a result, the frequency of the first pole and the first zero point shifts from the state shown by the solid line to the higher frequency as shown in FIG. 6, resulting in a reduction in phase margin. Therefore, if the effective load capacitance CL is reduced as in the offset voltage detection mode and the phase compensation capacitance Cf is used together as shown by a broken line in FIG. 1, such a problem can be avoided. And a phase margin can be secured. In this case, since the phase compensation capacitance Cf may be a small value, for example, 0.5 pF, an increase in the chip area is small, and
The advantages of the present invention are not compromised.

Next, a specific circuit configuration of the amplifier circuit of FIG. 1 will be described with reference to FIGS. 7 to FIG.
1 shows a first specific example of the amplifier circuit. The first amplifier circuit shown in FIG. 7 has a configuration having two amplification stages, and includes a current source and a differential circuit including transistors Mp1 and Mp2 forming a differential transistor pair and a transistor Mp4 for providing a tail current to the differential transistor pair. An input amplification stage composed of a current mirror composed of transistors Mn1 and Mn2 having a current input terminal and a current output terminal connected to the drains of the two output terminals of the transistor pair, and an output amplification stage composed of a complementary transistor pair composed of transistors Mp3 and Mn3. And a resistor Rf forming a resistor circuit. Note that Mpx is a P-channel MOS transistor, M
nx represents an N-channel MOS transistor (the same applies hereinafter).

FIG. 8 shows a second specific example of an amplifier circuit using the on-resistances of the transistors Mpr and Mnr instead of the resistor Rf of FIG. According to this, the source and the drain of the P-channel MOS transistor Mpr and the N-channel MOS transistor Mnr forming the resistance circuit are connected to each other, connected between the nodes of the transistors Mp3 and Mn3 and the output terminal OUT, and the transistor Mp
The gates of r and Mnr are connected to power supplies Vdd and Vss, respectively.

FIG. 9 shows the function of the switch SW4 required for the input-converted offset voltage canceling operation of the amplifier circuit described with reference to FIGS. 4 and 5 by using the transistors Mpr and Mn shown in FIG.
A third specific example of an amplifier circuit in which r also functions is shown.
According to this amplifier circuit, the gate of the transistor Mnr is connected to the gate of the transistor Mpr via the inverter IN. According to this circuit, when a switching signal is input to the signal line SL, both transistors Mpr, Mpr,
Mnr is turned on, and this on resistance performs the function of the resistance Rf.

FIG. 10 shows a simulation result of the gain and phase frequency characteristics when the value of the load capacitance CL is 150 pF in the amplifier circuit of FIG. It can be seen that the provision of the resistor Rf significantly improves the phase margin as compared with the case without the resistor Rf.

As described above, the signal output terminal OUT is disconnected from the load capacitance CL in the input-converted offset voltage detection mode or the like.
When the pF becomes small, the obtained phase margin becomes small as shown in FIG. For this, for example, 0.5
By using pF and a small phase compensation capacitance Cf together,
As shown in FIG. 12, a large phase margin can be ensured for both large and small load capacities.

As shown in FIG. 13, even if the capacity is small,
When a large capacity load is used by using the phase compensation capacitor Cf together, the phase margin is slightly reduced. FIG. 14 shows a switch SWC connected in series to the phase compensation capacitor Cf to improve this point.
Is provided, the signal output terminal OUT is disconnected from the load capacitance CL in the input conversion offset voltage detection mode or the like, and equivalently, the switch SWC is closed only when the load capacitance CL is reduced to, for example, 2 pF. The fourth example is shown. According to this, the switch SWC is connected between the node of the transistors Mn2 and Mn3 and the capacitor Cf, and when the load capacitance CL decreases, the switch SWC is closed. As a result, the original phase margin according to the present invention can be secured.

The signal line of the liquid crystal display is represented by a simple capacitance model as described above, a π-type model as shown in FIG. 15, or the like. Even if the load includes the resistance component RL as in the π-type model, the frequency characteristics hardly change as is clear from the simulation results shown in FIG.

FIG. 17 shows a voltage follower configuration in which feedback is provided from the output terminal (drain of transistors Mn3 and Mp3) of the output amplifier stage of the amplifier circuit shown in FIG. 7 to the negative signal input terminal IN-. The simulation result at the time of inputting a rectangular wave as a voltage is shown. In the amplifier circuit shown in FIG.
It is determined by the current supplied from p3 and the value of the load capacitance value CL. Since the current supplied from the transistor Mp3 is small, a sufficient slew rate cannot be obtained.

In this regard, the rise slew rate is increased by detecting that the input signal voltage of the amplifier circuit has changed to the positive side and increasing the output current of the transistor Mp3 that supplies the bias current of the output amplifier stage. Can be improved.

FIG. 18 shows a fifth specific example of an amplifier circuit in which the rising slew rate is improved based on this principle. This amplifier circuit detects that the input signal voltage has changed to the positive polarity by the transistors Mn4 and Mp6. Then, when the input signal voltage changes to the positive polarity, the transistor Mp7 is turned on, and the current supplied from the current source IL is changed to the transistor Mp7.
3 to the diode-connected transistor Mp5 which determines the gate bias voltage of the transistor Mp3.
Are configured to increase the gate bias voltage.

The circuit of FIG. 18 will be described in more detail. The transistor Mp6 forms a current source, and its gate is connected to the drain and gate of the bias current determining transistor Mp5. The transistor Mp7 has a gate connected to the drains of the transistors Mn4 and Mp6, and a source connected to the bias current determining transistor Mp4.
5, and the drain is connected to the constant current source IL.

Here, in order to simplify the description, the transistor Mn4 and the transistor Mn1 of the input amplification stage 2 have the same size, that is, W / L (W is the channel width of the MOS transistor, and L is the channel length of the MOS transistor). It is assumed that they are the same. It is also assumed that the size (W / L) Mp6 of the transistor Mp6 is 0.6 times the size (W / L) Mp4 of the current source transistor Mp4 of the input amplification stage 2. When the voltage applied between the signal input terminals IN + and IN− is zero or negative, that is, the signal input terminal IN on the positive side
When the voltage of + is lower than the voltage of the signal input terminal IN− on the negative side, a current that is less than half of the current supplied from the transistor Mp4 flows through the transistor Mn1, and the current of the transistor Mn1 is copied by the transistor Mn4.

Here, the current supplied from the transistor Mp6 is 0.6 times the current supplied from the transistor Mp4. In this case, since the current supplied to the transistor Mp4 is larger than the current supplied to the transistor Mp4, the drain voltage of the transistor Mp6 increases. Since the transistor Mp7 is turned off, the current supplied from the current source IL
Not added to 5.

On the other hand, when the input signal voltage applied between the signal input terminals IN + and IN− is equal to or higher than a predetermined positive voltage, that is, the voltage of the positive signal input terminal IN + is changed to the negative signal input terminal IN +. When the voltage is higher than the negative voltage by a predetermined value,
A current larger than 0.6 times the current supplied from the transistor Mp4 flows through the transistor Mn1, and the current of the transistor Mn1 is copied by the transistor Mn4.

Here, the current supplied from the transistor Mp6 is 0.6 times the current supplied from the transistor Mp4. In this case, since the current supplied to the transistor Mp4 is smaller than the current supplied to the transistor Mp4, the drain voltage of the transistor Mp6 decreases. , The transistor Mp7 is turned on. As a result, the current supplied from the current source IL is supplied to the bias current determining transistor Mp5 via the transistor Mp7.
, The gate-source voltage of the transistor Mp5 increases, and the current supplied from the transistor Mp3 also increases.

In this manner, when the input signal voltage changes to the positive polarity, the current supplied from the transistor Mp3 of the output amplification stage 3 can be controlled to be large, so that the rising slew rate can be improved. .

In FIG. 19, in the amplifying circuit in which the rising slew rate shown in FIG. 18 is improved, the output from the output amplifying stage (the drains of the transistors Mn3 and Mp3) is fed back to the negative signal input terminal IN-. 7 shows a simulation result when a rectangular wave is input as an input signal voltage in a voltage follower configuration. Here, v2 is the output voltage of the output amplification stage 2 (transistors Mp3 and Mn3
, Vo is the voltage of the signal output terminal OUT. It can be seen that the rising characteristics are improved to the same extent as the falling characteristics.

Since the resistance circuit Rf and the load capacitance CL constitute a low-pass filter (hereinafter referred to as LPF), vo is delayed from v2 by the time constant τ (= Rf · CL). Normally, in an LPF formed by a resistor and a capacitor, a time approximately five times the time constant is required for settling. Therefore, the amplifier circuit of the present invention is applied to, for example, a liquid crystal display driving circuit in which a signal voltage changes every predetermined period. In this case, the time constant τ may be set to be 1/5 or less of the predetermined period.

By doing so, as shown in FIG. 19, the signal output terminal O with respect to the output voltage v2 of the input amplification stage 2
The predetermined settling characteristics can be satisfied by reducing the delay time of the voltage vo of the UT. Specifically, for example, since the driving cycle of the signal voltage in the liquid crystal display driving circuit is approximately 20 μsec, the load capacitance CL is set to 50p.
Assuming about F to 100 pF, the value of the resistance circuit Rf may be set to 50 kΩ or less.

Since the signal line of the liquid crystal display varies depending on the size of the display and the material of the signal line, it is desirable to select the resistor Rf to an optimum value according to these. 20 to 22 show specific examples for setting the resistance Rf to an optimum value.

FIG. 20 shows the output terminals (the drains of the transistors Mn3 and Mp3) of the output amplification stage and the signal output terminal OUT.
And a plurality of resistors Rf10, Rf11,
Are arranged in parallel via switches SW10, SW11, SW12,..., And switches SW10, SW11, SW12,.
This is a specific example of an amplifier circuit in which the value of the resistor Rf is selected by controlling the opening and closing of.

In FIG. 20, resistors Rf10 and Rf1
, Rf12,... Have the same resistance, and switches SW10,
The value of the resistor Rf may be selected by changing the number of resistors connected in parallel by opening and closing SW11, SW12,.

FIG. 21 shows the output terminals (the drains of the transistors Mn3 and Mp3) of the output amplification stage and the signal output terminal OUT.
And a plurality of resistors Rf10, Rf11,
.. Are arranged in series, and each resistor Rf10,.
Rf11, Rf12,... Switches SW10, SW11, SW1
2, ... are arranged in parallel, and switches SW10, SW11, SW1
This is a seventh specific example of an amplifier circuit in which the value of the resistor Rf is determined by controlling the opening and closing of 2,.

In FIG. 21, the resistors Rf10, Rf1
, Rf12,... Have the same resistance, and switches SW10,
The value of the resistor Rf may be selected by changing the number of resistors connected in series by opening and closing SW11, SW12,.

FIG. 22 shows that a plurality of resistors Rf10, Rf11, Rf12,... Are formed in advance on a chip when the amplifier circuit is integrated, and the resistance value Rf is optimized according to the liquid crystal display panel. As described above, these resistors Rf10,
This is an eighth specific example of an amplifier circuit realized by changing one or a plurality of resistors among Rf11, Rf12,... Only in a metal wiring layer.

FIG. 23 shows a ninth embodiment, in which the present invention is applied to an amplifier circuit having a wide common-mode input voltage range.
This shows an il type amplifier circuit. According to this, the input amplification stage 2 includes a differential pair including transistors Mp11 and Mp12 and a bias current source Ib2, and includes a first differential amplification circuit having an in-phase input voltage range on the Vss side and transistors Mn11 and Mn12. The second differential amplifier circuit includes a differential pair and a bias current source Ibl and has a common-mode input voltage range on the Vdd side, and a current mirror circuit including transistors Mp14 to Mp17. Thus, the output current of the first differential amplifier circuit and the current output of the second differential amplifier circuit are folded back by the current mirror circuit and added. Here, the transistor Mn1
4, Mn15 operates as an active load.

In the amplifier circuit having the above configuration, when a high input voltage, that is, an input voltage IN on the voltage Vdd side is applied to the input amplifier stage 2, the first differential amplifier circuit including the transistors Mn11 and Mn12 becomes active. . On the other hand, when the input voltage IN is low, that is, on the voltage Vss side, the second differential amplifier circuit becomes active. That is, even if the input voltage IN is on the Vdd side or the Vss side, either one of the first and second differential amplifier circuits operates, so that
An input amplifier stage 2 having a wide input common mode voltage range is realized. In this configuration, the signal path when the input voltage IN is on the Vdd side is longer than the signal path when the input voltage is on the Vss side, which causes a delay time difference.
The delay time difference is small in view of the operating speed of the amplifier circuit for the -Si (Amorphous Silicon) TFT liquid crystal display driving circuit, and the effect of the present invention is not changed.

FIG. 24 shows a rail-to-rail type (rail-to-rail type) in which the present invention is applied to an amplifier circuit having a wide common mode input voltage range.
rail type) A tenth specific example of the amplifier circuit is shown. According to this, the input amplification stage 2 includes the transistors Mp11 and Mp11.
12 and the sources of the differential pairs Mp21 and Mp22 have a common source.
The input signal is applied to the gate of the transistor 12 and the transistor Mp
13 and Mp14 are connected to transistors Mn11 and Mn11, respectively.
n12 is connected to the output of a differential amplifier circuit composed of a differential pair. Further, the transistors Mn11, Mn1
The operating point of the output of the differential amplifier circuit composed of a differential pair of 2 is set to a voltage at which the transistors Mp21 and Mp22 operate.

With this configuration, even when the input voltage approaches the Vdd side and the transistors Mp11 and Mp12 are turned off, Mn
Transistors Mp21 and Mp2 via a differential amplifier circuit composed of a differential pair of transistors 11 and Mn12.
2 operates, the input amplification stage 2 having a wide input common mode voltage range is realized. In this configuration, when the input voltage goes to the Vdd side, the difference between the input voltage and the operation when the input voltage approaches the Vss side is equivalent to the operation when the input voltage approaches the Vss side by the amount of passing through the differential amplifier circuit composed of the differential pair of the transistors Mn11 and Mn12. Although the delay is delayed by the delay time of the dynamic amplifying circuit, the delay time difference is small in view of the operating speed of the normal a-Si TFT liquid crystal display drive circuit amplifying circuit, and the effect of the present invention is not changed.

In the example shown in FIGS. 23 and 24, a−S
Although the amplifier circuit of the iTFT liquid crystal display drive circuit was premised, the amplifier circuit of the Poly-Si TFT liquid crystal display drive circuit drives a plurality of signal lines of the panel in a time-division manner by one amplifier circuit. An amplifier circuit that operates at least 10 times faster than the amplifier circuit of the liquid crystal display drive circuit is required. For this reason, the delay time difference due to the input voltage generated in the input amplifier stage having a wide common-mode input voltage range cannot be ignored, unlike the amplifying circuit for the a-Si TFT liquid crystal display driving circuit, and the phase margin deteriorates. This is because, as shown in FIGS. 25 and 26, the output from the differential amplifier circuit composed of a differential pair of transistors M11 and M12 added to increase the common mode input voltage is output from the output amplifier stage including a capacitive element. In FIG. 25, the time required for the high-frequency signal component to pass through Mp16 and Mp17 by adding the idle-forward path, and FIG.
In this case, the time required to pass through Mp21 and Mp22 can be shortened. As a result, the delay time difference can be reduced.

More specifically, in FIGS. 25 and 26, the bias voltage Vb is applied to the gate of the transistor Mp13 constituting the bias current source of the output amplification stage via the resistor Rff, and the gate of the transistor Mp15 is connected to the transistor Mp13. A feedforward path with a capacitance Cff2 is added to the gate of the gate. Further, the amplifying transistor Mn13 in the output amplifying stage is replaced with transistors Mn13a and Mn13b having a common gate and a cascode configuration, and a connection point between the source of the transistor Mn13a and the drain of the transistor Mn13b is connected to the transistor Mp.
A feedforward path with a capacitance Cff1 is added between the gate and the fourteenth gate. With this configuration, even if the input voltage changes at a high speed, the high-frequency component at the change point is fed forward to the output amplification stage via these capacitive feed-forward paths. The delay time difference due to the input voltage generated in the stage can be reduced.

In FIGS. 25 and 26, the resistor Rff is used to form a feedforward path to the gate of the transistor Mp13. However, as shown in FIG. 27, the on-resistance of the field effect transistor Mff may be used. good.

As shown in FIG. 28, when the input signal voltage fluctuates to the positive side in the amplifier circuit shown in FIG. 26, the output current of the transistor Mp13 that supplies the bias current of the output amplification stage 3 is detected. Increasing bias voltage (V
b) Control circuits can be combined. At this time, as indicated by a dotted line in FIG. 28, a bias current IL2 to be added by detecting that the input signal voltage has changed to the positive side is not directly added to the bias current Ibl of the amplifier circuit, but a feedforward path is provided. Since the voltage IL2 × Rff is applied to the resistor Rff by adding the voltage via the added resistor Rff, the transistor M
The gate-source voltage of p3 can be increased.
That is, when the input signal voltage fluctuates to the positive side, a large output current can be supplied from the transistor Mp13 with a small bias current IL.

In the amplifier circuit shown in FIG. 28, transistors Mn16, Mp32, Mp33, Mp34, current source IL
The bias voltage (Vb) control circuit constituted by I and IL2 detects a large change in the input voltage from a low voltage to a high voltage, detects this, and outputs the output of the transistor Mp13 that supplies the bias current of the output amplification stage 3 to the output voltage. Increase the current. The control circuit includes a differential pair of transistors Mn11 and Mn12 provided to extend the common-mode input voltage range, and an amplifier circuit including an active load of transistors Mp14 to Mp17.
11 and Mp12, and connected to a differential pair of transistors Mpll and Mp12 provided in parallel with the differential pair of Mp12. The output of the differential pair is applied to the gate of the transistor Mn16, which is the input of the control circuit. Therefore, there is a delay before the control circuit operates to increase the output current with respect to the change in the input voltage. This delay is, as shown in FIG. 29, a transistor which is an output of an amplifier circuit constituted by a differential pair formed by transistors Mn11 and Mn12 and an active load formed by transistors Mp14 and Mp17 added to extend the common mode input voltage range. By providing the capacitance Cff3 between the output of Mn12 and the output of the transistor Mn16, which is the output of the input voltage change detection unit, the change in the input voltage is fed forward to the output of the input voltage change detection unit via the capacitance Cff3. Can be relaxed.

FIG. 30 shows the function of the amplifier circuit for the liquid crystal display drive circuit. As shown in FIG. 30, when the common voltage Vcom applied to the common electrode side of the liquid crystal cell is set to a constant voltage, and the signal voltage VRGB is periodically inverted with reference to this voltage Vcom, the liquid crystal display driving circuit is configured as shown in FIG. As shown, a positive D / A converter DA1 for digital-to-analog conversion of an input RGB signal to a voltage more positive than Vcom, and a negative D / A converter for digital-to-analog conversion to a voltage more negative than Vcom DA2 and a two-input amplifier circuit AMP having different input voltage change ranges for amplifying the output voltages of the positive and negative D / A converters are required. The function of the two-input amplifier circuit is that, when the output of one D / A converter is input and amplified, the amplifier circuit that receives the output of the other D / A converter is off. Is required.

FIG. 31 shows a fifteenth embodiment in which the present invention is applied to the above-described two-input amplifier circuits having different input signal voltage ranges. This two-input amplifier circuit has a two-stage amplification stage. The input amplification stage has a positive-side amplifier circuit having a positive-side input signal voltage range with respect to the common voltage Vcom, and a common voltage V
A positive-side amplifier circuit having a negative-side input signal voltage range with respect to com, and a positive-side and negative-side amplifier based on a selection signal POL for selecting whether to output the output of the positive-side or negative-side D / A converter. It is composed of first and second switches SW20 and SW21 for selecting the operation of the circuit.

The positive side amplifier circuit includes transistors Mn41,
A first differential transistor pair constituted by Mn42, a first current source Ib1 for applying a tail current to the first differential transistor pair, and two output terminals of the first differential transistor pair (transistors Mn41 and Mn41). The first current mirror is composed of transistors Mp44 and Mp45 whose current input terminal and current output terminal are connected to the drain of Mn42, respectively. The negative side amplifier circuit is similarly configured by transistors Mp41 and Mp42.
Differential transistor pair, a second current source Ib1 that applies a tail current to the second differential transistor pair, and two output terminals (transistor Mp4) of the second differential transistor pair.
1, the drains of Mp42) are connected to the current input terminal and the current output terminal, respectively.
5 is constituted by a second current mirror.

The first switch SW20 is connected between two output terminals of the first differential transistor pair, and the second switch SW21 is connected between two output terminals of the second differential transistor pair. .

The output amplifying stage includes a transistor Mp4
3, Mn43, and the resistor circuit is constituted by the resistor Rf.

In order to explain the operation of the two-input amplifier circuit shown in FIG. 31, first consider the case where the output of the negative D / A converter is input to the negative amplifier circuit. At this time, the selection signal PO
“0” is given to L, the switch SW20 is on, and the switch SW21 is off. Although the output voltage of the positive-side D / A converter is indefinite, it is higher than the common voltage Vcom. Therefore, even if the gate voltage of the transistor Mn1, that is, the output voltage of the output amplifier stage of the amplifier circuit is lower than Vcom, the transistor Mn42 is in the ON state. Becomes Also, switch S
Since W20 is on, the transistor Mp45 is also diode-connected.

The current supplied from current source Ib1 is supplied to diode-connected transistors Mp44 and Mp via one or both of transistors Mn42 and Mn41.
45, a current generated according to a ratio of twice the size (W / L) of the transistors Mp44 and Mp45 to the size (W / L) of the transistor Mp43 is supplied from the transistor Mp43 as a bias current of the output amplification stage. Is done.

That is, when the output of the negative-side D / A converter is input, the circuit operates in the connection state shown in FIG. This is exactly the same as the circuit connection shown in FIG. 7 except that the way of applying the bias current of the output amplification stage 3 is different.
As described with reference to FIG. 9, it is clear that stable operation can be realized by the resistor Rf without requiring a phase compensation capacitor. Therefore, the chip area required for the phase compensation capacitor can be reduced, and the cost can be reduced.

When inputting the output of the positive D / A converter, a P-channel MOS transistor and an N-channel M
The basic operation is the same as when the output of the negative D / A converter is input, except that the OS transistor is reversed.

Also, by short-circuiting the outputs of the differential transistor pairs of the unused amplifier circuit with a switch, the bias current of the output amplification stage can be easily set.

FIG. 33 shows a sixteenth embodiment of the amplifier circuit according to the modification of FIG. 31. The bias of the output amplifier stage is adaptively applied to the first current mirror of the positive side amplifier circuit by referring to the current of the transistor Mp44. A transistor Mp46 for generating a current for applying a current is added, and a transistor Mn44 is added to the second current mirror of the negative side amplifier circuit.
Transistor Mn4 that generates a current for adaptively applying a bias current of the output amplification stage with reference to the current of
6 has been added.

Further, third and fourth switches SW22 and SW23 for controlling ON / OFF of the current sources Ib1 and Ib2 of the positive side amplifier circuit and the negative side amplifier circuit, and a second current mirror of the first current mirror. The transistor Mp which is a current output terminal
A fifth switch SW24 inserted between the drain of the second current mirror and the current input terminal of the second current mirror; and a transistor M which is a second current output terminal of the second current mirror.
A sixth switch SW26 inserted between the drain of n46 and the current input terminal of the first current mirror is added. The added switches SW22 to SW26 are also controlled by the selection signal POL similarly to the switches SW20 and SW21.

The output amplifying stage includes a transistor Mp4
3, Mn43, and the resistor circuit is constituted by the resistor Rf.

In order to explain the operation of the two-input amplifier circuit shown in FIG. 33, first consider the case where the output of the negative D / A converter is input to the negative amplifier circuit. At this time, the selection signal PO
"0" is given to L, and the switches SW20, SW2
3, SW25 is ON, switches SW21, SW22, S
W24 is off. Since the switch SW22 is off, the current supplied from the current source Ib1 does not flow to the transistors Mn41 and Mn42, and the differential input transistors Mn41 and Mn42 constituting the positive side amplifier circuit.
Is turned off. Also, since the switch SW23 is on, the current supplied from the current source Ib2 flows through the transistors Mp41 and Mp42, and the negative side amplifier circuit operates.

Here, the transistor Mn46 generates a current with reference to the current flowing through the transistor Mn44,
Through the switch SW25 that is turned on, the switch SW20 that is also turned on flows into the diode-connected transistors Mp45 and Mp44, and the size of the transistor Mp44 and Mp45 is twice as large as the size (W / L) of the transistor. A current generated according to the size (W / L) ratio of Mp43 is supplied from the transistor Mp43 as a bias current of the output amplification stage. After all, when the output of the negative D / A converter is input, the amplifier circuit operates in the connection state shown in FIG.

That is, when the amplifier circuit is in a steady state in the connection state of FIG. 34, in other words, when the positive and negative input signal voltages of the negative amplifier circuit are balanced, the bias from the current source Ib2 of the negative amplifier circuit is set. A half of the current is generated according to the ratio (W / L) Mp46 / (W / L) Mp6 of the size (W / L) of the transistors Mn44 and Mn46, which is the size (W / L) of the transistors Mp44 and Mp45. L)
And the size of the transistor Mp43 (W
/ L) is exactly the same as the circuit connection shown in FIG. 7 except that the current amplified according to the ratio is supplied from the transistor Mp3 as the bias current of the output amplification stage, and as described in FIGS. Obviously, stable operation can be realized by the resistor Rf.

In a transient state where the positive input of the negative amplifier circuit is larger than the negative input, the current source Ib
2, the bias current from the output amplifier stage supplied from the transistor Mp43 can be twice as large as that in the steady state. As a result, the rise characteristic determined by the transistor Mp43 and the load capacitance can be doubled without increasing power consumption in a steady state.

Further, in a transient state where the positive input of the negative side amplifier circuit becomes smaller than the negative input, the current source Ib2
All flow through the transistor Mp42 and no longer flow through the transistor Mn44. As a result, the bias current of the output amplification stage supplied from the transistor Mp43 becomes zero, the through current flowing from the transistor Mp43 to the transistor Mn43 is reduced, and low power consumption can be achieved.

When inputting the output of the positive side D / A converter, a P-channel MOS transistor and an N-channel M
The basic operation is the same as when the output of the negative D / A converter is input, except that the OS transistor is reversed.

By providing the resistor Rf as described above,
Stable operation of the amplifier circuit can be realized without the need for a phase compensation capacitor, and not only the chip area can be reduced, but also the transient characteristics of rising and falling can be doubled without increasing power consumption in a steady state. be able to.

FIG. 35 is a diagram showing a configuration in which the amplifier circuit of the present invention is used for a liquid crystal display driving circuit used in the liquid crystal display device shown in FIG.

In the liquid crystal display device shown in FIG. 36, liquid crystal cells 301 are arranged in a matrix, and a plurality of signal lines 304 to which image signals are supplied and a plurality of scanning lines 305 are arranged to intersect. A liquid crystal display panel 300 configured, a liquid crystal display driving circuit 302 for supplying an image signal to a signal line 304 to drive the liquid crystal display panel 300, and a scanning line selection circuit 303 for selectively driving a scanning line 305. Be composed.

As shown in FIG. 35, the display drive circuit includes the same number of latches 222 as the number of pixels required for one horizontal line for storing RGB signals, a shift register 221 for transferring a timing pulse for latching RGB, and a latch 2.
The latch 223 further stores the RGB signal stored at 22 in the cycle of one horizontal period, and the D / D converter converts the RGB signal of one horizontal line stored at the latch 223 into an analog value.
It is composed of an A converter 224 and a drive circuit 225 for receiving the RGB signals converted into analog voltages by the D / A converter 224 and driving the signal lines of the liquid crystal display panel and the liquid crystal cells.

The amplifier circuit 225 is a circuit of a fifteenth embodiment based on the present invention shown in FIG. 31 in this example. FIG.
As described in 1, the amplifier circuit 225 does not require a phase compensation capacitor for stabilizing the operation.

FIG. 35 illustrates an example in which the amplifier circuit of the specific example shown in FIG. 31 is applied to the drive circuit 225. However, an amplifier circuit of another specific example may be used for the drive circuit 225. is there.

In the above embodiments, the amplifier circuit constituted by MOS transistors has been described. However, each transistor may be replaced with a bipolar transistor to constitute an amplifier circuit. In that case, the gate may be replaced by the base, the source by the emitter, the drain by the collector, and W / L by the emitter area.

[0093]

As described above, according to the present invention, in an amplifier circuit having at least an input amplifier stage and an output amplifier stage, a resistor circuit is provided between the output terminal of the output amplifier stage and the signal output terminal of the amplifier circuit. , The phase compensation capacitance, which is essential for stabilization in the conventional amplifier circuit, becomes unnecessary or can be greatly reduced.
When integrated, the chip area can be reduced, the cost can be reduced, and an amplifier circuit that operates stably can be provided at low cost.

Further, by applying the amplifier circuit of the present invention to an integrated liquid crystal display driving circuit, the cost of the liquid crystal display device can be reduced.

In the conventional phase compensation, the pole frequency is proportional to the transconductance of the output amplifying stage for a large-capacity load. Therefore, the phase margin can be improved by increasing the current of the output amplifying stage. The power consumption was increasing. In contrast, in the present invention, the transconductance itself is not directly related to the pole frequency,
Phase compensation can be performed with low power consumption.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of an amplifier circuit according to one embodiment of the present invention.

FIG. 2 is a diagram showing an equivalent circuit of the amplifier circuit of FIG. 1;

FIG. 3 is a diagram illustrating frequency characteristics of gain and phase of the amplifier circuit of FIG. 1;

FIG. 4 is a diagram illustrating an input conversion offset of an amplifier circuit.

FIG. 5 is a diagram illustrating an input conversion offset cancel operation of the amplifier circuit.

FIG. 6 is a diagram showing a change in gain and phase frequency characteristics in an offset detection mode when a phase compensation capacitor is not used in the amplifier circuit of FIG. 1;

FIG. 7 is a diagram showing a first specific example of the amplifier circuit in FIG. 1;

FIG. 8 is a diagram showing a second specific example of the amplifier circuit in which the resistance circuit is realized by the on-resistance of the field effect transistor in FIG. 7;

9 is a diagram showing a third specific example of the amplifier circuit in FIG. 8 in which a field-effect transistor used as an on-resistance also serves as a switch;

FIG. 10 is a diagram for explaining an effect of improving frequency characteristics according to the present invention;

FIG. 11 is a diagram showing the dependence of frequency characteristics on load capacitance.

FIG. 12 is a diagram showing the effect of using a phase compensation capacitor together.

FIG. 13 is a diagram showing the influence of a phase compensation capacitance on frequency characteristics.

FIG. 14 is a diagram showing a fourth specific example of the amplifier circuit to which a switch for turning on and off the phase compensation capacitance is added.

FIG. 15 is a diagram showing a state where a load including a resistance component is connected to the amplifier circuit shown in FIG. 7;

FIG. 16 is a diagram showing the frequency characteristics of FIG.

FIG. 17 is a diagram showing transient characteristics of the amplifier circuit of FIG. 7;

18 is a diagram showing a fifth specific example of the amplifier circuit in which the transient characteristics of the amplifier circuit of FIG. 5 are improved.

FIG. 19 is a diagram showing improved transient characteristics of the amplifier circuit of FIG. 18;

FIG. 20 is a diagram illustrating a sixth specific example in which the amplifier circuit of FIG. 18 is modified;

FIG. 21 is a diagram showing a seventh specific example obtained by modifying the amplifier circuit of FIG. 18;

FIG. 22 is a diagram showing an eighth specific example obtained by modifying the amplifier circuit of FIG. 18;

FIG. 23 is a diagram showing a ninth specific example of an amplifier circuit in which the present invention is applied to an amplifier circuit in an in-phase input voltage range;

FIG. 24 is a diagram showing a tenth specific example of an amplifier circuit in which the present invention is applied to an amplifier circuit in the common-mode input voltage range;

FIG. 25 is a diagram showing an eleventh specific example of the amplifier circuit for increasing the speed of the amplifier circuit of FIG. 23;

FIG. 26 is a diagram showing a twelfth specific example of the amplifier circuit for increasing the speed of the amplifier circuit of FIG. 24;

FIG. 27 is a diagram showing a thirteenth specific example of the amplifier circuit using the field-effect transistor used as the on-resistance in FIG. 26;

FIG. 28 is a diagram showing a fourteenth specific example according to a modified example of the amplifier circuit of FIG. 26 in which the transient characteristics are improved.

FIG. 29 is a diagram illustrating a fifteenth specific example according to another modified example of the amplifier circuit in FIG. 26 in which the transient characteristics are improved.

FIG. 30 is a view for explaining functions necessary for the amplifier circuit of the liquid crystal display drive circuit when the common electrode voltage Vcom is kept constant.

FIG. 31 is a diagram showing a sixteenth specific example of the two-input amplifier circuit having different input signal voltage ranges according to the present invention;

FIG. 32 illustrates the operation of the amplifier circuit in FIG. 31;

FIG. 33 is a diagram showing a seventeenth specific example of an amplifier circuit according to a modification of the amplifier circuit of FIG. 31;

FIG. 34 illustrates the operation of the amplifier circuit in FIG. 33.

FIG. 35 is a diagram showing a liquid crystal display driving circuit to which the amplifier circuit of FIG. 33 is applied.

FIG. 36 illustrates a configuration of a liquid crystal display device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Amplification circuit 2 ... Input amplification stage 3 ... Output amplification stage 4 ... Resistance circuit 221 ... Shift register 222, 223 ... Latch circuit 224 ... D / A converter 225 ... Drive circuit 300 ... Liquid crystal display 301 ... Liquid crystal cell 302 ... Liquid crystal Display drive circuit 303 Scanning line selection circuit 304 Signal line 305 Scanning line Mp ~ ... N-channel MOS transistor Mn ~ ... P-channel MOS transistor gm ~ ... Transconductance of each amplification stage vi ... Input signal voltage of amplification circuit v1 ... Output voltage of input amplifier stage v2 ... Output voltage of output amplifier stage vo ... Output signal voltage of amplifier circuit Vcom ... Voltage of common electrode of liquid crystal display I ~ ... Current source Vdd ... First power supply potential point Vss ... Second power supply Potential point Cf: phase compensation capacitance C1: capacitance component CL attached to the output terminal of the input amplification stage CL1, CL2: Load capacitance component R1: Parallel resistance of output resistance of input amplification stage and input resistance of output amplification stage R2: Output resistance of output amplification stage Rf ~: Resistance for stabilization RL: Resistance component of load IN +, IN-: Signal input terminal of amplifier circuit OUT: Signal output terminal of amplifier circuit

Claims (18)

[Claims] An amplifier circuit for driving a capacitive load, comprising: a plurality of amplifier stages having at least an input amplifier stage and an output amplifier stage cascaded between a signal input terminal and a signal output terminal of the amplifier circuit; An amplifier circuit comprising: a resistor circuit including at least one resistor inserted between an output terminal of the output amplifier stage and the signal output terminal. 2. An amplifier circuit for driving a capacitive load, comprising: a plurality of amplifier stages having at least an input amplifier stage and an output amplifier stage cascaded between a signal input terminal and a signal output terminal of the amplifier circuit; A resistance circuit including a plurality of resistors inserted between an output terminal of the output amplification stage and the signal output terminal, wherein the resistance circuit is at least one of the output amplification stages selected from the plurality of resistors And an amplifier circuit connected between the signal output terminal. 3. The amplifier circuit according to claim 1, further comprising a feedback path for performing feedback from an output terminal of said output amplification stage to an input terminal of said input amplification stage. 4. The frequency of a second pole appearing in the open loop frequency characteristic of the amplifier circuit is lower than the frequency at which the gain of the amplifier circuit becomes 1, and the frequency of the first zero point appearing in the open loop frequency characteristic is The amplifier circuit according to any one of claims 1 to 3, wherein the gain of the amplifier circuit is lower than a frequency at which the gain becomes 1. 5. The amplifier circuit according to claim 1, wherein a feedback path including a capacitance is provided between input and output terminals of the output amplification stage.
5. The amplifier circuit according to any one of items 4 to 4. 6. The amplifying circuit inputs an input signal voltage that changes every predetermined period to the signal input terminal, and a time constant of the resistive circuit and a capacitive component of the capacitive load is equal to the predetermined constant. The amplifier circuit according to any one of claims 1 to 5, wherein the period is not more than 1/5 of the period. 7. The amplifier circuit according to claim 6, wherein a resistance value of said resistance circuit is 50 kΩ or less. 8. The amplifier according to claim 2, wherein the resistance circuit comprises a plurality of resistors and a plurality of switches, and a resistance value of the resistance circuit is set by turning on / off the switches. circuit. 9. The resistance circuit according to claim 1, wherein said resistance circuit is constituted by an on-resistance of a field effect transistor.
9. The amplifier circuit according to any one of 8. 10. The amplifying circuit further includes means for detecting that an input signal voltage input to the signal input terminal has changed to a predetermined polarity and controlling a bias current of the output amplifying stage. The amplifier circuit according to any one of claims 1 to 9, wherein 11. The input amplifying stage has a positive side amplifying circuit and a negative side amplifying circuit for inputting first and second input signals respectively changing to a positive side and a negative side with respect to a predetermined common voltage. The positive-side amplifier circuit includes: a first differential transistor pair that inputs the first input signal; a first current source that supplies a tail current of the first differential transistor pair; A first current mirror in which a current input terminal and a current output terminal are respectively connected to two output terminals of the differential transistor pair, and a first current mirror provided between two output terminals of the first differential transistor pair. Wherein the negative side amplifier circuit includes a second differential transistor pair for inputting the second input signal, and a first current source for providing a tail current of the second differential transistor pair. And the second differential transistor A second current mirror in which a current input terminal and a current output terminal are respectively connected to two output terminals of the data pair; a second switch provided between two output terminals of the second differential transistor pair; When the first input signal is input to the positive side amplifier circuit, the first switch is controlled to be in an off state and the second switch is controlled to be in an on state, and the second input signal is controlled. When a signal is input to the negative side amplifier circuit, the first switch is controlled to be in an on state and the second switch is controlled to be in an off state. The complementary stage is constituted by a pair of complementary transistors commonly connected to an output terminal of the amplification stage, and one gate or base of the pair of complementary transistors is connected to one of the positive side amplifier circuits. 11. The power supply terminal according to claim 1, wherein the other gate or the base of the complementary transistor pair is connected to one output terminal of the negative side amplifier circuit. Amplifier circuit. 12. The input amplifying stage has a positive side amplifying circuit and a negative side amplifying circuit for inputting first and second input signals respectively changing to a positive side and a negative side with respect to a predetermined common voltage. The positive-side amplifier circuit includes: a first differential transistor pair that inputs the first input signal; a first current source that supplies a tail current of the first differential transistor pair; And a first current mirror in which a current input terminal and a first current output terminal are respectively connected to two output terminals of the differential transistor pair, and two output terminals of the first differential transistor pair. A first switch, and a third switch for turning on / off the first current source, wherein the negative side amplifier circuit includes a second differential transistor pair for inputting the second input signal. And the second differential transistor pair A first current source for providing a tail current, a second current mirror having a current input terminal and a first current output terminal connected to two output terminals of the second differential transistor pair, respectively, A second switch provided between two output terminals of the differential transistor pair, and a fourth switch for turning on / off the second current source. A second current output terminal is connected to a current input terminal of the second current mirror via a fifth switch, and a second current output terminal of the second current mirror is connected to the second current mirror via a sixth switch. Connected to a current input terminal of a first current mirror, and when the first input signal is input to the positive side amplifier circuit, the first, fourth, and sixth switches are turned off; Second, third and fifth switches When the second input signal is input to the negative side amplifier circuit, the first, fourth, and sixth switches are turned on, and the second, third, and second switches are turned on. A fifth switch is controlled to be in an off state, and the output amplification stage is constituted by a pair of complementary transistors each having a drain or a collector commonly connected to an output terminal of the output amplification stage. One gate or base is connected to one output terminal of the positive-side amplifier circuit, and the other gate or base of the complementary transistor pair is connected to one output terminal of the negative-side amplifier circuit. The amplifier circuit according to claim 1. 13. The input amplification stage includes a first input circuit including a transistor of a first conductivity type to which the signal input terminal is connected, and a second conductivity type to which the signal input terminal is connected. And a second input circuit including at least one transistor, and a feedforward path including at least a capacitive element from a drain or a source of the first or second transistor to the output amplification stage. Amplifier circuit. 14. The output amplification stage includes first and second transistors having a gate for receiving a signal, a drain of the first transistor is connected to the signal output terminal, and A source and a drain of the second transistor are connected, and the second
14. The amplifier circuit according to claim 13, wherein a source of the transistor is connected to a first power supply, and the feedforward signal path is connected to a connection node between a source of the first transistor and a drain of the second transistor. 15. A current source for supplying a bias current to said output amplifier stage, comprising a resistor and a third transistor having a gate to which a bias voltage is applied via said resistor, wherein said resistor is 14. The amplifier circuit according to claim 13, wherein the foot forward signal path is connected to a connection node between a gate of the third transistor and a gate of the third transistor. 16. A means for detecting a change in an input signal voltage inputted to said signal input terminal to a predetermined polarity and outputting said bias voltage for controlling a bias current of said output amplification stage. 2. The amplifier circuit according to 1. 17. The amplifier circuit according to claim 15, wherein said resistance element is constituted by a field effect transistor having a predetermined on-resistance. 18. A liquid crystal display in which a plurality of pixels, a signal line for selectively applying a signal voltage corresponding to an image signal to each of the pixels, and a scanning line intersecting with the signal line are formed. A driving circuit that drives a signal line according to an image signal, and a selection circuit that sequentially selects the scanning line, wherein the driving circuit has the amplification circuit according to any one of claims 1 to 17. A liquid crystal display device characterized by the above-mentioned.