JPH1116348A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable reduction of address signal lines to realize high integration density and prevent increase in chip size by providing, in the row address decoder or column address decoder side, a first address latch circuit for latching an internal address signal to be output from an address input buffer. SOLUTION: A latch circuit LTH consisting of 13 unit-latches of the single end type of 13 bits output respectively from address input buffers ABF0 to ABF12 is provided to redundant circuits RDD0 to RDD3 and row address decoders RDEC0 to RDEC3. The latch circuit LTH of each bank selectively executes the latch operation with the bank selection signals RAEB0 to RAEB3 formed by decoding the bank address signal in the timing control signal. The address signal line ADL up to each bank from the address input buffers ABF0 to ABF12 is used in common by four banks 0 to 3 to prevent increase of address signal line due to the use of many banks.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory technology and a technology effective when applied to an address signal fetching method in a semiconductor memory device, for example, a technology effective for use in a clock synchronous semiconductor memory device.

[0002]

2. Description of the Related Art In a semiconductor memory device such as a synchronous dynamic RAM (hereinafter abbreviated as a synchronous DRAM), a memory array is constituted by a unit called a plurality of banks, and data reading and writing are externally input. Some are configured to be performed by a command (read command or write command). In addition,
Here, the command refers to a combination of external input control signals such as a chip select signal CS, a row address strobe signal RAS, a column address strobe signal CAS, and a write enable signal WE. The command (code) supplied from the microprocessor to a peripheral device (such as a CRT controller) has a slightly different property.

[0003]

In the above-mentioned synchronous DRAM of the bank type, the number of address latch circuits corresponding to the banks is provided so that continuous data is sequentially allocated to different banks for writing and at the time of data reading. By accessing different banks one after another,
Data can be read / written at a higher speed than when data is continuously written to the same bank or data is continuously read from the same bank.

FIG. 7 shows a configuration in a case where a memory array is composed of four banks in a 256-Mbit memory. In the example shown, four row address latch circuits are provided for each bit of the address signal corresponding to the four banks. Note that reference numerals ABF0 to ABF12
Are indicated by the address buffer circuit and the LT
a, LTb, LTc, LTd} are row address latch circuits provided four by four for each address buffer. The column address is input to the address buffers ABF0 to ABF12 from the same address terminal as the row address in the address multiplex system, and is configured to be latched by a column address latch circuit (not shown).

As shown in FIG. 7, row address latch circuits LTa, LTb, LTc, and LTd} are provided near address buffers ABF0 to ABF12, and redundant circuits RDD0 to RDD3 and row decoder RDEC0 of each memory bank are provided. ~ RDEC3 is supplied with a 13-bit address signal by a signal line in a complementary signal format, and 104 address signal lines (= 13 × 4 × 2) are required, and these signal lines are provided in the chip. Since the wirings are routed over a relatively long distance, the area occupied by the signal lines increases, which causes a problem that the chip size increases. This problem becomes more remarkable when the number of banks further increases as the memory capacity increases.

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the number of address signal lines in a semiconductor memory device in which a memory array section is composed of a plurality of banks, thereby achieving high integration and preventing an increase in chip size. It is to provide a simple semiconductor memory device.

Another object of the present invention is to provide a semiconductor memory device with low power consumption.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, an address latch circuit is provided in each of the address decoding section and the redundant circuit section on each bank side. Thus, the address signal lines from the address input buffer circuit to each bank can be shared by a plurality of banks, and an increase in the number of address signal lines due to the increase in the number of banks can be prevented.

Furthermore, in the address multiplex type semiconductor memory device, an address latch circuit is provided on the address input buffer side together with the address decode circuit and the address latch circuit on the redundant circuit section side. This prevents a change in the address signal line shared by a plurality of banks, that is, charging / discharging, when taking in one of the row address signal or the column address signal and then taking in the other address signal, thereby reducing power consumption. Can be achieved.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a synchronous dynamic RAM to which the present invention is applied.

In FIG. 1, 10A, 10B, 10C,
10D is a memory array configured as four banks BANK0 to BANK3 each having a storage capacity of, for example, 16 Mbits, and 11A and 11B are a row address (row address) signal and a column address (column) input from the outside in a time division manner. An address input buffer circuit for amplifying and waveform-shaping an address signal and supplying the amplified signal to a predetermined internal circuit. Reference numeral 12 denotes a refresh counter for generating an address for refreshing a memory cell. Also, 1
Rows 3A, 13B, 13C, and 13D decode the internal complementary address signal supplied from the address input buffer circuit 11A or the refresh counter 12 and select a corresponding word line in the memory arrays 10A, 10B, 10C, and 10D. A decoder and a redundant circuit.

Reference numeral 14 denotes a column address counter for generating a continuous column address necessary for reading / writing a plurality of bytes of data based on a column address input from the outside. Reference numerals 15A, 15B, 15C, and 15D denote a column address counter from the column address counter 14. The supplied internal address signal is decoded and the memory arrays 10A, 10B, 10C,
A column decoder for selecting a corresponding bit line in 10D, 16A, 16B, 16C and 16D are sense amplifiers for amplifying data read to the bit lines, and a plurality of bit lines are commonly connected via a column switch. I /
O bus.

A data input buffer circuit 17 receives a write data signal and supplies it to the memory arrays 10A to 10D via the sense amplifier & I / O buses 16A to 16D. A reference numeral 18 denotes the sense amplifier & I / O bus 16A. Through the memory arrays 10A through 10D
A data output buffer circuit for outputting the data read from D to the outside, and a timing control circuit 19 for forming a timing signal to be supplied to the internal circuit based on various control signals and clock signals input from the outside.

The control signal input from the outside to the memory of this embodiment is, for example, a control signal for controlling not to supply the input clock to an internal circuit in order to reduce power consumption, in addition to the synchronization clock signal CLK. A clock enable signal CKE, a chip selection signal / CS for indicating that the memory is selected, a row address strobe signal / RAS for giving a timing for taking a row address into the address input buffer 11A, and a column address taking timing , A write control signal / WE for indicating that writing is valid, and a control signal DQM for requesting that a predetermined bit of data not be read or written be masked. Etc. Note that a control signal in which “/” (“−” above the sign in the figure) precedes each sign indicates that the low level is an effective level.

In this embodiment, 2-bit bank address signals BA0 and BA1 indicating which one of the memory arrays 10A to 10D, that is, the banks BANK0 to BANK3 are selected, are input to the timing control circuit 19, By decoding address signals BA0 and BA1, bank select signals RAEB0-RAEB are provided at a predetermined timing according to the command at that time.
3 to form the row decoder and redundant circuit 13A.
To 13D.

In the memory of this embodiment, although not particularly limited, the number of address pins is 13 from A0 to A12, the row address signal is 13 bits from A0 to A12, and the column address signal is 12 bits from A0 to A11. Have been.

FIG. 2 shows a main part of the first embodiment of the present invention. In the figure, ABF0 to ABF12 are 1
Address input buffers RDD0, RDD1, RDD2 provided for the three address pins A0 to A12.
RDD3 is a bank 0 of each of the memory arrays 10A to 10D.
A redundant circuit for repairing a defective bit provided corresponding to 3;
RDEC0, RDEC1, RDEC2, and RDEC3 are row address signal decoders provided for the banks 0 to 3, respectively.

In this embodiment, each of the above redundant circuits RDD0
To RDD3 and row decoders RDEC0 to RDEC3
Address input buffers ABF0 to ABF12, respectively.
And a latch circuit LTH including 13 unit latches for latching a 13-bit single-ended internal address signal output from the internal memory. The latch circuit LTH of each bank is provided with the bank control signals RAEB0 to RAEBR formed by decoding the bank address signals BA0 and BA1 in the timing control circuit 19.
The AEB 3 is configured to selectively perform a latch operation.

More specifically, the synchronous DRAM of this embodiment
When a predetermined command called a bank active command is input to the timing control circuit 19, the address signal input to the address pins A0 to A12 at that time is regarded as a row address and the bank address signal BA
0, BA1 redundancy circuits RDD0-RD of the bank corresponding to BA1
D3 and the latch circuits LTH in the row decoders RDEC0 to RDEC3 are latched. Row decoder RDEC
When the row address is latched in any one of the latch circuits LTH of 0 to RDEC3, the row address is decoded by the row decoder RDEC, and the corresponding one word line in the bank is set to the selected level.

When the row address is latched by the latch circuit LTH in one of the redundant circuits RDD0 to RDD3, the latched address is supplied to a comparator (not shown) and is set in advance by using a fuse or the like. The memory address is compared with the defective address, and if they match, the normal memory row is replaced with a spare memory row.

In this embodiment, the address input buffer A
Since the address signal lines ADL from BF0 to ABF12 to each bank can be shared by the four banks 0 to 3, it is possible to prevent an increase in the number of address signal lines due to the increase in the number of banks. That is, in the system of FIG. 7, 104 address signal lines are required for four banks, but in the above embodiment, only 13 address signal lines are required.

FIG. 3 shows a configuration example of the latch circuit LTH. INV1 is an inverter for inputting address signals RA0 to RA12, INV2 and INV3 are signal holding inverters whose input and output terminals are coupled to each other, and inverters INV1 and INV2 are so-called clocked inverters. . INV4, I
NV5 is a serial inverter that forms a control clock for the clocked inverters INV1 and INV2 based on the latch timing signals RAEB0 to RAEB3 supplied from the timing control circuit 19, INV6 is an inverter that inverts a holding signal, G2 is an output NOR gate, which is configured to output a signal of a complementary type of true (true level) and bar (pseudo level).

In the above embodiment, the redundant circuit RDD0
To RDD3 also have row decoders RDEC0 to RDEC0.
Although it has been described that the number of latch circuits LTH equal to the number of bits of the row address signal is provided similarly to C3, instead of latching the row address signal, the input row address and the set defective address are compared with a comparator. May be configured to latch the comparison result. Thus, when the number of replaceable memory rows is smaller than the number of bits of the row address signal, the number of latch circuits LTH in each redundant circuit can be reduced as compared with the above embodiment.

FIG. 4 shows a main part of a second embodiment of the present invention. This embodiment is different from the first embodiment in that
Latch circuits LTh0 to LTh12 for latching row addresses also on the address input buffers ABF0 to ABF12 side
Is provided. This prevents the address signal line ADL shared by the four banks BANK0 to BANK3 from being charged and discharged due to the switching of the address signal when the column address signal is fetched after fetching the row address signal. Thus, power consumption can be reduced.

In particular, the synchronous DRAM has an operation mode called a burst mode in which one word line is selected by a row address and only the column address is continuously changed to perform reading. If the signal line for supplying the row address signal to the bank fluctuates during the burst mode, the power consumption increases accordingly. However, in this embodiment, the power consumption due to such a change in the column address is undesired. There is an advantage that the increase can be prevented.

Further, in this embodiment, an address signal is sent from the latch circuits LTh0 to LTh12 on the input buffer side to the bank as a single-ended signal instead of a complementary signal, and a complementary signal is formed by the latch circuit LTH on the bank. With such a configuration, an attempt is made to reduce the number of row address signal lines.

In the embodiment of FIG. 3, a latch circuit for latching a row address is provided in each of the address input buffers ABF0 to ABF12, the redundancy circuit on each bank side, and the row decoder. Even when the latch circuits LTh0 to LTh12 for latching the row address are provided only on the buffers ABF0 to ABF12 side, the effect of reducing the power consumption can be obtained.

FIG. 5 shows the latch circuits LTh0 to LTh1.
2 is shown. Latch circuit L of this embodiment
Since Th0 to LTh12 do not need to output a complementary signal unlike the latch circuit of FIG.
1, G2 and the holding signal inverting inverter INV6 are omitted, and the address signal RAi input inverter INV1 is omitted.
, The signal holding inverters INV2 and INV3, and the latched timing signal RBA supplied from the timing control circuit 19, based on the clocked inverter IV2.
It is composed of serial inverters INV4 and INV5 that form control clocks for NV1 and INV2.

The latch timing signal RBA is formed based on a bank active command. In FIG.
The relationship between the bank active command ACTV and the latch timing signals RBA and RAEB and the timing of fetching a row address by these signals are shown.
When the bank active command ACTV is taken into the timing control circuit 19 in synchronization with the rise (t1) of the clock signal CLK, the latch timing signal RB
A is changed to a high level, and based on this, the row address signals RA0 to RA12 input to the address pins A0 to A12 at that time are latched by the latch circuits LTh0 to LTh12.
Latched.

At this time, based on the bank addresses BA0 and BA1 input to the timing control circuit 19, any one of the timing signals RAEB0 to RAEB3 for giving the address latch timing of the bank changes to a high level. Then, the row address is taken into the latch circuit LTH on the bank side. by this,
One word line in the selected bank is changed to the selected level.

Thereafter, when the read command READ is taken into the timing control circuit 19 (t2), the column address signals CA0 to CA11 input to the address pins A0 to A12 at that time are changed to the column decoder 1 on the bank side.
Latched by a latch circuit (not shown) in 5A. Even if the address signal input to the address pins A0 to A12 changes from the row address signal to the column address signal as described above, the row address latch timing signal RBA has already been set to the low level at that time. Is transmitted to the row decoders 13A to 13D without change, that is, the address signal line ADL is not charged / discharged, so that unnecessary current consumption can be prevented from flowing. Note that the latch timing signals RAEB0 to RAEB0
RAEB3 is a precharge command P for precharging the data line to a potential such as Vcc / 2 thereafter.
At the time point (t3) when C is input, it is changed to the low level.

In each of the above embodiments, the case where the row address is latched has been described. However, the column address is also stored in the bank-side column decoder 15A (see FIG. 1) and the address input buffers ABF0 to ABF1.
A latch circuit may be provided on both the second side and the bank side.

As described above, in the above embodiment, the address latch circuit is provided in each of the address decode section and the redundant circuit section on each bank side, so that the address signal lines from the address input buffer circuit to each bank are provided. This can be shared by a plurality of banks, so that an increase in the number of address signal lines due to the increase in the number of banks can be avoided, and an effect of achieving high integration can be achieved.

Further, since the address latch circuit is provided on the address input buffer side together with the address latch circuit on the side of the address decode section and the redundant circuit section, when the row address signal is fetched and then the column address signal is fetched, There is an effect that a change in the row address signal line shared by a plurality of banks, that is, charging / discharging is prevented, and power consumption can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say. For example, in the above-described embodiment, a case has been described in which the row address decoder side is provided with a redundant circuit that replaces a memory row including a defective bit with a spare memory row. The present invention can also be applied to a case where a redundant circuit for replacing the memory row is provided.

In the above embodiment, the case where the memory array is composed of four banks has been described. However, the present invention can be applied to the case where the memory array is composed of eight banks, sixteen banks, and the like. The effectiveness of the invention is increased. Further, address pins and input buffers are also used in the thirteenth embodiment.
The number is not limited to the number, and may be an arbitrary number according to the storage capacity.

Further, the command method in the memory of the embodiment is a method in which a command is given by a combination of control signals input from the outside, but is configured such that the command is given by a method like a command code in a microcomputer system. May be a memory that has been used.

In the above description, the case where the invention made by the present inventor is mainly applied to a synchronous DRAM, which is the field of application as the background, has been described. However, the present invention is not limited to this, and is not limited to the DRAM. The present invention can be generally used for a semiconductor memory and a semiconductor integrated circuit having a built-in memory.

[0041]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in a semiconductor memory device in which a memory array section is composed of a plurality of banks, the number of address signal lines can be reduced, thereby preventing high integration and an increase in chip size and power consumption. Semiconductor memory device with less noise can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronous dynamic RAM as an example of a semiconductor memory device suitable for applying the present invention.

FIG. 2 is a block diagram showing a main part (row address latch system) of the first embodiment of the present invention.

FIG. 3 is a logic circuit diagram showing an example of an address latch circuit on the bank side.

FIG. 4 is a block diagram showing a main part (row address latch system) of a second embodiment of the present invention.

FIG. 5 is a logic circuit diagram showing an example of an address latch circuit on the input buffer side.

FIG. 6 is a timing chart showing a relationship between a command input timing and an address signal latch timing.

FIG. 7 is a block diagram showing a row address latch method in a conventional synchronous DRAM.

[Explanation of symbols]

 10A to 10D Memory array (bank) 11A, 11B Address input buffer circuit 12 Refresh counter 13A to 13D Row decoder & redundant circuit 14 Column address counter 15A to 15D Column decoder 16A to 16D Sense amplifier & I / O bus 17 Data input buffer circuit 18 Data output buffer circuit 19 Timing control circuit LTH, LTh Latch circuit ADL Address signal line RDEC Row address decoder RDD Redundant circuit

Claims (6)

[Claims] 1. A plurality of memory arrays, a row address decoder and a column address decoder provided for each memory array, and an address for supplying an address signal input from an external terminal to the row address decoder and the column address decoder. A semiconductor memory device provided with an input buffer, wherein a first address latch circuit for latching an internal address signal output from the address input buffer is provided on the row address decoder or column address decoder side. Semiconductor storage device. 2. A second address latch for replacing a defective bit with a spare bit corresponding to each of said memory arrays, and latching an address signal output from said address input buffer in said redundant circuit. 2. The semiconductor memory device according to claim 1, further comprising a circuit. A third address latch circuit for latching an address signal output from the address input buffer on the side of the address input buffer, wherein an internal address signal from the third address latch circuit is converted into a single-ended signal. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is configured to be supplied to the row address decoder and the column address decoder. 4. A timing signal formed on the basis of an address signal input for designating any one of the plurality of memory arrays, wherein the first address latch circuit and the second address latch circuit are provided. 2. An address signal latch according to claim 1,
4. The semiconductor memory device according to 2 or 3. 5. The method according to claim 1, wherein the row address signal and the column address signal are input from the same address terminal in a time division manner, and the first address latch circuit is provided corresponding to the row address decoder. The semiconductor memory device according to claim 1, 2, 3, or 4, wherein 6. The first address based on a clock input terminal, a clock signal input to the clock input terminal, and an address signal input to specify one of the plurality of memory arrays. 6. A timing control circuit for forming a latch timing signal for giving a latch timing to a latch circuit and a second address latch circuit.
3. The semiconductor memory device according to claim 1.